diff options
Diffstat (limited to 'sim/mips/dv-tx3904cpu.c')
| -rw-r--r-- | sim/mips/dv-tx3904cpu.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/sim/mips/dv-tx3904cpu.c b/sim/mips/dv-tx3904cpu.c index 56b3386..cf9399a 100644 --- a/sim/mips/dv-tx3904cpu.c +++ b/sim/mips/dv-tx3904cpu.c @@ -141,7 +141,7 @@ deliver_tx3904cpu_interrupt (struct hw *me, struct tx3904cpu *controller = hw_data (me); SIM_DESC sd = hw_system (me); sim_cpu *cpu = STATE_CPU (sd, 0); /* NB: fix CPU 0. */ - address_word cia = CIA_GET (cpu); + address_word cia = CPU_PC_GET (cpu); #define CPU cpu #define SD current_state @@ -149,20 +149,20 @@ deliver_tx3904cpu_interrupt (struct hw *me, if (controller->pending_reset) { controller->pending_reset = 0; - HW_TRACE ((me, "reset pc=0x%08lx", (long) CIA_GET (cpu))); + HW_TRACE ((me, "reset pc=0x%08lx", (long) CPU_PC_GET (cpu))); SignalExceptionNMIReset(); } else if (controller->pending_nmi) { controller->pending_nmi = 0; - HW_TRACE ((me, "nmi pc=0x%08lx", (long) CIA_GET (cpu))); + HW_TRACE ((me, "nmi pc=0x%08lx", (long) CPU_PC_GET (cpu))); SignalExceptionNMIReset(); } else if (controller->pending_level) { HW_TRACE ((me, "interrupt level=%d pc=0x%08lx sr=0x%08lx", controller->pending_level, - (long) CIA_GET (cpu), (long) SR)); + (long) CPU_PC_GET (cpu), (long) SR)); /* Clear CAUSE register. It may stay this way if the interrupt was cleared with a negative pending_level. */ |