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-rw-r--r--sim/mcore/interp.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/sim/mcore/interp.c b/sim/mcore/interp.c
index 48d9ff8..7561c44 100644
--- a/sim/mcore/interp.c
+++ b/sim/mcore/interp.c
@@ -757,7 +757,7 @@ step_once (SIM_DESC sd, SIM_CPU *cpu)
break;
case 0x0B: /* lsr */
{
- unsigned long dst, src;
+ uint32_t dst, src;
dst = gr[RD];
src = gr[RS];
/* We must not rely solely upon the native shift operations, since they
@@ -1060,7 +1060,7 @@ step_once (SIM_DESC sd, SIM_CPU *cpu)
case 0x3E: case 0x3F: /* lsrc, lsri */
{
unsigned imm = IMM5;
- unsigned long tmp = gr[RD];
+ uint32_t tmp = gr[RD];
if (imm == 0)
{
NEW_C (tmp);