diff options
Diffstat (limited to 'sim/igen/gen-engine.c')
-rw-r--r-- | sim/igen/gen-engine.c | 46 |
1 files changed, 23 insertions, 23 deletions
diff --git a/sim/igen/gen-engine.c b/sim/igen/gen-engine.c index 4b6861e..ee27e68 100644 --- a/sim/igen/gen-engine.c +++ b/sim/igen/gen-engine.c @@ -98,21 +98,21 @@ print_run_body (lf *file, if (!options.gen.smp) { - lf_putstr (file, " -/* CASE 1: NO SMP (with or with out instruction cache). - -In this case, we can take advantage of the fact that the current -instruction address (CIA) does not need to be read from / written to -the CPU object after the execution of an instruction. - -Instead, CIA is only saved when the main loop exits. This occures -when either sim_engine_halt or sim_engine_restart is called. Both of -these functions save the current instruction address before halting / -restarting the simulator. - -As a variation, there may also be support for an instruction cracking -cache. */ - + lf_putstr (file, "\ +/* CASE 1: NO SMP (with or with out instruction cache).\n\ +\n\ +In this case, we can take advantage of the fact that the current\n\ +instruction address (CIA) does not need to be read from / written to\n\ +the CPU object after the execution of an instruction.\n\ +\n\ +Instead, CIA is only saved when the main loop exits. This occures\n\ +when either sim_engine_halt or sim_engine_restart is called. Both of\n\ +these functions save the current instruction address before halting /\n\ +restarting the simulator.\n\ +\n\ +As a variation, there may also be support for an instruction cracking\n\ +cache. */\n\ +\n\ "); lf_putstr (file, "\n"); @@ -215,14 +215,14 @@ cache. */ if (options.gen.smp) { - lf_putstr (file, " -/* CASE 2: SMP (With or without ICACHE) - -The complexity here comes from needing to correctly halt the simulator -when it is aborted. For instance, if cpu0 requests a restart then -cpu1 will normally be the next cpu that is run. Cpu0 being restarted -after all the other CPU's and the event queue have been processed */ - + lf_putstr (file, "\ +/* CASE 2: SMP (With or without ICACHE)\n\ +\n\ +The complexity here comes from needing to correctly halt the simulator\n\ +when it is aborted. For instance, if cpu0 requests a restart then\n\ +cpu1 will normally be the next cpu that is run. Cpu0 being restarted\n\ +after all the other CPU's and the event queue have been processed */\n\ +\n\ "); lf_putstr (file, "\n"); |