aboutsummaryrefslogtreecommitdiff
path: root/sim/d10v
diff options
context:
space:
mode:
Diffstat (limited to 'sim/d10v')
-rw-r--r--sim/d10v/ChangeLog5
-rw-r--r--sim/d10v/simops.c12
2 files changed, 13 insertions, 4 deletions
diff --git a/sim/d10v/ChangeLog b/sim/d10v/ChangeLog
index a5f9e99..d801cb2 100644
--- a/sim/d10v/ChangeLog
+++ b/sim/d10v/ChangeLog
@@ -1,3 +1,8 @@
+Tue Dec 2 15:01:08 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * simops.c (OP_3A00): For "macu", perform multiply stage using 32
+ bit rather than 16 bit precision.
+
Tue Dec 2 11:04:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
* simops.c (OP_1000): For "sub2w", compute carry by comparing
diff --git a/sim/d10v/simops.c b/sim/d10v/simops.c
index d617cb4..6f12e5a 100644
--- a/sim/d10v/simops.c
+++ b/sim/d10v/simops.c
@@ -1352,13 +1352,17 @@ OP_1A00 ()
void
OP_3A00 ()
{
- int64 tmp;
+ uint64 tmp;
+ uint32 src1;
+ uint32 src2;
trace_input ("macu", OP_ACCUM, OP_REG, OP_REG);
- tmp = SEXT40 (State.regs[OP[1]] * State.regs[OP[2]]);
+ src1 = (uint16) State.regs[OP[1]];
+ src2 = (uint16) State.regs[OP[2]];
+ tmp = src1 * src2;
if (State.FX)
- tmp = SEXT40( (tmp << 1) & MASK40);
- State.a[OP[0]] = (SEXT40 (State.a[OP[0]]) + tmp) & MASK40;
+ tmp = (tmp << 1);
+ State.a[OP[0]] = (State.a[OP[0]] + tmp) & MASK40;
trace_output (OP_ACCUM);
}