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Diffstat (limited to 'sim/d10v/ChangeLog')
| -rw-r--r-- | sim/d10v/ChangeLog | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/sim/d10v/ChangeLog b/sim/d10v/ChangeLog index 7c884fb..ca21f30 100644 --- a/sim/d10v/ChangeLog +++ b/sim/d10v/ChangeLog @@ -1,3 +1,18 @@ +Mon Oct 27 14:43:33 1997 Fred Fish <fnf@cygnus.com> + + * (dmem_addr): If address is illegal or in I/O space, signal a bus + error. Allocate unified memory on demand. Fix DMEM address + calculations. + +Mon Feb 16 10:27:53 1998 Andrew Cagney <cagney@b1.cygnus.com> + + * simops.c (OP_5F20): Implement "dbt". + (OP_5F60): Implement "rtd". + + * d10v_sim.h (DPC_CR): Define enum. + (DBT_VECTOR_START): Define + (DPSW, DPC): Define. + Fri Feb 13 15:15:58 1998 Andrew Cagney <cagney@b1.cygnus.com> * simops.c (move_to_cr): Sync regs[SP_IDX] with State.sp according |