1 files changed, 60 insertions, 1 deletions
diff --git a/sim/cris/crisv10f.c b/sim/cris/crisv10f.c
index 0c2a17c..976badb 100644
--- a/sim/cris/crisv10f.c
+++ b/sim/cris/crisv10f.c
@@ -1,5 +1,5 @@
 /* CRIS v10 simulator support code
-   Copyright (C) 2004, 2005 Free Software Foundation, Inc.
+   Copyright (C) 2004, 2005, 2006 Free Software Foundation, Inc.
    Contributed by Axis Communications.
 
 This file is part of the GNU simulators.
@@ -40,3 +40,62 @@ MY (XCONCAT3 (f_model_crisv,BASENUM,
 }
 
 #endif /* WITH_PROFILE_MODEL_P */
+
+/* Do the interrupt sequence if possible, and return 1.  If interrupts
+   are disabled or some other lockout is active, return 0 and do
+   nothing.
+
+   Beware, the v10 implementation is incomplete and doesn't properly
+   lock out interrupts e.g. after special-register access and doesn't
+   handle user-mode.  */
+
+int
+MY (deliver_interrupt) (SIM_CPU *current_cpu,
+			enum cris_interrupt_type type,
+			unsigned int vec)
+{
+  unsigned char entryaddr_le[4];
+  int was_user;
+  SIM_DESC sd = CPU_STATE (current_cpu);
+  unsigned32 entryaddr;
+
+  /* We haven't implemented other interrupt-types yet.  */
+  if (type != CRIS_INT_INT)
+    abort ();
+
+  /* We're supposed to be called outside of prefixes and branch
+     delay-slots etc, but why not check.  */
+  if (GET_H_INSN_PREFIXED_P ())
+    abort ();
+
+  if (!GET_H_IBIT ())
+    return 0;
+
+  /* User mode isn't supported for interrupts.  (And we shouldn't see
+     this as 1 anyway.  The user-mode bit isn't visible from user
+     mode.  It doesn't make it into the U bit until the next
+     interrupt/exception.)  */
+  if (GET_H_UBIT ())
+    abort ();
+
+  SET_H_PBIT (1);
+
+  if (sim_core_read_buffer (sd,
+			    current_cpu,
+			    read_map, entryaddr_le,
+			    GET_H_SR (H_SR_PRE_V32_IBR) + vec * 4, 4) == 0)
+    {
+      /* Nothing to do actually; either abort or send a signal.  */
+      sim_core_signal (sd, current_cpu, CIA_GET (current_cpu), 0, 4,
+		       GET_H_SR (H_SR_PRE_V32_IBR) + vec * 4,
+		       read_transfer, sim_core_unmapped_signal);
+      return 0;
+    }
+
+  entryaddr = bfd_getl32 (entryaddr_le);
+
+  SET_H_SR (H_SR_PRE_V32_IRP, GET_H_PC ());
+  SET_H_PC (entryaddr);
+
+  return 1;
+}