diff options
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 13 | ||||
| -rw-r--r-- | opcodes/aarch64-opc.c | 20 | ||||
| -rw-r--r-- | opcodes/aarch64-tbl.h | 8 |
3 files changed, 33 insertions, 8 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 3b35149..26d1e7a 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,7 +1,16 @@ 2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com> - * aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP, - PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM. + * aarch64-opc.c (aarch64_print_operand): Change to print + AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal + in comment. + * aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag + from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and + OP_MOV_IMM_WIDE. + +2013-01-04 Yufeng Zhang <yufeng.zhang@arm.com> + + * aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP, + PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM. 2013-01-02 H.J. Lu <hongjiu.lu@intel.com> diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index fdb4ceb..72ecf5b 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -1,5 +1,5 @@ /* aarch64-opc.c -- AArch64 opcode support. - Copyright 2009, 2010, 2011, 2012 Free Software Foundation, Inc. + Copyright 2009, 2010, 2011, 2012, 2013 Free Software Foundation, Inc. Contributed by ARM Ltd. This file is part of the GNU opcodes library. @@ -2433,10 +2433,26 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc, case AARCH64_OPND_IMMR: case AARCH64_OPND_IMMS: case AARCH64_OPND_FBITS: - case AARCH64_OPND_IMM_MOV: snprintf (buf, size, "#%" PRIi64, opnd->imm.value); break; + case AARCH64_OPND_IMM_MOV: + switch (aarch64_get_qualifier_esize (opnds[0].qualifier)) + { + case 4: /* e.g. MOV Wd, #<imm32>. */ + { + int imm32 = opnd->imm.value; + snprintf (buf, size, "#0x%-20x\t// #%d", imm32, imm32); + } + break; + case 8: /* e.g. MOV Xd, #<imm64>. */ + snprintf (buf, size, "#0x%-20" PRIx64 "\t// #%" PRIi64, + opnd->imm.value, opnd->imm.value); + break; + default: assert (0); + } + break; + case AARCH64_OPND_FPIMM0: snprintf (buf, size, "#0.0"); break; diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index d360b14..fd38a9d 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -1,6 +1,6 @@ /* aarch64-tbl.h -- AArch64 opcode description table and instruction operand description table. - Copyright 2012 Free Software Foundation, Inc. + Copyright 2012, 2013 Free Software Foundation, Inc. This file is part of the GNU opcodes library. @@ -2017,7 +2017,7 @@ struct aarch64_opcode aarch64_opcode_table[] = {"and", 0x12000000, 0x7f800000, log_imm, 0, CORE, OP3 (Rd_SP, Rn, LIMM), QL_R2NIL, F_HAS_ALIAS | F_SF}, {"bic", 0x12000000, 0x7f800000, log_imm, OP_BIC, CORE, OP3 (Rd_SP, Rn, LIMM), QL_R2NIL, F_ALIAS | F_PSEUDO | F_SF}, {"orr", 0x32000000, 0x7f800000, log_imm, 0, CORE, OP3 (Rd_SP, Rn, LIMM), QL_R2NIL, F_HAS_ALIAS | F_SF}, - {"mov", 0x320003e0, 0x7f8003e0, log_imm, OP_MOV_IMM_LOG, CORE, OP2 (Rd_SP, IMM_MOV), QL_R1NIL, F_ALIAS | F_PSEUDO | F_P1 | F_SF | F_CONV}, + {"mov", 0x320003e0, 0x7f8003e0, log_imm, OP_MOV_IMM_LOG, CORE, OP2 (Rd_SP, IMM_MOV), QL_R1NIL, F_ALIAS | F_P1 | F_SF | F_CONV}, {"eor", 0x52000000, 0x7f800000, log_imm, 0, CORE, OP3 (Rd_SP, Rn, LIMM), QL_R2NIL, F_SF}, {"ands", 0x72000000, 0x7f800000, log_imm, 0, CORE, OP3 (Rd, Rn, LIMM), QL_R2NIL, F_HAS_ALIAS | F_SF}, {"tst", 0x7200001f, 0x7f80001f, log_imm, 0, CORE, OP2 (Rn, LIMM), QL_R1NIL, F_ALIAS | F_SF}, @@ -2036,9 +2036,9 @@ struct aarch64_opcode aarch64_opcode_table[] = {"bics", 0x6a200000, 0x7f200000, log_shift, 0, CORE, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_SF}, /* Move wide (immediate). */ {"movn", 0x12800000, 0x7f800000, movewide, OP_MOVN, CORE, OP2 (Rd, HALF), QL_DST_R, F_SF | F_HAS_ALIAS}, - {"mov", 0x12800000, 0x7f800000, movewide, OP_MOV_IMM_WIDEN, CORE, OP2 (Rd, IMM_MOV), QL_DST_R, F_SF | F_ALIAS | F_PSEUDO | F_CONV}, + {"mov", 0x12800000, 0x7f800000, movewide, OP_MOV_IMM_WIDEN, CORE, OP2 (Rd, IMM_MOV), QL_DST_R, F_SF | F_ALIAS | F_CONV}, {"movz", 0x52800000, 0x7f800000, movewide, OP_MOVZ, CORE, OP2 (Rd, HALF), QL_DST_R, F_SF | F_HAS_ALIAS}, - {"mov", 0x52800000, 0x7f800000, movewide, OP_MOV_IMM_WIDE, CORE, OP2 (Rd, IMM_MOV), QL_DST_R, F_SF | F_ALIAS | F_PSEUDO | F_CONV}, + {"mov", 0x52800000, 0x7f800000, movewide, OP_MOV_IMM_WIDE, CORE, OP2 (Rd, IMM_MOV), QL_DST_R, F_SF | F_ALIAS | F_CONV}, {"movk", 0x72800000, 0x7f800000, movewide, OP_MOVK, CORE, OP2 (Rd, HALF), QL_DST_R, F_SF}, /* PC-rel. addressing. */ {"adr", 0x10000000, 0x9f000000, pcreladdr, 0, CORE, OP2 (Rd, ADDR_PCREL21), QL_ADRP, 0}, |