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-rw-r--r--opcodes/ChangeLog5
-rw-r--r--opcodes/riscv-opc.c2
2 files changed, 6 insertions, 1 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 5588e4b..880f863 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,8 @@
+2018-12-07 Jim Wilson <jimw@sifive.com>
+
+ PR gas/23956
+ * riscv-opc.c (riscv_opcodes) <"add">: Use 1 not 0 for fourth arg.
+
2018-12-06 Andrew Burgess <andrew.burgess@embecosm.com>
* configure.ac (enable-cgen-maint): Support passing path to cgen
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index 3da2a77..29c6944 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -276,7 +276,7 @@ const struct riscv_opcode riscv_opcodes[] =
{"add", 0, {"I", 0}, "d,s,t", MATCH_ADD, MASK_ADD, match_opcode, 0 },
/* This is used for TLS, where the fourth arg is %tprel_add, to get a reloc
applied to an add instruction, for relaxation to use. */
-{"add", 0, {"I", 0}, "d,s,t,0",MATCH_ADD, MASK_ADD, match_opcode, 0 },
+{"add", 0, {"I", 0}, "d,s,t,1",MATCH_ADD, MASK_ADD, match_opcode, 0 },
{"add", 0, {"I", 0}, "d,s,j", MATCH_ADDI, MASK_ADDI, match_opcode, INSN_ALIAS },
{"la", 0, {"I", 0}, "d,B", 0, (int) M_LA, match_never, INSN_MACRO },
{"lla", 0, {"I", 0}, "d,B", 0, (int) M_LLA, match_never, INSN_MACRO },