diff options
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 14 | ||||
| -rw-r--r-- | opcodes/mips-dis.c | 5 | ||||
| -rw-r--r-- | opcodes/mips-opc.c | 13 |
3 files changed, 29 insertions, 3 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 6175d24..6b7edd6 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,17 @@ +2014-10-31 Andrew Pinski <apinski@cavium.com> + Naveen H.S <Naveen.Hurugalawadi@caviumnetworks.com> + + * mips-dis.c (mips_arch_choices): Add octeon3. + * mips-opc.c (IOCT): Include INSN_OCTEON3. + (IOCT2): Likewise. + (IOCT3): New define. + (IVIRT): New define. + (mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0, + tlbinv, tlbinvf, tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp, tlti + IVIRT instructions. + Extend mtm0, mtm1, mtm2, mtp0, mtp1, mtp2 instructions to take another + operand for IOCT3. + 2014-10-29 Nick Clifton <nickc@redhat.com> * po/de.po: Updated German translation. diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c index 1eb1d45..e710d04 100644 --- a/opcodes/mips-dis.c +++ b/opcodes/mips-dis.c @@ -649,6 +649,11 @@ const struct mips_arch_choice mips_arch_choices[] = ISA_MIPS64R2 | INSN_OCTEON2, 0, mips_cp0_names_numeric, NULL, 0, mips_cp1_names_mips3264, mips_hwr_names_numeric }, + { "octeon3", 1, bfd_mach_mips_octeon3, CPU_OCTEON3, + ISA_MIPS64R5 | INSN_OCTEON3, ASE_VIRT | ASE_VIRT64, + mips_cp0_names_numeric, + NULL, 0, mips_cp1_names_mips3264, mips_hwr_names_numeric }, + { "xlr", 1, bfd_mach_mips_xlr, CPU_XLR, ISA_MIPS64 | INSN_XLR, 0, mips_cp0_names_xlr, diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c index 0e9f716..6e0299e 100644 --- a/opcodes/mips-opc.c +++ b/opcodes/mips-opc.c @@ -316,9 +316,10 @@ decode_mips_operand (const char *p) #define N5 (INSN_5400 | INSN_5500) #define N54 INSN_5400 #define N55 INSN_5500 -#define IOCT (INSN_OCTEON | INSN_OCTEONP | INSN_OCTEON2) -#define IOCTP (INSN_OCTEONP | INSN_OCTEON2) -#define IOCT2 INSN_OCTEON2 +#define IOCT (INSN_OCTEON | INSN_OCTEONP | INSN_OCTEON2 | INSN_OCTEON3) +#define IOCTP (INSN_OCTEONP | INSN_OCTEON2 | INSN_OCTEON3) +#define IOCT2 (INSN_OCTEON2 | INSN_OCTEON3) +#define IOCT3 INSN_OCTEON3 #define XLR INSN_XLR #define IVIRT ASE_VIRT #define IVIRT64 ASE_VIRT64 @@ -1496,11 +1497,17 @@ const struct mips_opcode mips_builtin_opcodes[] = {"mtlhx", "s", 0x00000053, 0xfc1fffff, RD_1|MOD_HILO, 0, 0, SMT, 0 }, {"mtcr", "t,s", 0x70000019, 0xfc00ffff, RD_1|RD_2, 0, XLR, 0, 0 }, {"mtm0", "s", 0x70000008, 0xfc1fffff, RD_1, 0, IOCT, 0, 0 }, +{"mtm0", "s,t", 0x70000008, 0xfc00ffff, RD_1|RD_2, 0, IOCT3, 0, 0 }, {"mtm1", "s", 0x7000000c, 0xfc1fffff, RD_1, 0, IOCT, 0, 0 }, +{"mtm1", "s,t", 0x7000000c, 0xfc00ffff, RD_1|RD_2, 0, IOCT3, 0, 0 }, {"mtm2", "s", 0x7000000d, 0xfc1fffff, RD_1, 0, IOCT, 0, 0 }, +{"mtm2", "s,t", 0x7000000d, 0xfc00ffff, RD_1|RD_2, 0, IOCT3, 0, 0 }, {"mtp0", "s", 0x70000009, 0xfc1fffff, RD_1, 0, IOCT, 0, 0 }, +{"mtp0", "s,t", 0x70000009, 0xfc00ffff, RD_1|RD_2, 0, IOCT3, 0, 0 }, {"mtp1", "s", 0x7000000a, 0xfc1fffff, RD_1, 0, IOCT, 0, 0 }, +{"mtp1", "s,t", 0x7000000a, 0xfc00ffff, RD_1|RD_2, 0, IOCT3, 0, 0 }, {"mtp2", "s", 0x7000000b, 0xfc1fffff, RD_1, 0, IOCT, 0, 0 }, +{"mtp2", "s,t", 0x7000000b, 0xfc00ffff, RD_1|RD_2, 0, IOCT3, 0, 0 }, {"mtsa", "s", 0x00000029, 0xfc1fffff, RD_1, 0, EE, 0, 0 }, {"mtsab", "s,j", 0x04180000, 0xfc1f0000, RD_1, 0, EE, 0, 0 }, {"mtsah", "s,j", 0x04190000, 0xfc1f0000, RD_1, 0, EE, 0, 0 }, |