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-rw-r--r--opcodes/ChangeLog6
-rw-r--r--opcodes/mips-dis.c6
-rw-r--r--opcodes/mips-opc.c7
3 files changed, 13 insertions, 6 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 0b8925b..5cba4ec 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,9 @@
+2002-07-09 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de>
+
+ * mips-dis.c (mips_isa_type): Add MIPS16 insn handling.
+ * mips-opc.c (I16): New define.
+ (mips_builtin_opcodes): Make jalx an I16 insn.
+
2002-06-18 Dave Brolley <brolley@redhat.com>
* po/POTFILES.in: Add frv-*.[ch].
diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c
index b832ca2..9b35a47 100644
--- a/opcodes/mips-dis.c
+++ b/opcodes/mips-dis.c
@@ -412,7 +412,7 @@ mips_isa_type (mach, isa, cputype)
break;
case bfd_mach_mips16:
*cputype = CPU_MIPS16;
- *isa = ISA_MIPS3;
+ *isa = ISA_MIPS3 | INSN_MIPS16;
break;
case bfd_mach_mips5:
*cputype = CPU_MIPS5;
@@ -429,12 +429,12 @@ mips_isa_type (mach, isa, cputype)
_MIPS32 Architecture For Programmers Volume I: Introduction to the
MIPS32 Architecture_ (MIPS Document Number MD00082, Revision 0.95),
page 1. */
- *isa = ISA_MIPS32;
+ *isa = ISA_MIPS32 | INSN_MIPS16;
break;
case bfd_mach_mipsisa64:
*cputype = CPU_MIPS64;
/* For stock MIPS64, disassemble all applicable MIPS-specified ASEs. */
- *isa = ISA_MIPS64 | INSN_MDMX | INSN_MIPS3D;
+ *isa = ISA_MIPS64 | INSN_MIPS16 | INSN_MIPS3D | INSN_MDMX;
break;
default:
diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
index cbf9223..7edda05 100644
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -87,6 +87,9 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
#define I64 INSN_ISA64
/* MIPS64 MIPS-3D ASE support. */
+#define I16 INSN_MIPS16
+
+/* MIPS64 MIPS-3D ASE support. */
#define M3D INSN_MIPS3D
/* MIPS64 MDMX ASE support. */
@@ -568,9 +571,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
assembler, but will never match user input (because the line above
will match first). */
{"jal", "a", 0x0c000000, 0xfc000000, UBD|WR_31, I1 },
- /* jalx really should only be avaliable if mips16 is available,
- but for now make it I1. */
-{"jalx", "a", 0x74000000, 0xfc000000, UBD|WR_31, I1 },
+{"jalx", "a", 0x74000000, 0xfc000000, UBD|WR_31, I16 },
{"la", "t,o(b)", 0x24000000, 0xfc000000, WR_t|RD_s, I1 }, /* addiu */
{"la", "t,A(b)", 0, (int) M_LA_AB, INSN_MACRO, I1 },
{"lb", "t,o(b)", 0x80000000, 0xfc000000, LDD|RD_b|WR_t, I1 },