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-rw-r--r--opcodes/m32r-desc.c48
1 files changed, 24 insertions, 24 deletions
diff --git a/opcodes/m32r-desc.c b/opcodes/m32r-desc.c
index 98fecb2..30a0719 100644
--- a/opcodes/m32r-desc.c
+++ b/opcodes/m32r-desc.c
@@ -2,7 +2,7 @@
THIS FILE IS MACHINE GENERATED WITH CGEN.
-Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
+Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
This file is part of the GNU Binutils and/or GDB, the GNU debugger.
@@ -320,67 +320,67 @@ const CGEN_OPERAND m32r_cgen_operand_table[] =
{
/* pc: program counter */
{ "pc", M32R_OPERAND_PC, HW_H_PC, 0, 0,
- { 0, { (const PTR) &m32r_cgen_ifld_table[0] } },
+ { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_NIL] } },
{ 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
/* sr: source register */
{ "sr", M32R_OPERAND_SR, HW_H_GR, 12, 4,
- { 0, { (const PTR) &m32r_cgen_ifld_table[6] } },
+ { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_R2] } },
{ 0, { (1<<MACH_BASE) } } },
/* dr: destination register */
{ "dr", M32R_OPERAND_DR, HW_H_GR, 4, 4,
- { 0, { (const PTR) &m32r_cgen_ifld_table[5] } },
+ { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_R1] } },
{ 0, { (1<<MACH_BASE) } } },
/* src1: source register 1 */
{ "src1", M32R_OPERAND_SRC1, HW_H_GR, 4, 4,
- { 0, { (const PTR) &m32r_cgen_ifld_table[5] } },
+ { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_R1] } },
{ 0, { (1<<MACH_BASE) } } },
/* src2: source register 2 */
{ "src2", M32R_OPERAND_SRC2, HW_H_GR, 12, 4,
- { 0, { (const PTR) &m32r_cgen_ifld_table[6] } },
+ { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_R2] } },
{ 0, { (1<<MACH_BASE) } } },
/* scr: source control register */
{ "scr", M32R_OPERAND_SCR, HW_H_CR, 12, 4,
- { 0, { (const PTR) &m32r_cgen_ifld_table[6] } },
+ { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_R2] } },
{ 0, { (1<<MACH_BASE) } } },
/* dcr: destination control register */
{ "dcr", M32R_OPERAND_DCR, HW_H_CR, 4, 4,
- { 0, { (const PTR) &m32r_cgen_ifld_table[5] } },
+ { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_R1] } },
{ 0, { (1<<MACH_BASE) } } },
/* simm8: 8 bit signed immediate */
{ "simm8", M32R_OPERAND_SIMM8, HW_H_SINT, 8, 8,
- { 0, { (const PTR) &m32r_cgen_ifld_table[7] } },
+ { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_SIMM8] } },
{ 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
/* simm16: 16 bit signed immediate */
{ "simm16", M32R_OPERAND_SIMM16, HW_H_SINT, 16, 16,
- { 0, { (const PTR) &m32r_cgen_ifld_table[8] } },
+ { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_SIMM16] } },
{ 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
/* uimm4: 4 bit trap number */
{ "uimm4", M32R_OPERAND_UIMM4, HW_H_UINT, 12, 4,
- { 0, { (const PTR) &m32r_cgen_ifld_table[10] } },
+ { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM4] } },
{ 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
/* uimm5: 5 bit shift count */
{ "uimm5", M32R_OPERAND_UIMM5, HW_H_UINT, 11, 5,
- { 0, { (const PTR) &m32r_cgen_ifld_table[11] } },
+ { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM5] } },
{ 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
/* uimm16: 16 bit unsigned immediate */
{ "uimm16", M32R_OPERAND_UIMM16, HW_H_UINT, 16, 16,
- { 0, { (const PTR) &m32r_cgen_ifld_table[12] } },
+ { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM16] } },
{ 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
/* imm1: 1 bit immediate */
{ "imm1", M32R_OPERAND_IMM1, HW_H_UINT, 15, 1,
- { 0, { (const PTR) &m32r_cgen_ifld_table[25] } },
+ { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_IMM1] } },
{ 0|A(HASH_PREFIX), { (1<<MACH_M32RX) } } },
/* accd: accumulator destination register */
{ "accd", M32R_OPERAND_ACCD, HW_H_ACCUMS, 4, 2,
- { 0, { (const PTR) &m32r_cgen_ifld_table[22] } },
+ { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_ACCD] } },
{ 0, { (1<<MACH_M32RX) } } },
/* accs: accumulator source register */
{ "accs", M32R_OPERAND_ACCS, HW_H_ACCUMS, 12, 2,
- { 0, { (const PTR) &m32r_cgen_ifld_table[21] } },
+ { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_ACCS] } },
{ 0, { (1<<MACH_M32RX) } } },
/* acc: accumulator reg (d) */
{ "acc", M32R_OPERAND_ACC, HW_H_ACCUMS, 8, 1,
- { 0, { (const PTR) &m32r_cgen_ifld_table[20] } },
+ { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_ACC] } },
{ 0, { (1<<MACH_M32RX) } } },
/* hash: # prefix */
{ "hash", M32R_OPERAND_HASH, HW_H_SINT, 0, 0,
@@ -388,31 +388,31 @@ const CGEN_OPERAND m32r_cgen_operand_table[] =
{ 0, { (1<<MACH_BASE) } } },
/* hi16: high 16 bit immediate, sign optional */
{ "hi16", M32R_OPERAND_HI16, HW_H_HI16, 16, 16,
- { 0, { (const PTR) &m32r_cgen_ifld_table[14] } },
+ { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_HI16] } },
{ 0|A(SIGN_OPT), { (1<<MACH_BASE) } } },
/* slo16: 16 bit signed immediate, for low() */
{ "slo16", M32R_OPERAND_SLO16, HW_H_SLO16, 16, 16,
- { 0, { (const PTR) &m32r_cgen_ifld_table[8] } },
+ { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_SIMM16] } },
{ 0, { (1<<MACH_BASE) } } },
/* ulo16: 16 bit unsigned immediate, for low() */
{ "ulo16", M32R_OPERAND_ULO16, HW_H_ULO16, 16, 16,
- { 0, { (const PTR) &m32r_cgen_ifld_table[12] } },
+ { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM16] } },
{ 0, { (1<<MACH_BASE) } } },
/* uimm24: 24 bit address */
{ "uimm24", M32R_OPERAND_UIMM24, HW_H_ADDR, 8, 24,
- { 0, { (const PTR) &m32r_cgen_ifld_table[13] } },
+ { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_UIMM24] } },
{ 0|A(HASH_PREFIX)|A(RELOC)|A(ABS_ADDR), { (1<<MACH_BASE) } } },
/* disp8: 8 bit displacement */
{ "disp8", M32R_OPERAND_DISP8, HW_H_IADDR, 8, 8,
- { 0, { (const PTR) &m32r_cgen_ifld_table[15] } },
+ { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_DISP8] } },
{ 0|A(RELAX)|A(RELOC)|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
/* disp16: 16 bit displacement */
{ "disp16", M32R_OPERAND_DISP16, HW_H_IADDR, 16, 16,
- { 0, { (const PTR) &m32r_cgen_ifld_table[16] } },
+ { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_DISP16] } },
{ 0|A(RELOC)|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
/* disp24: 24 bit displacement */
{ "disp24", M32R_OPERAND_DISP24, HW_H_IADDR, 8, 24,
- { 0, { (const PTR) &m32r_cgen_ifld_table[17] } },
+ { 0, { (const PTR) &m32r_cgen_ifld_table[M32R_F_DISP24] } },
{ 0|A(RELAX)|A(RELOC)|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
/* condbit: condition bit */
{ "condbit", M32R_OPERAND_CONDBIT, HW_H_COND, 0, 0,