diff options
Diffstat (limited to 'include')
| -rw-r--r-- | include/ChangeLog | 6 | ||||
| -rw-r--r-- | include/opcode/mips.h | 11 |
2 files changed, 15 insertions, 2 deletions
diff --git a/include/ChangeLog b/include/ChangeLog index b97775e..d0cc5c4 100644 --- a/include/ChangeLog +++ b/include/ChangeLog @@ -1,5 +1,11 @@ 2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk> + * opcode/mips.h: Document `g' and `y' operand codes. + (mips_reg_operand_type): Add OP_REG_CONTROL enumeration + constant. + +2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk> + * opcode/mips.h: Complement change made to opcodes and remove references to the `g' regular MIPS ISA operand code. diff --git a/include/opcode/mips.h b/include/opcode/mips.h index 9fa9fcb..e0a6447 100644 --- a/include/opcode/mips.h +++ b/include/opcode/mips.h @@ -461,6 +461,10 @@ enum mips_reg_operand_type { also be used in some contexts. */ OP_REG_COPRO, + /* Coprocessor control registers $0-$31. Mnemonic names like c1_fcsr can + also be used in some contexts. */ + OP_REG_CONTROL, + /* Hardware registers $0-$31. Mnemonic names like hwr_cpunum can also be used in some contexts. */ OP_REG_HW, @@ -841,6 +845,7 @@ mips_opcode_32bit_p (const struct mips_opcode *mo) "H" 3 bit sel field for (d)mtc* and (d)mfc* (OP_*_SEL) "P" 5 bit performance-monitor register (OP_*_PERFREG) "e" 5 bit vector register byte specifier (OP_*_VECBYTE) + "g" 5 bit control destination register (OP_*_RD) "%" 3 bit immediate vr5400 vector alignment operand (OP_*_VECALIGN) Macro instructions: @@ -899,6 +904,7 @@ mips_opcode_32bit_p (const struct mips_opcode *mo) "$" 1 bit load high flag (OP_*_MT_H) "*" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_T) "&" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_D) + "y" 5 bit control target register (OP_*_RT) "+t" 5 bit coprocessor 0 destination register (OP_*_RT) MCU ASE usage: @@ -1000,7 +1006,7 @@ mips_opcode_32bit_p (const struct mips_opcode *mo) "1234567890" "%[]<>(),+-:'@!#$*&\~" "ABCDEFGHIJKLMNOPQRSTUVWXYZ" - "abcdef hijkl opqrstuvwx z" + "abcdef hijkl opqrstuvwxyz" Extension character sequences used so far ("+" followed by the following), for quick reference when adding more: @@ -2277,6 +2283,7 @@ extern const int bfd_mips16_num_opcodes; "E" 5-bit target register (MICROMIPSOP_*_RT) "G" 5-bit source register (MICROMIPSOP_*_RS) "H" 3-bit sel field for (D)MTC* and (D)MFC* (MICROMIPSOP_*_SEL) + "g" 5-bit control source register (MICROMIPSOP_*_RS) Macro instructions: "A" general 32 bit expression @@ -2338,7 +2345,7 @@ extern const int bfd_mips16_num_opcodes; "12345678 0" "<>(),+-.@\^|~" "ABCDEFGHI KLMN RST V " - "abcd f hijklmnopqrstuvw yz" + "abcd fghijklmnopqrstuvw yz" Extension character sequences used so far ("+" followed by the following), for quick reference when adding more: |