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-rw-r--r--include/ChangeLog6
-rw-r--r--include/coff/pe.h5
2 files changed, 10 insertions, 1 deletions
diff --git a/include/ChangeLog b/include/ChangeLog
index dc320cb..a6e3ebc 100644
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,3 +1,9 @@
+2017-11-13 Jan Beulich <jbeulich@suse.com>
+
+ * coff/pe.h (COFF_ENCODE_ALIGNMENT): Cap value to maximum one
+ representable.
+ (COFF_DECODE_ALIGNMENT): Define.
+
2017-11-09 Tamar Christina <tamar.christina@arm.com>
* opcode/aarch64.h (AARCH64_ARCH_V8_4): Enable DOTPROD.
diff --git a/include/coff/pe.h b/include/coff/pe.h
index f51ceed..5239916 100644
--- a/include/coff/pe.h
+++ b/include/coff/pe.h
@@ -104,7 +104,10 @@
/* Encode alignment power into IMAGE_SCN_ALIGN bits of s_flags. */
#define COFF_ENCODE_ALIGNMENT(SECTION, ALIGNMENT_POWER) \
- ((SECTION).s_flags |= IMAGE_SCN_ALIGN_POWER_CONST ((ALIGNMENT_POWER)))
+ ((SECTION).s_flags |= IMAGE_SCN_ALIGN_POWER_CONST ((ALIGNMENT_POWER) <= 13 \
+ ? (ALIGNMENT_POWER) : 13))
+#define COFF_DECODE_ALIGNMENT(X) \
+ IMAGE_SCN_ALIGN_POWER_NUM ((X) & IMAGE_SCN_ALIGN_POWER_BIT_MASK)
#define IMAGE_SCN_LNK_NRELOC_OVFL 0x01000000 /* Section contains extended relocations. */
#define IMAGE_SCN_MEM_NOT_CACHED 0x04000000 /* Section is not cachable. */