aboutsummaryrefslogtreecommitdiff
path: root/include
diff options
context:
space:
mode:
Diffstat (limited to 'include')
-rw-r--r--include/elf/ChangeLog30
-rw-r--r--include/elf/ppc.h27
-rw-r--r--include/opcode/ChangeLog15
-rw-r--r--include/opcode/ppc.h43
4 files changed, 106 insertions, 9 deletions
diff --git a/include/elf/ChangeLog b/include/elf/ChangeLog
index a405d8b..81ae20d 100644
--- a/include/elf/ChangeLog
+++ b/include/elf/ChangeLog
@@ -1,3 +1,33 @@
+2012-05-14 James Lemke <jwlemke@codesourcery.com>
+ * ppc.h (SEC_PPC_VLE): Remove.
+
+2012-05-14 Catherine Moore <clm@codesourcery.com>
+ James Lemke <jwlemke@codesourcery.com>
+
+ * ppc.h (R_PPC_VLE_REL8): New reloction.
+ (R_PPC_VLE_REL15): Likewise.
+ (R_PPC_VLE_REL24): Likewise.
+ (R_PPC_VLE_LO16A): Likewise.
+ (R_PPC_VLE_LO16D): Likewise.
+ (R_PPC_VLE_HI16A): Likewise.
+ (R_PPC_VLE_HI16D): Likewise.
+ (R_PPC_VLE_HA16A): Likewise.
+ (R_PPC_VLE_HA16D): Likewise.
+ (R_PPC_VLE_SDA21): Likewise.
+ (R_PPC_VLE_SDA21_LO): Likewise.
+ (R_PPC_VLE_SDAREL_LO16A): Likewise.
+ (R_PPC_VLE_SDAREL_LO16D): Likewise.
+ (R_PPC_VLE_SDAREL_HI16A): Likewise.
+ (R_PPC_VLE_SDAREL_HI16D): Likewise.
+ (R_PPC_VLE_SDAREL_HA16A): Likewise.
+ (R_PPC_VLE_SDAREL_HA16D): Likewise.
+ (SEC_PPC_VLE): Remove.
+ (PF_PPC_VLE): New program header flag.
+ (SHF_PPC_VLE): New section header flag.
+ (vle_opcodes, vle_num_opcodes): New.
+ (VLE_OP): New macro.
+ (VLE_OP_TO_SEG): New macro.
+
2012-05-11 Georg-Johann Lay <avr@gjlay.de
PR target/13503
diff --git a/include/elf/ppc.h b/include/elf/ppc.h
index 8e27855..f80a1e8 100644
--- a/include/elf/ppc.h
+++ b/include/elf/ppc.h
@@ -131,6 +131,25 @@ START_RELOC_NUMBERS (elf_ppc_reloc_type)
RELOC_NUMBER (R_PPC_EMB_BIT_FLD, 115)
RELOC_NUMBER (R_PPC_EMB_RELSDA, 116)
+/* PowerPC VLE relocations. */
+ RELOC_NUMBER (R_PPC_VLE_REL8, 216)
+ RELOC_NUMBER (R_PPC_VLE_REL15, 217)
+ RELOC_NUMBER (R_PPC_VLE_REL24, 218)
+ RELOC_NUMBER (R_PPC_VLE_LO16A, 219)
+ RELOC_NUMBER (R_PPC_VLE_LO16D, 220)
+ RELOC_NUMBER (R_PPC_VLE_HI16A, 221)
+ RELOC_NUMBER (R_PPC_VLE_HI16D, 222)
+ RELOC_NUMBER (R_PPC_VLE_HA16A, 223)
+ RELOC_NUMBER (R_PPC_VLE_HA16D, 224)
+ RELOC_NUMBER (R_PPC_VLE_SDA21, 225)
+ RELOC_NUMBER (R_PPC_VLE_SDA21_LO, 226)
+ RELOC_NUMBER (R_PPC_VLE_SDAREL_LO16A, 227)
+ RELOC_NUMBER (R_PPC_VLE_SDAREL_LO16D, 228)
+ RELOC_NUMBER (R_PPC_VLE_SDAREL_HI16A, 229)
+ RELOC_NUMBER (R_PPC_VLE_SDAREL_HI16D, 230)
+ RELOC_NUMBER (R_PPC_VLE_SDAREL_HA16A, 231)
+ RELOC_NUMBER (R_PPC_VLE_SDAREL_HA16D, 232)
+
/* Support STT_GNU_IFUNC plt calls. */
RELOC_NUMBER (R_PPC_IRELATIVE, 248)
@@ -166,9 +185,11 @@ END_RELOC_NUMBERS (R_PPC_max)
#define EF_PPC_RELOCATABLE 0x00010000 /* PowerPC -mrelocatable flag. */
#define EF_PPC_RELOCATABLE_LIB 0x00008000 /* PowerPC -mrelocatable-lib flag. */
-/* This bit is reserved by BFD for processor specific stuff. Name
- it properly so that we can easily stay consistent elsewhere. */
-#define SEC_PPC_VLE SEC_TIC54X_BLOCK
+/* Processor specific program headers, p_flags field. */
+#define PF_PPC_VLE 0x10000000 /* PowerPC VLE. */
+
+/* Processor specific section headers, sh_flags field. */
+#define SHF_PPC_VLE 0x10000000 /* PowerPC VLE text section. */
/* Processor specific section headers, sh_type field. */
diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog
index af70340..7160f10 100644
--- a/include/opcode/ChangeLog
+++ b/include/opcode/ChangeLog
@@ -1,3 +1,18 @@
+2012-05-14 Catherine Moore <clm@codesourcery.com>
+ Maciej W. Rozycki <macro@codesourcery.com>
+ Rhonda Wittels <rhonda@codesourcery.com>
+
+ * ppc.h (PPC_OPCODE_VLE): New definition.
+ (PPC_OP_SA): New macro.
+ (PPC_OP_SE_VLE): New macro.
+ (PPC_OP): Use a variable shift amount.
+ (powerpc_operand): Update comments.
+ (PPC_OPSHIFT_INV): New macro.
+ (PPC_OPERAND_CR): Replace with...
+ (PPC_OPERAND_CR_BIT): ...this and
+ (PPC_OPERAND_CR_REG): ...this.
+
+
2012-05-03 Sean Keys <skeys@ipdatasys.com>
* xgate.h: Header file for XGATE assembler.
diff --git a/include/opcode/ppc.h b/include/opcode/ppc.h
index e672502..2e789d6 100644
--- a/include/opcode/ppc.h
+++ b/include/opcode/ppc.h
@@ -65,6 +65,8 @@ struct powerpc_opcode
instructions. */
extern const struct powerpc_opcode powerpc_opcodes[];
extern const int powerpc_num_opcodes;
+extern const struct powerpc_opcode vle_opcodes[];
+extern const int vle_num_opcodes;
/* Values defined for the flags field of a struct powerpc_opcode. */
@@ -183,8 +185,20 @@ extern const int powerpc_num_opcodes;
/* Opcode is supported by Thread management APU */
#define PPC_OPCODE_TMR 0x800000000ull
+/* Opcode which is supported by the VLE extension. */
+#define PPC_OPCODE_VLE 0x1000000000ull
+
/* A macro to extract the major opcode from an instruction. */
#define PPC_OP(i) (((i) >> 26) & 0x3f)
+
+/* A macro to determine if the instruction is a 2-byte VLE insn. */
+#define PPC_OP_SE_VLE(m) ((m) <= 0xffff)
+
+/* A macro to extract the major opcode from a VLE instruction. */
+#define VLE_OP(i,m) (((i) >> ((m) <= 0xffff ? 10 : 26)) & 0x3f)
+
+/* A macro to convert a VLE opcode to a VLE opcode segment. */
+#define VLE_OP_TO_SEG(i) ((i) >> 1)
/* The operands table is an array of struct powerpc_operand. */
@@ -193,16 +207,22 @@ struct powerpc_operand
/* A bitmask of bits in the operand. */
unsigned int bitm;
- /* How far the operand is left shifted in the instruction.
- -1 to indicate that BITM and SHIFT cannot be used to determine
- where the operand goes in the insn. */
+ /* The shift operation to be applied to the operand. No shift
+ is made if this is zero. For positive values, the operand
+ is shifted left by SHIFT. For negative values, the operand
+ is shifted right by -SHIFT. Use PPC_OPSHIFT_INV to indicate
+ that BITM and SHIFT cannot be used to determine where the
+ operand goes in the insn. */
int shift;
/* Insertion function. This is used by the assembler. To insert an
operand value into an instruction, check this field.
If it is NULL, execute
- i |= (op & o->bitm) << o->shift;
+ if (o->shift >= 0)
+ i |= (op & o->bitm) << o->shift;
+ else
+ i |= (op & o->bitm) >> -o->shift;
(i is the instruction which we are filling in, o is a pointer to
this structure, and op is the operand value).
@@ -220,7 +240,10 @@ struct powerpc_operand
extract this operand type from an instruction, check this field.
If it is NULL, compute
- op = (i >> o->shift) & o->bitm;
+ if (o->shift >= 0)
+ op = (i >> o->shift) & o->bitm;
+ else
+ op = (i << -o->shift) & o->bitm;
if ((o->flags & PPC_OPERAND_SIGNED) != 0)
sign_extend (op);
(i is the instruction, o is a pointer to this structure, and op
@@ -244,6 +267,11 @@ struct powerpc_operand
extern const struct powerpc_operand powerpc_operands[];
extern const unsigned int num_powerpc_operands;
+/* Use with the shift field of a struct powerpc_operand to indicate
+ that BITM and SHIFT cannot be used to determine where the operand
+ goes in the insn. */
+#define PPC_OPSHIFT_INV (-1 << 31)
+
/* Values defined for the flags field of a struct powerpc_operand. */
/* This operand takes signed values. */
@@ -277,7 +305,7 @@ extern const unsigned int num_powerpc_operands;
cr4 4 cr5 5 cr6 6 cr7 7
These may be combined arithmetically, as in cr2*4+gt. These are
only supported on the PowerPC, not the POWER. */
-#define PPC_OPERAND_CR (0x10)
+#define PPC_OPERAND_CR_BIT (0x10)
/* This operand names a register. The disassembler uses this to print
register names with a leading 'r'. */
@@ -342,6 +370,9 @@ extern const unsigned int num_powerpc_operands;
/* This operand names a vector-scalar unit register. The disassembler
prints these with a leading 'vs'. */
#define PPC_OPERAND_VSR (0x100000)
+
+/* This is a CR FIELD that does not use symbolic names. */
+#define PPC_OPERAND_CR_REG (0x200000)
/* The POWER and PowerPC assemblers use a few macros. We keep them
with the operands table for simplicity. The macro table is an
generated by cgit v1.1 at 2024-07-28 16:56:33 +0000