diff options
Diffstat (limited to 'gdb/z80-tdep.c')
| -rw-r--r-- | gdb/z80-tdep.c | 620 |
1 files changed, 308 insertions, 312 deletions
diff --git a/gdb/z80-tdep.c b/gdb/z80-tdep.c index 9dc24df..806ef4f 100644 --- a/gdb/z80-tdep.c +++ b/gdb/z80-tdep.c @@ -98,11 +98,11 @@ struct z80_unwind_cache struct { - int called:1; /* there is return address on stack */ - int load_args:1; /* prologues loads args using POPs */ - int fp_sdcc:1; /* prologue saves and adjusts frame pointer IX */ - int interrupt:1; /* __interrupt handler */ - int critical:1; /* __critical function */ + int called : 1; /* there is return address on stack */ + int load_args : 1; /* prologues loads args using POPs */ + int fp_sdcc : 1; /* prologue saves and adjusts frame pointer IX */ + int interrupt : 1; /* __interrupt handler */ + int critical : 1; /* __critical function */ } prologue_type; /* Table indicating the location of each and every register. */ @@ -152,12 +152,9 @@ struct z80_insn_info static const struct z80_insn_info * z80_get_insn_info (struct gdbarch *gdbarch, const gdb_byte *buf, int *size); -static const char *z80_reg_names[] = -{ +static const char *z80_reg_names[] = { /* 24 bit on eZ80, else 16 bit */ - "af", "bc", "de", "hl", - "sp", "pc", "ix", "iy", - "af'", "bc'", "de'", "hl'", + "af", "bc", "de", "hl", "sp", "pc", "ix", "iy", "af'", "bc'", "de'", "hl'", "ir", /* eZ80 only */ "sps" @@ -310,30 +307,33 @@ z80_scan_prologue (struct gdbarch *gdbarch, CORE_ADDR pc_beg, CORE_ADDR pc_end, enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); z80_gdbarch_tdep *tdep = gdbarch_tdep<z80_gdbarch_tdep> (gdbarch); int addr_len = tdep->addr_length; - gdb_byte prologue[32]; /* max prologue is 24 bytes: __interrupt with local array */ + gdb_byte + prologue[32]; /* max prologue is 24 bytes: __interrupt with local array */ int pos = 0; int len; int reg; CORE_ADDR value; len = pc_end - pc_beg; - if (len > (int)sizeof (prologue)) + if (len > (int) sizeof (prologue)) len = sizeof (prologue); read_memory (pc_beg, prologue, len); /* stage0: check for series of POPs and then PUSHs */ - if ((reg = z80_is_pop_rr(prologue, &pos))) + if ((reg = z80_is_pop_rr (prologue, &pos))) { int i; int size = pos; gdb_byte regs[8]; /* Z80 have only 6 register pairs */ regs[0] = reg & 0xff; for (i = 1; i < 8 && (regs[i] = z80_is_pop_rr (&prologue[pos], &size)); - ++i, pos += size); + ++i, pos += size) + ; /* now we expect series of PUSHs in reverse order */ for (--i; i >= 0 && regs[i] == z80_is_push_rr (&prologue[pos], &size); - --i, pos += size); + --i, pos += size) + ; if (i == -1 && pos > 0) info->prologue_type.load_args = 1; else @@ -361,15 +361,17 @@ z80_scan_prologue (struct gdbarch *gdbarch, CORE_ADDR pc_beg, CORE_ADDR pc_end, if (msymbol.minsym) { value = msymbol.value_address (); - if (value == extract_unsigned_integer (&prologue[pos+1], addr_len, byte_order)) + if (value + == extract_unsigned_integer (&prologue[pos + 1], addr_len, + byte_order)) { pos += 1 + addr_len; info->prologue_type.fp_sdcc = 1; } } } - else if (!memcmp (&prologue[pos], "\335\345\335\041\000\000", 4+addr_len) && - !memcmp (&prologue[pos+4+addr_len], "\335\071\335\371", 4)) + else if (!memcmp (&prologue[pos], "\335\345\335\041\000\000", 4 + addr_len) + && !memcmp (&prologue[pos + 4 + addr_len], "\335\071\335\371", 4)) { /* push ix; ld ix, #0; add ix, sp; ld sp, ix */ pos += 4 + addr_len + 4; info->prologue_type.fp_sdcc = 1; @@ -383,63 +385,67 @@ z80_scan_prologue (struct gdbarch *gdbarch, CORE_ADDR pc_beg, CORE_ADDR pc_end, /* stage3: check for local variables allocation */ switch (prologue[pos]) { - case 0xf5: /* push af */ - info->size = 0; - while (prologue[pos] == 0xf5) - { - info->size += addr_len; - pos++; - } - if (prologue[pos] == 0x3b) /* dec sp */ - { - info->size++; - pos++; - } - break; - case 0x3b: /* dec sp */ - info->size = 0; - while (prologue[pos] == 0x3b) - { - info->size++; - pos++; - } - break; - case 0x21: /*ld hl, -nn */ - if (prologue[pos+addr_len] == 0x39 && prologue[pos+addr_len] >= 0x80 && - prologue[pos+addr_len+1] == 0xf9) - { /* add hl, sp; ld sp, hl */ - info->size = -extract_signed_integer(&prologue[pos+1], addr_len, byte_order); - pos += 1 + addr_len + 2; - } - break; - case 0xfd: /* ld iy, -nn */ - if (prologue[pos+1] == 0x21 && prologue[pos+1+addr_len] >= 0x80 && - !memcmp (&prologue[pos+2+addr_len], "\375\071\375\371", 4)) - { - info->size = -extract_signed_integer(&prologue[pos+2], addr_len, byte_order); - pos += 2 + addr_len + 4; - } - break; - case 0xed: /* check for lea xx, ix - n */ - switch (prologue[pos+1]) - { - case 0x22: /* lea hl, ix - n */ - if (prologue[pos+2] >= 0x80 && prologue[pos+3] == 0xf9) - { /* ld sp, hl */ - info->size = -extract_signed_integer(&prologue[pos+2], 1, byte_order); - pos += 4; - } - break; - case 0x55: /* lea iy, ix - n */ - if (prologue[pos+2] >= 0x80 && prologue[pos+3] == 0xfd && - prologue[pos+4] == 0xf9) - { /* ld sp, iy */ - info->size = -extract_signed_integer(&prologue[pos+2], 1, byte_order); - pos += 5; - } - break; - } + case 0xf5: /* push af */ + info->size = 0; + while (prologue[pos] == 0xf5) + { + info->size += addr_len; + pos++; + } + if (prologue[pos] == 0x3b) /* dec sp */ + { + info->size++; + pos++; + } + break; + case 0x3b: /* dec sp */ + info->size = 0; + while (prologue[pos] == 0x3b) + { + info->size++; + pos++; + } + break; + case 0x21: /*ld hl, -nn */ + if (prologue[pos + addr_len] == 0x39 && prologue[pos + addr_len] >= 0x80 + && prologue[pos + addr_len + 1] == 0xf9) + { /* add hl, sp; ld sp, hl */ + info->size = -extract_signed_integer (&prologue[pos + 1], addr_len, + byte_order); + pos += 1 + addr_len + 2; + } + break; + case 0xfd: /* ld iy, -nn */ + if (prologue[pos + 1] == 0x21 && prologue[pos + 1 + addr_len] >= 0x80 + && !memcmp (&prologue[pos + 2 + addr_len], "\375\071\375\371", 4)) + { + info->size = -extract_signed_integer (&prologue[pos + 2], addr_len, + byte_order); + pos += 2 + addr_len + 4; + } + break; + case 0xed: /* check for lea xx, ix - n */ + switch (prologue[pos + 1]) + { + case 0x22: /* lea hl, ix - n */ + if (prologue[pos + 2] >= 0x80 && prologue[pos + 3] == 0xf9) + { /* ld sp, hl */ + info->size + = -extract_signed_integer (&prologue[pos + 2], 1, byte_order); + pos += 4; + } break; + case 0x55: /* lea iy, ix - n */ + if (prologue[pos + 2] >= 0x80 && prologue[pos + 3] == 0xfd + && prologue[pos + 4] == 0xf9) + { /* ld sp, iy */ + info->size + = -extract_signed_integer (&prologue[pos + 2], 1, byte_order); + pos += 5; + } + break; + } + break; } len = 0; @@ -477,7 +483,7 @@ z80_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) return std::max (pc, prologue_end); { - struct z80_unwind_cache info = {0}; + struct z80_unwind_cache info = { 0 }; struct trad_frame_saved_reg saved_regs[Z80_NUM_REGS]; info.saved_regs = saved_regs; @@ -487,8 +493,8 @@ z80_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) prologue_end = z80_scan_prologue (gdbarch, func_addr, func_end, &info); - if (info.prologue_type.fp_sdcc || info.prologue_type.interrupt || - info.prologue_type.critical) + if (info.prologue_type.fp_sdcc || info.prologue_type.interrupt + || info.prologue_type.critical) return std::max (pc, prologue_end); } @@ -498,8 +504,8 @@ z80_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) struct compunit_symtab *compunit = prologue_sal.symtab->compunit (); const char *debug_format = compunit->debugformat (); - if (debug_format != NULL && - !strncasecmp ("dwarf", debug_format, strlen("dwarf"))) + if (debug_format != NULL + && !strncasecmp ("dwarf", debug_format, strlen ("dwarf"))) return std::max (pc, prologue_end); } @@ -534,7 +540,8 @@ z80_return_value (struct gdbarch *gdbarch, struct value *function, { if (len > 2) { - regcache->cooked_write_part (Z80_DE_REGNUM, 0, len - 2, writebuf+2); + regcache->cooked_write_part (Z80_DE_REGNUM, 0, len - 2, + writebuf + 2); len = 2; } regcache->cooked_write_part (Z80_HL_REGNUM, 0, len, writebuf); @@ -544,7 +551,7 @@ z80_return_value (struct gdbarch *gdbarch, struct value *function, { if (len > 2) { - regcache->cooked_read_part (Z80_DE_REGNUM, 0, len - 2, readbuf+2); + regcache->cooked_read_part (Z80_DE_REGNUM, 0, len - 2, readbuf + 2); len = 2; } regcache->cooked_read_part (Z80_HL_REGNUM, 0, len, readbuf); @@ -555,13 +562,12 @@ z80_return_value (struct gdbarch *gdbarch, struct value *function, /* function unwinds current stack frame and returns next one */ static struct z80_unwind_cache * -z80_frame_unwind_cache (frame_info_ptr this_frame, - void **this_prologue_cache) +z80_frame_unwind_cache (frame_info_ptr this_frame, void **this_prologue_cache) { CORE_ADDR start_pc, current_pc; ULONGEST this_base; int i; - gdb_byte buf[sizeof(void*)]; + gdb_byte buf[sizeof (void *)]; struct z80_unwind_cache *info; struct gdbarch *gdbarch = get_frame_arch (this_frame); z80_gdbarch_tdep *tdep = gdbarch_tdep<z80_gdbarch_tdep> (gdbarch); @@ -578,8 +584,8 @@ z80_frame_unwind_cache (frame_info_ptr this_frame, start_pc = get_frame_func (this_frame); current_pc = get_frame_pc (this_frame); if ((start_pc > 0) && (start_pc <= current_pc)) - z80_scan_prologue (get_frame_arch (this_frame), - start_pc, current_pc, info); + z80_scan_prologue (get_frame_arch (this_frame), start_pc, current_pc, + info); if (info->prologue_type.fp_sdcc) { @@ -592,7 +598,7 @@ z80_frame_unwind_cache (frame_info_ptr this_frame, { CORE_ADDR addr; CORE_ADDR sp; - CORE_ADDR sp_mask = (1 << gdbarch_ptr_bit(gdbarch)) - 1; + CORE_ADDR sp_mask = (1 << gdbarch_ptr_bit (gdbarch)) - 1; enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); /* Assume that the FP is this frame's SP but with that pushed stack space added back. */ @@ -608,18 +614,16 @@ z80_frame_unwind_cache (frame_info_ptr this_frame, } /* find return address */ read_memory (sp, buf, addr_len); - addr = extract_unsigned_integer(buf, addr_len, byte_order); - read_memory (addr-addr_len-1, buf, addr_len+1); + addr = extract_unsigned_integer (buf, addr_len, byte_order); + read_memory (addr - addr_len - 1, buf, addr_len + 1); if (buf[0] == 0xcd || (buf[0] & 0307) == 0304) /* Is it CALL */ { /* CALL nn or CALL cc,nn */ - static const char *names[] = - { - "__sdcc_call_ix", "__sdcc_call_iy", "__sdcc_call_hl" - }; - addr = extract_unsigned_integer(buf+1, addr_len, byte_order); + static const char *names[] + = { "__sdcc_call_ix", "__sdcc_call_iy", "__sdcc_call_hl" }; + addr = extract_unsigned_integer (buf + 1, addr_len, byte_order); if (addr == start_pc) break; /* found */ - for (i = sizeof(names)/sizeof(*names)-1; i >= 0; --i) + for (i = sizeof (names) / sizeof (*names) - 1; i >= 0; --i) { struct bound_minimal_symbol msymbol; msymbol = lookup_minimal_symbol (names[i], NULL, NULL); @@ -642,8 +646,8 @@ z80_frame_unwind_cache (frame_info_ptr this_frame, offsets. */ for (i = 0; i < gdbarch_num_regs (gdbarch) - 1; i++) if (info->saved_regs[i].addr () > 0) - info->saved_regs[i].set_addr - (info->prev_sp - info->saved_regs[i].addr () * addr_len); + info->saved_regs[i].set_addr (info->prev_sp + - info->saved_regs[i].addr () * addr_len); /* Except for the startup code, the return PC is always saved on the stack and is at the base of the frame. */ @@ -682,8 +686,8 @@ z80_frame_this_id (frame_info_ptr this_frame, void **this_cache, } static struct value * -z80_frame_prev_register (frame_info_ptr this_frame, - void **this_prologue_cache, int regnum) +z80_frame_prev_register (frame_info_ptr this_frame, void **this_prologue_cache, + int regnum) { struct z80_unwind_cache *info = z80_frame_unwind_cache (this_frame, this_prologue_cache); @@ -700,8 +704,8 @@ z80_frame_prev_register (frame_info_ptr this_frame, z80_gdbarch_tdep *tdep = gdbarch_tdep<z80_gdbarch_tdep> (gdbarch); enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); - read_memory (info->saved_regs[Z80_PC_REGNUM].addr (), - buf, tdep->addr_length); + read_memory (info->saved_regs[Z80_PC_REGNUM].addr (), buf, + tdep->addr_length); pc = extract_unsigned_integer (buf, tdep->addr_length, byte_order); return frame_unwind_got_constant (this_frame, regnum, pc); } @@ -725,9 +729,10 @@ z80_breakpoint_kind_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr) addr = bh.value_address (); else { - warning(_("Unable to determine inferior's software breakpoint type: " - "couldn't find `_break_handler' function in inferior. Will " - "be used default software breakpoint instruction RST 0x08.")); + warning ( + _ ("Unable to determine inferior's software breakpoint type: " + "couldn't find `_break_handler' function in inferior. Will " + "be used default software breakpoint instruction RST 0x08.")); addr = 0x0008; } } @@ -770,7 +775,7 @@ z80_sw_breakpoint_from_kind (struct gdbarch *gdbarch, int kind, int *size) static std::vector<CORE_ADDR> z80_software_single_step (struct regcache *regcache) { - static const int flag_mask[] = {1 << 6, 1 << 0, 1 << 2, 1 << 7}; + static const int flag_mask[] = { 1 << 6, 1 << 0, 1 << 2, 1 << 7 }; gdb_byte buf[8]; ULONGEST t; ULONGEST addr; @@ -781,11 +786,11 @@ z80_software_single_step (struct regcache *regcache) struct gdbarch *gdbarch = target_gdbarch (); regcache->cooked_read (Z80_PC_REGNUM, &addr); - read_memory (addr, buf, sizeof(buf)); + read_memory (addr, buf, sizeof (buf)); info = z80_get_insn_info (gdbarch, buf, &size); ret[0] = addr + size; if (info == NULL) /* possible in case of double prefix */ - { /* forced NOP, TODO: replace by NOP */ + { /* forced NOP, TODO: replace by NOP */ return ret; } opcode = buf[size - info->size]; /* take opcode instead of prefix */ @@ -823,22 +828,22 @@ z80_software_single_step (struct regcache *regcache) case insn_jr_d: case insn_jr_cc_d: addr += size; - addr += (signed char)buf[size-1]; + addr += (signed char) buf[size - 1]; break; case insn_jp_rr: if (size == 1) opcode = Z80_HL_REGNUM; else - opcode = (buf[size-2] & 0x20) ? Z80_IY_REGNUM : Z80_IX_REGNUM; + opcode = (buf[size - 2] & 0x20) ? Z80_IY_REGNUM : Z80_IX_REGNUM; regcache->cooked_read (opcode, &addr); break; case insn_jp_nn: case insn_jp_cc_nn: case insn_call_nn: case insn_call_cc_nn: - addr = buf[size-1] * 0x100 + buf[size-2]; + addr = buf[size - 1] * 0x100 + buf[size - 2]; if (info->size > 3) /* long instruction mode */ - addr = addr * 0x100 + buf[size-3]; + addr = addr * 0x100 + buf[size - 3]; break; case insn_rst_n: addr = opcode & 070; @@ -860,10 +865,13 @@ z80_software_single_step (struct regcache *regcache) static unsigned (*cache_ovly_region_table)[3] = 0; static unsigned cache_novly_regions; static CORE_ADDR cache_ovly_region_table_base = 0; + enum z80_ovly_index - { - Z80_VMA, Z80_OSIZE, Z80_MAPPED_TO_LMA - }; +{ + Z80_VMA, + Z80_OSIZE, + Z80_MAPPED_TO_LMA +}; static void z80_free_overlay_region_table (void) @@ -879,8 +887,8 @@ z80_free_overlay_region_table (void) Convert to host order. LEN is number of ints. */ static void -read_target_long_array (CORE_ADDR memaddr, unsigned int *myaddr, - int len, int size, enum bfd_endian byte_order) +read_target_long_array (CORE_ADDR memaddr, unsigned int *myaddr, int len, + int size, enum bfd_endian byte_order) { /* alloca is safe here, because regions array is very small. */ gdb_byte *buf = (gdb_byte *) alloca (len * size); @@ -902,20 +910,20 @@ z80_read_overlay_region_table () z80_free_overlay_region_table (); novly_regions_msym = lookup_minimal_symbol ("_novly_regions", NULL, NULL); - if (! novly_regions_msym.minsym) + if (!novly_regions_msym.minsym) { - error (_("Error reading inferior's overlay table: " - "couldn't find `_novly_regions'\n" - "variable in inferior. Use `overlay manual' mode.")); + error (_ ("Error reading inferior's overlay table: " + "couldn't find `_novly_regions'\n" + "variable in inferior. Use `overlay manual' mode.")); return 0; } ovly_region_table_msym = lookup_bound_minimal_symbol ("_ovly_region_table"); - if (! ovly_region_table_msym.minsym) + if (!ovly_region_table_msym.minsym) { - error (_("Error reading inferior's overlay table: couldn't find " - "`_ovly_region_table'\n" - "array in inferior. Use `overlay manual' mode.")); + error (_ ("Error reading inferior's overlay table: couldn't find " + "`_ovly_region_table'\n" + "array in inferior. Use `overlay manual' mode.")); return 0; } @@ -927,19 +935,18 @@ z80_read_overlay_region_table () word_size = gdbarch_long_bit (gdbarch) / TARGET_CHAR_BIT; byte_order = gdbarch_byte_order (gdbarch); - cache_novly_regions = read_memory_integer (novly_regions_msym.value_address (), - 4, byte_order); + cache_novly_regions + = read_memory_integer (novly_regions_msym.value_address (), 4, byte_order); cache_ovly_region_table - = (unsigned int (*)[3]) xmalloc (cache_novly_regions * - sizeof (*cache_ovly_region_table)); - cache_ovly_region_table_base - = ovly_region_table_msym.value_address (); + = (unsigned int (*)[3]) xmalloc (cache_novly_regions + * sizeof (*cache_ovly_region_table)); + cache_ovly_region_table_base = ovly_region_table_msym.value_address (); read_target_long_array (cache_ovly_region_table_base, (unsigned int *) cache_ovly_region_table, cache_novly_regions * 3, word_size, byte_order); overlay_debugging = save_ovly_dbg; - return 1; /* SUCCESS */ + return 1; /* SUCCESS */ } static int @@ -953,7 +960,7 @@ z80_overlay_update_1 (struct obj_section *osect) /* find region corresponding to the section VMA */ for (i = 0; i < cache_novly_regions; i++) if (cache_ovly_region_table[i][Z80_VMA] == vma) - break; + break; if (i == cache_novly_regions) return 0; /* no such region */ @@ -965,8 +972,10 @@ z80_overlay_update_1 (struct obj_section *osect) ALL_OBJFILE_OSECTIONS (objfile, osect) if (section_is_overlay (osect)) { - osect->ovly_mapped = (lma == bfd_section_lma (osect->the_bfd_section)); - i |= osect->ovly_mapped; /* true, if at least one section is mapped */ + osect->ovly_mapped + = (lma == bfd_section_lma (osect->the_bfd_section)); + i |= osect + ->ovly_mapped; /* true, if at least one section is mapped */ } return i; } @@ -996,8 +1005,8 @@ z80_overlay_update (struct obj_section *osect) for (int i = 0; i < cache_novly_regions; ++i) if (cache_ovly_region_table[i][Z80_VMA] == vma) - osect->ovly_mapped = - (cache_ovly_region_table[i][Z80_MAPPED_TO_LMA] == lma); + osect->ovly_mapped + = (cache_ovly_region_table[i][Z80_MAPPED_TO_LMA] == lma); } } @@ -1008,7 +1017,7 @@ z80_insn_is_call (struct gdbarch *gdbarch, CORE_ADDR addr) gdb_byte buf[8]; int size; const struct z80_insn_info *info; - read_memory (addr, buf, sizeof(buf)); + read_memory (addr, buf, sizeof (buf)); info = z80_get_insn_info (gdbarch, buf, &size); if (info) switch (info->type) @@ -1028,7 +1037,7 @@ z80_insn_is_ret (struct gdbarch *gdbarch, CORE_ADDR addr) gdb_byte buf[8]; int size; const struct z80_insn_info *info; - read_memory (addr, buf, sizeof(buf)); + read_memory (addr, buf, sizeof (buf)); info = z80_get_insn_info (gdbarch, buf, &size); if (info) switch (info->type) @@ -1047,7 +1056,7 @@ z80_insn_is_jump (struct gdbarch *gdbarch, CORE_ADDR addr) gdb_byte buf[8]; int size; const struct z80_insn_info *info; - read_memory (addr, buf, sizeof(buf)); + read_memory (addr, buf, sizeof (buf)); info = z80_get_insn_info (gdbarch, buf, &size); if (info) switch (info->type) @@ -1063,9 +1072,7 @@ z80_insn_is_jump (struct gdbarch *gdbarch, CORE_ADDR addr) return 0; } -static const struct frame_unwind -z80_frame_unwind = -{ +static const struct frame_unwind z80_frame_unwind = { "z80", NORMAL_FRAME, default_frame_unwind_stop_reason, @@ -1139,12 +1146,12 @@ z80_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) /* Create a type for PC. We can't use builtin types here, as they may not be defined. */ - tdep->void_type = arch_type (gdbarch, TYPE_CODE_VOID, TARGET_CHAR_BIT, - "void"); + tdep->void_type + = arch_type (gdbarch, TYPE_CODE_VOID, TARGET_CHAR_BIT, "void"); tdep->func_void_type = make_function_type (tdep->void_type, NULL); - tdep->pc_type = arch_pointer_type (gdbarch, - tdep->addr_length * TARGET_CHAR_BIT, - NULL, tdep->func_void_type); + tdep->pc_type + = arch_pointer_type (gdbarch, tdep->addr_length * TARGET_CHAR_BIT, NULL, + tdep->func_void_type); set_gdbarch_short_bit (gdbarch, TARGET_CHAR_BIT); set_gdbarch_int_bit (gdbarch, 2 * TARGET_CHAR_BIT); @@ -1190,198 +1197,187 @@ z80_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) } /* Table to disassemble machine codes without prefix. */ -static const struct z80_insn_info -ez80_main_insn_table[] = -{ /* table with double prefix check */ - { 0100, 0377, 0, insn_force_nop}, //double prefix - { 0111, 0377, 0, insn_force_nop}, //double prefix - { 0122, 0377, 0, insn_force_nop}, //double prefix - { 0133, 0377, 0, insn_force_nop}, //double prefix +static const struct z80_insn_info ez80_main_insn_table[] = { + /* table with double prefix check */ + { 0100, 0377, 0, insn_force_nop }, //double prefix + { 0111, 0377, 0, insn_force_nop }, //double prefix + { 0122, 0377, 0, insn_force_nop }, //double prefix + { 0133, 0377, 0, insn_force_nop }, //double prefix /* initial table for eZ80_z80 */ - { 0100, 0377, 1, insn_z80 }, //eZ80 mode prefix - { 0111, 0377, 1, insn_z80 }, //eZ80 mode prefix - { 0122, 0377, 1, insn_adl }, //eZ80 mode prefix - { 0133, 0377, 1, insn_adl }, //eZ80 mode prefix + { 0100, 0377, 1, insn_z80 }, //eZ80 mode prefix + { 0111, 0377, 1, insn_z80 }, //eZ80 mode prefix + { 0122, 0377, 1, insn_adl }, //eZ80 mode prefix + { 0133, 0377, 1, insn_adl }, //eZ80 mode prefix /* here common Z80/Z180/eZ80 opcodes */ - { 0000, 0367, 1, insn_default }, //"nop", "ex af,af'" - { 0061, 0377, 3, insn_ld_sp_nn }, //"ld sp,nn" - { 0001, 0317, 3, insn_default }, //"ld rr,nn" - { 0002, 0347, 1, insn_default }, //"ld (rr),a", "ld a,(rr)" - { 0042, 0347, 3, insn_default }, //"ld (nn),hl/a", "ld hl/a,(nn)" - { 0063, 0377, 1, insn_inc_sp }, //"inc sp" - { 0073, 0377, 1, insn_dec_sp }, //"dec sp" - { 0003, 0303, 1, insn_default }, //"inc rr", "dec rr", ... - { 0004, 0307, 1, insn_default }, //"inc/dec r/(hl)" - { 0006, 0307, 2, insn_default }, //"ld r,n", "ld (hl),n" - { 0020, 0377, 2, insn_djnz_d }, //"djnz dis" - { 0030, 0377, 2, insn_jr_d }, //"jr dis" - { 0040, 0347, 2, insn_jr_cc_d }, //"jr cc,dis" - { 0100, 0300, 1, insn_default }, //"ld r,r", "halt" - { 0200, 0300, 1, insn_default }, //"alu_op a,r" - { 0300, 0307, 1, insn_ret_cc }, //"ret cc" - { 0301, 0317, 1, insn_pop_rr }, //"pop rr" - { 0302, 0307, 3, insn_jp_cc_nn }, //"jp cc,nn" - { 0303, 0377, 3, insn_jp_nn }, //"jp nn" - { 0304, 0307, 3, insn_call_cc_nn}, //"call cc,nn" - { 0305, 0317, 1, insn_push_rr }, //"push rr" - { 0306, 0307, 2, insn_default }, //"alu_op a,n" - { 0307, 0307, 1, insn_rst_n }, //"rst n" - { 0311, 0377, 1, insn_ret }, //"ret" - { 0313, 0377, 2, insn_default }, //CB prefix - { 0315, 0377, 3, insn_call_nn }, //"call nn" - { 0323, 0367, 2, insn_default }, //"out (n),a", "in a,(n)" - { 0335, 0337, 1, insn_z80_ddfd }, //DD/FD prefix - { 0351, 0377, 1, insn_jp_rr }, //"jp (hl)" - { 0355, 0377, 1, insn_z80_ed }, //ED prefix - { 0371, 0377, 1, insn_ld_sp_rr }, //"ld sp,hl" - { 0000, 0000, 1, insn_default } //others -} ; - -static const struct z80_insn_info -ez80_adl_main_insn_table[] = -{ /* table with double prefix check */ - { 0100, 0377, 0, insn_force_nop}, //double prefix - { 0111, 0377, 0, insn_force_nop}, //double prefix - { 0122, 0377, 0, insn_force_nop}, //double prefix - { 0133, 0377, 0, insn_force_nop}, //double prefix + { 0000, 0367, 1, insn_default }, //"nop", "ex af,af'" + { 0061, 0377, 3, insn_ld_sp_nn }, //"ld sp,nn" + { 0001, 0317, 3, insn_default }, //"ld rr,nn" + { 0002, 0347, 1, insn_default }, //"ld (rr),a", "ld a,(rr)" + { 0042, 0347, 3, insn_default }, //"ld (nn),hl/a", "ld hl/a,(nn)" + { 0063, 0377, 1, insn_inc_sp }, //"inc sp" + { 0073, 0377, 1, insn_dec_sp }, //"dec sp" + { 0003, 0303, 1, insn_default }, //"inc rr", "dec rr", ... + { 0004, 0307, 1, insn_default }, //"inc/dec r/(hl)" + { 0006, 0307, 2, insn_default }, //"ld r,n", "ld (hl),n" + { 0020, 0377, 2, insn_djnz_d }, //"djnz dis" + { 0030, 0377, 2, insn_jr_d }, //"jr dis" + { 0040, 0347, 2, insn_jr_cc_d }, //"jr cc,dis" + { 0100, 0300, 1, insn_default }, //"ld r,r", "halt" + { 0200, 0300, 1, insn_default }, //"alu_op a,r" + { 0300, 0307, 1, insn_ret_cc }, //"ret cc" + { 0301, 0317, 1, insn_pop_rr }, //"pop rr" + { 0302, 0307, 3, insn_jp_cc_nn }, //"jp cc,nn" + { 0303, 0377, 3, insn_jp_nn }, //"jp nn" + { 0304, 0307, 3, insn_call_cc_nn }, //"call cc,nn" + { 0305, 0317, 1, insn_push_rr }, //"push rr" + { 0306, 0307, 2, insn_default }, //"alu_op a,n" + { 0307, 0307, 1, insn_rst_n }, //"rst n" + { 0311, 0377, 1, insn_ret }, //"ret" + { 0313, 0377, 2, insn_default }, //CB prefix + { 0315, 0377, 3, insn_call_nn }, //"call nn" + { 0323, 0367, 2, insn_default }, //"out (n),a", "in a,(n)" + { 0335, 0337, 1, insn_z80_ddfd }, //DD/FD prefix + { 0351, 0377, 1, insn_jp_rr }, //"jp (hl)" + { 0355, 0377, 1, insn_z80_ed }, //ED prefix + { 0371, 0377, 1, insn_ld_sp_rr }, //"ld sp,hl" + { 0000, 0000, 1, insn_default } //others +}; + +static const struct z80_insn_info ez80_adl_main_insn_table[] = { + /* table with double prefix check */ + { 0100, 0377, 0, insn_force_nop }, //double prefix + { 0111, 0377, 0, insn_force_nop }, //double prefix + { 0122, 0377, 0, insn_force_nop }, //double prefix + { 0133, 0377, 0, insn_force_nop }, //double prefix /* initial table for eZ80_adl */ - { 0000, 0367, 1, insn_default }, //"nop", "ex af,af'" - { 0061, 0377, 4, insn_ld_sp_nn }, //"ld sp,Mmn" - { 0001, 0317, 4, insn_default }, //"ld rr,Mmn" - { 0002, 0347, 1, insn_default }, //"ld (rr),a", "ld a,(rr)" - { 0042, 0347, 4, insn_default }, //"ld (Mmn),hl/a", "ld hl/a,(Mmn)" - { 0063, 0377, 1, insn_inc_sp }, //"inc sp" - { 0073, 0377, 1, insn_dec_sp }, //"dec sp" - { 0003, 0303, 1, insn_default }, //"inc rr", "dec rr", ... - { 0004, 0307, 1, insn_default }, //"inc/dec r/(hl)" - { 0006, 0307, 2, insn_default }, //"ld r,n", "ld (hl),n" - { 0020, 0377, 2, insn_djnz_d }, //"djnz dis" - { 0030, 0377, 2, insn_jr_d }, //"jr dis" - { 0040, 0347, 2, insn_jr_cc_d }, //"jr cc,dis" - { 0100, 0377, 1, insn_z80 }, //eZ80 mode prefix (short instruction) - { 0111, 0377, 1, insn_z80 }, //eZ80 mode prefix (short instruction) - { 0122, 0377, 1, insn_adl }, //eZ80 mode prefix (long instruction) - { 0133, 0377, 1, insn_adl }, //eZ80 mode prefix (long instruction) - { 0100, 0300, 1, insn_default }, //"ld r,r", "halt" - { 0200, 0300, 1, insn_default }, //"alu_op a,r" - { 0300, 0307, 1, insn_ret_cc }, //"ret cc" - { 0301, 0317, 1, insn_pop_rr }, //"pop rr" - { 0302, 0307, 4, insn_jp_cc_nn }, //"jp cc,nn" - { 0303, 0377, 4, insn_jp_nn }, //"jp nn" - { 0304, 0307, 4, insn_call_cc_nn}, //"call cc,Mmn" - { 0305, 0317, 1, insn_push_rr }, //"push rr" - { 0306, 0307, 2, insn_default }, //"alu_op a,n" - { 0307, 0307, 1, insn_rst_n }, //"rst n" - { 0311, 0377, 1, insn_ret }, //"ret" - { 0313, 0377, 2, insn_default }, //CB prefix - { 0315, 0377, 4, insn_call_nn }, //"call Mmn" - { 0323, 0367, 2, insn_default }, //"out (n),a", "in a,(n)" - { 0335, 0337, 1, insn_adl_ddfd }, //DD/FD prefix - { 0351, 0377, 1, insn_jp_rr }, //"jp (hl)" - { 0355, 0377, 1, insn_adl_ed }, //ED prefix - { 0371, 0377, 1, insn_ld_sp_rr }, //"ld sp,hl" - { 0000, 0000, 1, insn_default } //others + { 0000, 0367, 1, insn_default }, //"nop", "ex af,af'" + { 0061, 0377, 4, insn_ld_sp_nn }, //"ld sp,Mmn" + { 0001, 0317, 4, insn_default }, //"ld rr,Mmn" + { 0002, 0347, 1, insn_default }, //"ld (rr),a", "ld a,(rr)" + { 0042, 0347, 4, insn_default }, //"ld (Mmn),hl/a", "ld hl/a,(Mmn)" + { 0063, 0377, 1, insn_inc_sp }, //"inc sp" + { 0073, 0377, 1, insn_dec_sp }, //"dec sp" + { 0003, 0303, 1, insn_default }, //"inc rr", "dec rr", ... + { 0004, 0307, 1, insn_default }, //"inc/dec r/(hl)" + { 0006, 0307, 2, insn_default }, //"ld r,n", "ld (hl),n" + { 0020, 0377, 2, insn_djnz_d }, //"djnz dis" + { 0030, 0377, 2, insn_jr_d }, //"jr dis" + { 0040, 0347, 2, insn_jr_cc_d }, //"jr cc,dis" + { 0100, 0377, 1, insn_z80 }, //eZ80 mode prefix (short instruction) + { 0111, 0377, 1, insn_z80 }, //eZ80 mode prefix (short instruction) + { 0122, 0377, 1, insn_adl }, //eZ80 mode prefix (long instruction) + { 0133, 0377, 1, insn_adl }, //eZ80 mode prefix (long instruction) + { 0100, 0300, 1, insn_default }, //"ld r,r", "halt" + { 0200, 0300, 1, insn_default }, //"alu_op a,r" + { 0300, 0307, 1, insn_ret_cc }, //"ret cc" + { 0301, 0317, 1, insn_pop_rr }, //"pop rr" + { 0302, 0307, 4, insn_jp_cc_nn }, //"jp cc,nn" + { 0303, 0377, 4, insn_jp_nn }, //"jp nn" + { 0304, 0307, 4, insn_call_cc_nn }, //"call cc,Mmn" + { 0305, 0317, 1, insn_push_rr }, //"push rr" + { 0306, 0307, 2, insn_default }, //"alu_op a,n" + { 0307, 0307, 1, insn_rst_n }, //"rst n" + { 0311, 0377, 1, insn_ret }, //"ret" + { 0313, 0377, 2, insn_default }, //CB prefix + { 0315, 0377, 4, insn_call_nn }, //"call Mmn" + { 0323, 0367, 2, insn_default }, //"out (n),a", "in a,(n)" + { 0335, 0337, 1, insn_adl_ddfd }, //DD/FD prefix + { 0351, 0377, 1, insn_jp_rr }, //"jp (hl)" + { 0355, 0377, 1, insn_adl_ed }, //ED prefix + { 0371, 0377, 1, insn_ld_sp_rr }, //"ld sp,hl" + { 0000, 0000, 1, insn_default } //others }; /* ED prefix opcodes table. Note the instruction length does include the ED prefix (+ 1 byte) */ -static const struct z80_insn_info -ez80_ed_insn_table[] = -{ +static const struct z80_insn_info ez80_ed_insn_table[] = { /* eZ80 only instructions */ - { 0002, 0366, 2, insn_default }, //"lea rr,ii+d" - { 0124, 0376, 2, insn_default }, //"lea ix,iy+d", "lea iy,ix+d" - { 0145, 0377, 2, insn_default }, //"pea ix+d" - { 0146, 0377, 2, insn_default }, //"pea iy+d" - { 0164, 0377, 2, insn_default }, //"tstio n" - /* Z180/eZ80 only instructions */ - { 0060, 0376, 1, insn_default }, //not an instruction - { 0000, 0306, 2, insn_default }, //"in0 r,(n)", "out0 (n),r" - { 0144, 0377, 2, insn_default }, //"tst a, n" - /* common instructions */ - { 0173, 0377, 3, insn_ld_sp_6nn9 }, //"ld sp,(nn)" - { 0103, 0307, 3, insn_default }, //"ld (nn),rr", "ld rr,(nn)" - { 0105, 0317, 1, insn_ret }, //"retn", "reti" - { 0000, 0000, 1, insn_default } -}; - -static const struct z80_insn_info -ez80_adl_ed_insn_table[] = -{ { 0002, 0366, 2, insn_default }, //"lea rr,ii+d" { 0124, 0376, 2, insn_default }, //"lea ix,iy+d", "lea iy,ix+d" { 0145, 0377, 2, insn_default }, //"pea ix+d" { 0146, 0377, 2, insn_default }, //"pea iy+d" { 0164, 0377, 2, insn_default }, //"tstio n" + /* Z180/eZ80 only instructions */ { 0060, 0376, 1, insn_default }, //not an instruction { 0000, 0306, 2, insn_default }, //"in0 r,(n)", "out0 (n),r" { 0144, 0377, 2, insn_default }, //"tst a, n" - { 0173, 0377, 4, insn_ld_sp_6nn9 }, //"ld sp,(nn)" - { 0103, 0307, 4, insn_default }, //"ld (nn),rr", "ld rr,(nn)" - { 0105, 0317, 1, insn_ret }, //"retn", "reti" + /* common instructions */ + { 0173, 0377, 3, insn_ld_sp_6nn9 }, //"ld sp,(nn)" + { 0103, 0307, 3, insn_default }, //"ld (nn),rr", "ld rr,(nn)" + { 0105, 0317, 1, insn_ret }, //"retn", "reti" { 0000, 0000, 1, insn_default } }; +static const struct z80_insn_info ez80_adl_ed_insn_table[] + = { { 0002, 0366, 2, insn_default }, //"lea rr,ii+d" + { 0124, 0376, 2, insn_default }, //"lea ix,iy+d", "lea iy,ix+d" + { 0145, 0377, 2, insn_default }, //"pea ix+d" + { 0146, 0377, 2, insn_default }, //"pea iy+d" + { 0164, 0377, 2, insn_default }, //"tstio n" + { 0060, 0376, 1, insn_default }, //not an instruction + { 0000, 0306, 2, insn_default }, //"in0 r,(n)", "out0 (n),r" + { 0144, 0377, 2, insn_default }, //"tst a, n" + { 0173, 0377, 4, insn_ld_sp_6nn9 }, //"ld sp,(nn)" + { 0103, 0307, 4, insn_default }, //"ld (nn),rr", "ld rr,(nn)" + { 0105, 0317, 1, insn_ret }, //"retn", "reti" + { 0000, 0000, 1, insn_default } }; + /* table for FD and DD prefixed instructions */ -static const struct z80_insn_info -ez80_ddfd_insn_table[] = -{ +static const struct z80_insn_info ez80_ddfd_insn_table[] = { /* ez80 only instructions */ { 0007, 0307, 2, insn_default }, //"ld rr,(ii+d)" { 0061, 0377, 2, insn_default }, //"ld ii,(ii+d)" /* common instructions */ - { 0011, 0367, 2, insn_default }, //"add ii,rr" - { 0041, 0377, 3, insn_default }, //"ld ii,nn" - { 0042, 0367, 3, insn_default }, //"ld (nn),ii", "ld ii,(nn)" - { 0043, 0367, 1, insn_default }, //"inc ii", "dec ii" - { 0044, 0366, 1, insn_default }, //"inc/dec iih/iil" - { 0046, 0367, 2, insn_default }, //"ld iih,n", "ld iil,n" - { 0064, 0376, 2, insn_default }, //"inc (ii+d)", "dec (ii+d)" - { 0066, 0377, 2, insn_default }, //"ld (ii+d),n" - { 0166, 0377, 0, insn_default }, //not an instruction - { 0160, 0370, 2, insn_default }, //"ld (ii+d),r" - { 0104, 0306, 1, insn_default }, //"ld r,iih", "ld r,iil" - { 0106, 0307, 2, insn_default }, //"ld r,(ii+d)" - { 0140, 0360, 1, insn_default }, //"ld iih,r", "ld iil,r" - { 0204, 0306, 1, insn_default }, //"alu_op a,iih", "alu_op a,iil" - { 0206, 0307, 2, insn_default }, //"alu_op a,(ii+d)" - { 0313, 0377, 3, insn_default }, //DD/FD CB dd oo instructions - { 0335, 0337, 0, insn_force_nop}, //double DD/FD prefix, exec DD/FD as NOP - { 0341, 0373, 1, insn_default }, //"pop ii", "push ii" - { 0343, 0377, 1, insn_default }, //"ex (sp),ii" - { 0351, 0377, 1, insn_jp_rr }, //"jp (ii)" - { 0371, 0377, 1, insn_ld_sp_rr}, //"ld sp,ii" - { 0000, 0000, 0, insn_default } //not an instruction, exec DD/FD as NOP + { 0011, 0367, 2, insn_default }, //"add ii,rr" + { 0041, 0377, 3, insn_default }, //"ld ii,nn" + { 0042, 0367, 3, insn_default }, //"ld (nn),ii", "ld ii,(nn)" + { 0043, 0367, 1, insn_default }, //"inc ii", "dec ii" + { 0044, 0366, 1, insn_default }, //"inc/dec iih/iil" + { 0046, 0367, 2, insn_default }, //"ld iih,n", "ld iil,n" + { 0064, 0376, 2, insn_default }, //"inc (ii+d)", "dec (ii+d)" + { 0066, 0377, 2, insn_default }, //"ld (ii+d),n" + { 0166, 0377, 0, insn_default }, //not an instruction + { 0160, 0370, 2, insn_default }, //"ld (ii+d),r" + { 0104, 0306, 1, insn_default }, //"ld r,iih", "ld r,iil" + { 0106, 0307, 2, insn_default }, //"ld r,(ii+d)" + { 0140, 0360, 1, insn_default }, //"ld iih,r", "ld iil,r" + { 0204, 0306, 1, insn_default }, //"alu_op a,iih", "alu_op a,iil" + { 0206, 0307, 2, insn_default }, //"alu_op a,(ii+d)" + { 0313, 0377, 3, insn_default }, //DD/FD CB dd oo instructions + { 0335, 0337, 0, insn_force_nop }, //double DD/FD prefix, exec DD/FD as NOP + { 0341, 0373, 1, insn_default }, //"pop ii", "push ii" + { 0343, 0377, 1, insn_default }, //"ex (sp),ii" + { 0351, 0377, 1, insn_jp_rr }, //"jp (ii)" + { 0371, 0377, 1, insn_ld_sp_rr }, //"ld sp,ii" + { 0000, 0000, 0, insn_default } //not an instruction, exec DD/FD as NOP }; -static const struct z80_insn_info -ez80_adl_ddfd_insn_table[] = -{ - { 0007, 0307, 2, insn_default }, //"ld rr,(ii+d)" - { 0061, 0377, 2, insn_default }, //"ld ii,(ii+d)" - { 0011, 0367, 1, insn_default }, //"add ii,rr" - { 0041, 0377, 4, insn_default }, //"ld ii,nn" - { 0042, 0367, 4, insn_default }, //"ld (nn),ii", "ld ii,(nn)" - { 0043, 0367, 1, insn_default }, //"inc ii", "dec ii" - { 0044, 0366, 1, insn_default }, //"inc/dec iih/iil" - { 0046, 0367, 2, insn_default }, //"ld iih,n", "ld iil,n" - { 0064, 0376, 2, insn_default }, //"inc (ii+d)", "dec (ii+d)" - { 0066, 0377, 3, insn_default }, //"ld (ii+d),n" - { 0166, 0377, 0, insn_default }, //not an instruction - { 0160, 0370, 2, insn_default }, //"ld (ii+d),r" - { 0104, 0306, 1, insn_default }, //"ld r,iih", "ld r,iil" - { 0106, 0307, 2, insn_default }, //"ld r,(ii+d)" - { 0140, 0360, 1, insn_default }, //"ld iih,r", "ld iil,r" - { 0204, 0306, 1, insn_default }, //"alu_op a,iih", "alu_op a,iil" - { 0206, 0307, 2, insn_default }, //"alu_op a,(ii+d)" - { 0313, 0377, 3, insn_default }, //DD/FD CB dd oo instructions - { 0335, 0337, 0, insn_force_nop}, //double DD/FD prefix, exec DD/FD as NOP - { 0341, 0373, 1, insn_default }, //"pop ii", "push ii" - { 0343, 0377, 1, insn_default }, //"ex (sp),ii" - { 0351, 0377, 1, insn_jp_rr }, //"jp (ii)" - { 0371, 0377, 1, insn_ld_sp_rr}, //"ld sp,ii" - { 0000, 0000, 0, insn_default } //not an instruction, exec DD/FD as NOP +static const struct z80_insn_info ez80_adl_ddfd_insn_table[] = { + { 0007, 0307, 2, insn_default }, //"ld rr,(ii+d)" + { 0061, 0377, 2, insn_default }, //"ld ii,(ii+d)" + { 0011, 0367, 1, insn_default }, //"add ii,rr" + { 0041, 0377, 4, insn_default }, //"ld ii,nn" + { 0042, 0367, 4, insn_default }, //"ld (nn),ii", "ld ii,(nn)" + { 0043, 0367, 1, insn_default }, //"inc ii", "dec ii" + { 0044, 0366, 1, insn_default }, //"inc/dec iih/iil" + { 0046, 0367, 2, insn_default }, //"ld iih,n", "ld iil,n" + { 0064, 0376, 2, insn_default }, //"inc (ii+d)", "dec (ii+d)" + { 0066, 0377, 3, insn_default }, //"ld (ii+d),n" + { 0166, 0377, 0, insn_default }, //not an instruction + { 0160, 0370, 2, insn_default }, //"ld (ii+d),r" + { 0104, 0306, 1, insn_default }, //"ld r,iih", "ld r,iil" + { 0106, 0307, 2, insn_default }, //"ld r,(ii+d)" + { 0140, 0360, 1, insn_default }, //"ld iih,r", "ld iil,r" + { 0204, 0306, 1, insn_default }, //"alu_op a,iih", "alu_op a,iil" + { 0206, 0307, 2, insn_default }, //"alu_op a,(ii+d)" + { 0313, 0377, 3, insn_default }, //DD/FD CB dd oo instructions + { 0335, 0337, 0, insn_force_nop }, //double DD/FD prefix, exec DD/FD as NOP + { 0341, 0373, 1, insn_default }, //"pop ii", "push ii" + { 0343, 0377, 1, insn_default }, //"ex (sp),ii" + { 0351, 0377, 1, insn_jp_rr }, //"jp (ii)" + { 0371, 0377, 1, insn_ld_sp_rr }, //"ld sp,ii" + { 0000, 0000, 0, insn_default } //not an instruction, exec DD/FD as NOP }; /* Return pointer to instruction information structure corresponded to opcode |