diff options
Diffstat (limited to 'gdb/sparc-tdep.c')
| -rw-r--r-- | gdb/sparc-tdep.c | 321 |
1 files changed, 140 insertions, 181 deletions
diff --git a/gdb/sparc-tdep.c b/gdb/sparc-tdep.c index bd3dc94..83cf1e1 100644 --- a/gdb/sparc-tdep.c +++ b/gdb/sparc-tdep.c @@ -73,16 +73,17 @@ struct regset; #define X_A(i) (((i) >> 29) & 1) #define X_COND(i) (((i) >> 25) & 0xf) #define X_OP2(i) (((i) >> 22) & 0x7) -#define X_IMM22(i) ((i) & 0x3fffff) +#define X_IMM22(i) ((i) &0x3fffff) #define X_OP3(i) (((i) >> 19) & 0x3f) #define X_RS1(i) (((i) >> 14) & 0x1f) -#define X_RS2(i) ((i) & 0x1f) +#define X_RS2(i) ((i) &0x1f) #define X_I(i) (((i) >> 13) & 1) /* Sign extension macros. */ #define X_DISP22(i) ((X_IMM22 (i) ^ 0x200000) - 0x200000) -#define X_DISP19(i) ((((i) & 0x7ffff) ^ 0x40000) - 0x40000) -#define X_DISP10(i) ((((((i) >> 11) && 0x300) | (((i) >> 5) & 0xff)) ^ 0x200) - 0x200) -#define X_SIMM13(i) ((((i) & 0x1fff) ^ 0x1000) - 0x1000) +#define X_DISP19(i) ((((i) &0x7ffff) ^ 0x40000) - 0x40000) +#define X_DISP10(i) \ + ((((((i) >> 11) && 0x300) | (((i) >> 5) & 0xff)) ^ 0x200) - 0x200) +#define X_SIMM13(i) ((((i) &0x1fff) ^ 0x1000) - 0x1000) /* Macros to identify some instructions. */ /* RETURN (RETT in V8) */ #define X_RETTURN(i) ((X_OP (i) == 0x2) && (X_OP3 (i) == 0x39)) @@ -106,7 +107,6 @@ sparc_fetch_instruction (CORE_ADDR pc) insn = (insn << 8) | buf[i]; return insn; } - /* Return non-zero if the instruction corresponding to PC is an "unimp" instruction. */ @@ -115,7 +115,7 @@ static int sparc_is_unimp_insn (CORE_ADDR pc) { const unsigned long insn = sparc_fetch_instruction (pc); - + return ((insn & 0xc1c00000) == 0); } @@ -198,7 +198,6 @@ sparc_fetch_wcookie (struct gdbarch *gdbarch) return extract_unsigned_integer (buf, len, byte_order); } - /* The functions on this page are intended to be used to classify function arguments. */ @@ -351,30 +350,22 @@ sparc_arg_by_memory_p (const struct type *type) } /* Register information. */ -#define SPARC32_FPU_REGISTERS \ - "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \ - "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", \ - "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", \ - "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31" +#define SPARC32_FPU_REGISTERS \ + "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", "f9", "f10", "f11", \ + "f12", "f13", "f14", "f15", "f16", "f17", "f18", "f19", "f20", "f21", \ + "f22", "f23", "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31" #define SPARC32_CP0_REGISTERS \ "y", "psr", "wim", "tbr", "pc", "npc", "fsr", "csr" -static const char * const sparc_core_register_names[] = { - SPARC_CORE_REGISTERS -}; -static const char * const sparc32_fpu_register_names[] = { - SPARC32_FPU_REGISTERS -}; -static const char * const sparc32_cp0_register_names[] = { - SPARC32_CP0_REGISTERS -}; +static const char *const sparc_core_register_names[] + = { SPARC_CORE_REGISTERS }; +static const char *const sparc32_fpu_register_names[] + = { SPARC32_FPU_REGISTERS }; +static const char *const sparc32_cp0_register_names[] + = { SPARC32_CP0_REGISTERS }; -static const char * const sparc32_register_names[] = -{ - SPARC_CORE_REGISTERS, - SPARC32_FPU_REGISTERS, - SPARC32_CP0_REGISTERS -}; +static const char *const sparc32_register_names[] + = { SPARC_CORE_REGISTERS, SPARC32_FPU_REGISTERS, SPARC32_CP0_REGISTERS }; /* Total number of registers. */ #define SPARC32_NUM_REGS ARRAY_SIZE (sparc32_register_names) @@ -382,11 +373,9 @@ static const char * const sparc32_register_names[] = /* We provide the aliases %d0..%d30 for the floating registers as "psuedo" registers. */ -static const char * const sparc32_pseudo_register_names[] = -{ - "d0", "d2", "d4", "d6", "d8", "d10", "d12", "d14", - "d16", "d18", "d20", "d22", "d24", "d26", "d28", "d30" -}; +static const char *const sparc32_pseudo_register_names[] + = { "d0", "d2", "d4", "d6", "d8", "d10", "d12", "d14", + "d16", "d18", "d20", "d22", "d24", "d26", "d28", "d30" }; /* Total number of pseudo registers. */ #define SPARC32_NUM_PSEUDO_REGS ARRAY_SIZE (sparc32_pseudo_register_names) @@ -415,7 +404,7 @@ sparc32_register_name (struct gdbarch *gdbarch, int regnum) return sparc32_pseudo_register_name (gdbarch, regnum); } - + /* Construct types for ISA-specific registers. */ static struct type * @@ -484,7 +473,7 @@ sparc32_pseudo_register_type (struct gdbarch *gdbarch, int regnum) if (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM) return builtin_type (gdbarch)->builtin_double; - internal_error (_("sparc32_pseudo_register_type: bad register number %d"), + internal_error (_ ("sparc32_pseudo_register_type: bad register number %d"), regnum); } @@ -520,8 +509,8 @@ sparc32_register_type (struct gdbarch *gdbarch, int regnum) static enum register_status sparc32_pseudo_register_read (struct gdbarch *gdbarch, - readable_regcache *regcache, - int regnum, gdb_byte *buf) + readable_regcache *regcache, int regnum, + gdb_byte *buf) { enum register_status status; @@ -537,8 +526,8 @@ sparc32_pseudo_register_read (struct gdbarch *gdbarch, static void sparc32_pseudo_register_write (struct gdbarch *gdbarch, - struct regcache *regcache, - int regnum, const gdb_byte *buf) + struct regcache *regcache, int regnum, + const gdb_byte *buf) { regnum -= gdbarch_num_regs (gdbarch); gdb_assert (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM); @@ -547,7 +536,7 @@ sparc32_pseudo_register_write (struct gdbarch *gdbarch, regcache->raw_write (regnum, buf); regcache->raw_write (regnum + 1, buf + 4); } - + /* Implement the stack_frame_destroyed_p gdbarch method. */ int @@ -570,7 +559,6 @@ sparc_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc) return X_RETTURN (insn); } - static CORE_ADDR sparc32_frame_align (struct gdbarch *gdbarch, CORE_ADDR address) @@ -581,11 +569,9 @@ sparc32_frame_align (struct gdbarch *gdbarch, CORE_ADDR address) static CORE_ADDR sparc32_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, - CORE_ADDR funcaddr, - struct value **args, int nargs, - struct type *value_type, - CORE_ADDR *real_pc, CORE_ADDR *bp_addr, - struct regcache *regcache) + CORE_ADDR funcaddr, struct value **args, int nargs, + struct type *value_type, CORE_ADDR *real_pc, + CORE_ADDR *bp_addr, struct regcache *regcache) { enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); @@ -713,8 +699,8 @@ sparc32_push_dummy_call (struct gdbarch *gdbarch, struct value *function, function_call_return_method return_method, CORE_ADDR struct_addr) { - CORE_ADDR call_pc = (return_method == return_method_struct - ? (bp_addr - 12) : (bp_addr - 8)); + CORE_ADDR call_pc + = (return_method == return_method_struct ? (bp_addr - 12) : (bp_addr - 8)); /* Set return address. */ regcache_cooked_write_unsigned (regcache, SPARC_O7_REGNUM, call_pc); @@ -734,7 +720,6 @@ sparc32_push_dummy_call (struct gdbarch *gdbarch, struct value *function, return sp; } - /* Use the program counter to determine the contents and size of a breakpoint instruction. Return a pointer to a string of bytes that @@ -744,7 +729,6 @@ sparc32_push_dummy_call (struct gdbarch *gdbarch, struct value *function, constexpr gdb_byte sparc_break_insn[] = { 0x91, 0xd0, 0x20, 0x01 }; typedef BP_MANIPULATION (sparc_break_insn) sparc_breakpoint; - /* Allocate and initialize a frame cache. */ @@ -773,7 +757,7 @@ sparc_alloc_frame_cache (void) of each function prologue when compiling with -fstack-check. If one of such sequences starts at START_PC, then return the address of the instruction immediately past this sequence. Otherwise, return START_PC. */ - + static CORE_ADDR sparc_skip_stack_check (const CORE_ADDR start_pc) { @@ -819,7 +803,7 @@ sparc_skip_stack_check (const CORE_ADDR start_pc) } /* sub %sp, %g1, %g1 */ - if (!(X_OP (insn) == 2 && X_OP3 (insn) == 0x4 && !X_I(insn) + if (!(X_OP (insn) == 2 && X_OP3 (insn) == 0x4 && !X_I (insn) && X_RD (insn) == 1 && X_RS1 (insn) == 14 && X_RS2 (insn) == 1)) return start_pc; @@ -839,7 +823,7 @@ sparc_skip_stack_check (const CORE_ADDR start_pc) clr [%g1 - some immediate] */ /* clr [%g1 - some immediate] */ - if (X_OP (insn) == 3 && X_OP3(insn) == 0x4 && X_I(insn) + if (X_OP (insn) == 3 && X_OP3 (insn) == 0x4 && X_I (insn) && X_RS1 (insn) == 1 && X_RD (insn) == 0) { /* Valid stack-check sequence, return the new PC. */ @@ -855,35 +839,35 @@ sparc_skip_stack_check (const CORE_ADDR start_pc) clr [%g1 - some immediate] */ /* clr [%g1] */ - else if (X_OP (insn) == 3 && X_OP3(insn) == 0x4 && !X_I(insn) - && X_RS1 (insn) == 1 && X_RD (insn) == 0) + else if (X_OP (insn) == 3 && X_OP3 (insn) == 0x4 && !X_I (insn) + && X_RS1 (insn) == 1 && X_RD (insn) == 0) { while (1) { /* add %g1, -<some immediate>, %g1 */ insn = sparc_fetch_instruction (pc); pc = pc + 4; - if (!(X_OP (insn) == 2 && X_OP3(insn) == 0 && X_I(insn) + if (!(X_OP (insn) == 2 && X_OP3 (insn) == 0 && X_I (insn) && X_RS1 (insn) == 1 && X_RD (insn) == 1)) break; /* clr [%g1] */ insn = sparc_fetch_instruction (pc); pc = pc + 4; - if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 && !X_I(insn) + if (!(X_OP (insn) == 3 && X_OP3 (insn) == 0x4 && !X_I (insn) && X_RD (insn) == 0 && X_RS1 (insn) == 1)) return start_pc; } /* clr [%g1 - some immediate] */ - if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 && X_I(insn) + if (!(X_OP (insn) == 3 && X_OP3 (insn) == 0x4 && X_I (insn) && X_RS1 (insn) == 1 && X_RD (insn) == 0)) return start_pc; /* We found a valid stack-check sequence, return the new PC. */ return pc; } - + /* Third sequence: A probing loop. [first three instructions above] sub %g1, %g4, %g4 @@ -900,14 +884,14 @@ sparc_skip_stack_check (const CORE_ADDR start_pc) if (probing_loop) { /* sub %g1, %g4, %g4 */ - if (!(X_OP (insn) == 2 && X_OP3 (insn) == 0x4 && !X_I(insn) + if (!(X_OP (insn) == 2 && X_OP3 (insn) == 0x4 && !X_I (insn) && X_RD (insn) == 4 && X_RS1 (insn) == 1 && X_RS2 (insn) == 4)) return start_pc; /* cmp %g1, %g4 */ insn = sparc_fetch_instruction (pc); pc = pc + 4; - if (!(X_OP (insn) == 2 && X_OP3 (insn) == 0x14 && !X_I(insn) + if (!(X_OP (insn) == 2 && X_OP3 (insn) == 0x14 && !X_I (insn) && X_RD (insn) == 0 && X_RS1 (insn) == 1 && X_RS2 (insn) == 4)) return start_pc; @@ -920,7 +904,7 @@ sparc_skip_stack_check (const CORE_ADDR start_pc) /* add %g1, -<some immediate>, %g1 */ insn = sparc_fetch_instruction (pc); pc = pc + 4; - if (!(X_OP (insn) == 2 && X_OP3(insn) == 0 && X_I(insn) + if (!(X_OP (insn) == 2 && X_OP3 (insn) == 0 && X_I (insn) && X_RS1 (insn) == 1 && X_RD (insn) == 1)) return start_pc; @@ -933,9 +917,8 @@ sparc_skip_stack_check (const CORE_ADDR start_pc) /* clr [%g1] (st %g0, [%g1] or st %g0, [%g1+0]) */ insn = sparc_fetch_instruction (pc); pc = pc + 4; - if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 - && X_RD (insn) == 0 && X_RS1 (insn) == 1 - && (!X_I(insn) || X_SIMM13 (insn) == 0))) + if (!(X_OP (insn) == 3 && X_OP3 (insn) == 0x4 && X_RD (insn) == 0 + && X_RS1 (insn) == 1 && (!X_I (insn) || X_SIMM13 (insn) == 0))) return start_pc; /* We found a valid stack-check sequence, return the new PC. */ @@ -943,7 +926,7 @@ sparc_skip_stack_check (const CORE_ADDR start_pc) /* optional: clr [%g4 - some immediate] */ insn = sparc_fetch_instruction (pc); pc = pc + 4; - if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 && X_I(insn) + if (!(X_OP (insn) == 3 && X_OP3 (insn) == 0x4 && X_I (insn) && X_RS1 (insn) == 4 && X_RD (insn) == 0)) return pc - 4; else @@ -1020,9 +1003,10 @@ sparc_analyze_prologue (struct gdbarch *gdbarch, CORE_ADDR pc, /* Recognize stores into the corresponding stack slots. */ if (regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM && ((X_I (insn) - && X_SIMM13 (insn) == (X_OP3 (insn) == 0xe - ? (regnum - SPARC_L0_REGNUM) * 8 + BIAS - : (regnum - SPARC_L0_REGNUM) * 4)) + && X_SIMM13 (insn) + == (X_OP3 (insn) == 0xe + ? (regnum - SPARC_L0_REGNUM) * 8 + BIAS + : (regnum - SPARC_L0_REGNUM) * 4)) || (!X_I (insn) && regnum == SPARC_L0_REGNUM))) { cache->saved_regs_mask |= (1 << (regnum - SPARC_L0_REGNUM)); @@ -1062,10 +1046,8 @@ sparc_analyze_prologue (struct gdbarch *gdbarch, CORE_ADDR pc, } /* Check for an arithmetic operation on %sp. */ - if (X_OP (insn) == 2 - && (X_OP3 (insn) == 0 || X_OP3 (insn) == 0x4) - && X_RS1 (insn) == SPARC_SP_REGNUM - && X_RD (insn) == SPARC_SP_REGNUM) + if (X_OP (insn) == 2 && (X_OP3 (insn) == 0 || X_OP3 (insn) == 0x4) + && X_RS1 (insn) == SPARC_SP_REGNUM && X_RD (insn) == SPARC_SP_REGNUM) { if (X_I (insn)) { @@ -1078,10 +1060,8 @@ sparc_analyze_prologue (struct gdbarch *gdbarch, CORE_ADDR pc, insn = sparc_fetch_instruction (pc + offset); /* Check for an arithmetic operation that sets up the frame. */ - if (X_OP (insn) == 2 - && (X_OP3 (insn) == 0 || X_OP3 (insn) == 0x4) - && X_RS1 (insn) == SPARC_SP_REGNUM - && X_RD (insn) == SPARC_FP_REGNUM) + if (X_OP (insn) == 2 && (X_OP3 (insn) == 0 || X_OP3 (insn) == 0x4) + && X_RS1 (insn) == SPARC_SP_REGNUM && X_RD (insn) == SPARC_FP_REGNUM) { cache->frameless_p = 0; cache->frame_offset = 0; @@ -1094,15 +1074,12 @@ sparc_analyze_prologue (struct gdbarch *gdbarch, CORE_ADDR pc, } /* Check for a move (or) operation that copies the return register. */ - if (X_OP (insn) == 2 - && X_OP3 (insn) == 0x2 - && !X_I (insn) - && X_RS1 (insn) == SPARC_G0_REGNUM - && X_RS2 (insn) == SPARC_O7_REGNUM + if (X_OP (insn) == 2 && X_OP3 (insn) == 0x2 && !X_I (insn) + && X_RS1 (insn) == SPARC_G0_REGNUM && X_RS2 (insn) == SPARC_O7_REGNUM && X_RD (insn) == SPARC_I7_REGNUM) { - cache->copied_regs_mask |= 0x80; - offset += 4; + cache->copied_regs_mask |= 0x80; + offset += 4; } return pc + offset; @@ -1149,8 +1126,8 @@ sparc32_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc) /* Recognize instructions that store incoming arguments into the corresponding stack slots. */ - if (X_OP (insn) == 3 && (X_OP3 (insn) & 0x3c) == 0x04 - && X_I (insn) && X_RS1 (insn) == SPARC_FP_REGNUM) + if (X_OP (insn) == 3 && (X_OP3 (insn) & 0x3c) == 0x04 && X_I (insn) + && X_RS1 (insn) == SPARC_FP_REGNUM) { int regnum = X_RD (insn); @@ -1202,15 +1179,13 @@ sparc_frame_cache (frame_info_ptr this_frame, void **this_cache) /* This function is frameless, so %fp (%i6) holds the frame pointer for our calling frame. Use %sp (%o6) as this frame's base address. */ - cache->base = - get_frame_register_unsigned (this_frame, SPARC_SP_REGNUM); + cache->base = get_frame_register_unsigned (this_frame, SPARC_SP_REGNUM); } else { /* For normal frames, %fp (%i6) holds the frame pointer, the base address for the current stack frame. */ - cache->base = - get_frame_register_unsigned (this_frame, SPARC_FP_REGNUM); + cache->base = get_frame_register_unsigned (this_frame, SPARC_FP_REGNUM); } cache->base += cache->frame_offset; @@ -1263,8 +1238,8 @@ sparc32_frame_cache (frame_info_ptr this_frame, void **this_cache) an "unimp" instruction. If it is, then it is a struct-return function. */ CORE_ADDR pc; - int regnum = - (cache->copied_regs_mask & 0x80) ? SPARC_I7_REGNUM : SPARC_O7_REGNUM; + int regnum + = (cache->copied_regs_mask & 0x80) ? SPARC_I7_REGNUM : SPARC_O7_REGNUM; pc = get_frame_register_unsigned (this_frame, regnum) + 8; if (sparc_is_unimp_insn (pc)) @@ -1278,8 +1253,8 @@ static void sparc32_frame_this_id (frame_info_ptr this_frame, void **this_cache, struct frame_id *this_id) { - struct sparc_frame_cache *cache = - sparc32_frame_cache (this_frame, this_cache); + struct sparc_frame_cache *cache + = sparc32_frame_cache (this_frame, this_cache); /* This marks the outermost frame. */ if (cache->base == 0) @@ -1289,12 +1264,12 @@ sparc32_frame_this_id (frame_info_ptr this_frame, void **this_cache, } static struct value * -sparc32_frame_prev_register (frame_info_ptr this_frame, - void **this_cache, int regnum) +sparc32_frame_prev_register (frame_info_ptr this_frame, void **this_cache, + int regnum) { struct gdbarch *gdbarch = get_frame_arch (this_frame); - struct sparc_frame_cache *cache = - sparc32_frame_cache (this_frame, this_cache); + struct sparc_frame_cache *cache + = sparc32_frame_cache (this_frame, this_cache); if (regnum == SPARC32_PC_REGNUM || regnum == SPARC32_NPC_REGNUM) { @@ -1306,8 +1281,8 @@ sparc32_frame_prev_register (frame_info_ptr this_frame, if (cache->struct_return_p) pc += 4; - regnum = - (cache->copied_regs_mask & 0x80) ? SPARC_I7_REGNUM : SPARC_O7_REGNUM; + regnum + = (cache->copied_regs_mask & 0x80) ? SPARC_I7_REGNUM : SPARC_O7_REGNUM; pc += get_frame_register_unsigned (this_frame, regnum) + 8; return frame_unwind_got_constant (this_frame, regnum, pc); } @@ -1346,34 +1321,27 @@ sparc32_frame_prev_register (frame_info_ptr this_frame, return frame_unwind_got_register (this_frame, regnum, regnum); } -static const struct frame_unwind sparc32_frame_unwind = -{ - "sparc32 prologue", - NORMAL_FRAME, - default_frame_unwind_stop_reason, - sparc32_frame_this_id, - sparc32_frame_prev_register, - NULL, - default_frame_sniffer -}; - +static const struct frame_unwind sparc32_frame_unwind + = { "sparc32 prologue", + NORMAL_FRAME, + default_frame_unwind_stop_reason, + sparc32_frame_this_id, + sparc32_frame_prev_register, + NULL, + default_frame_sniffer }; static CORE_ADDR sparc32_frame_base_address (frame_info_ptr this_frame, void **this_cache) { - struct sparc_frame_cache *cache = - sparc32_frame_cache (this_frame, this_cache); + struct sparc_frame_cache *cache + = sparc32_frame_cache (this_frame, this_cache); return cache->base; } -static const struct frame_base sparc32_frame_base = -{ - &sparc32_frame_unwind, - sparc32_frame_base_address, - sparc32_frame_base_address, - sparc32_frame_base_address -}; +static const struct frame_base sparc32_frame_base + = { &sparc32_frame_unwind, sparc32_frame_base_address, + sparc32_frame_base_address, sparc32_frame_base_address }; static struct frame_id sparc_dummy_id (struct gdbarch *gdbarch, frame_info_ptr this_frame) @@ -1385,7 +1353,6 @@ sparc_dummy_id (struct gdbarch *gdbarch, frame_info_ptr this_frame) sp += BIAS; return frame_id_build (sp, get_frame_pc (this_frame)); } - /* Extract a function return value of TYPE from REGCACHE, and copy that into VALBUF. */ @@ -1618,19 +1585,18 @@ sparc_execute_dwarf_cfa_vendor_op (struct gdbarch *gdbarch, gdb_byte op, return true; } - /* The SPARC Architecture doesn't have hardware single-step support, and most operating systems don't implement it either, so we provide software single-step mechanism. */ static CORE_ADDR -sparc_analyze_control_transfer (struct regcache *regcache, - CORE_ADDR pc, CORE_ADDR *npc) +sparc_analyze_control_transfer (struct regcache *regcache, CORE_ADDR pc, + CORE_ADDR *npc) { unsigned long insn = sparc_fetch_instruction (pc); int conditional_p = X_COND (insn) & 0x7; int branch_p = 0, fused_p = 0; - long offset = 0; /* Must be signed for sign-extend. */ + long offset = 0; /* Must be signed for sign-extend. */ if (X_OP (insn) == 0 && X_OP2 (insn) == 3) { @@ -1765,7 +1731,6 @@ sparc_write_pc (struct regcache *regcache, CORE_ADDR pc) regcache_cooked_write_unsigned (regcache, tdep->pc_regnum, pc); regcache_cooked_write_unsigned (regcache, tdep->npc_regnum, pc + 4); } - /* Iterate over core file register note sections. */ @@ -1782,15 +1747,13 @@ sparc_iterate_over_regset_sections (struct gdbarch *gdbarch, cb (".reg2", tdep->sizeof_fpregset, tdep->sizeof_fpregset, tdep->fpregset, NULL, cb_data); } - static int validate_tdesc_registers (const struct target_desc *tdesc, struct tdesc_arch_data *tdesc_data, const char *feature_name, - const char * const register_names[], - unsigned int registers_num, - unsigned int reg_start) + const char *const register_names[], + unsigned int registers_num, unsigned int reg_start) { int valid_p = 1; const struct tdesc_feature *feature; @@ -1800,8 +1763,7 @@ validate_tdesc_registers (const struct target_desc *tdesc, return 0; for (unsigned int i = 0; i < registers_num; i++) - valid_p &= tdesc_numbered_register (feature, tdesc_data, - reg_start + i, + valid_p &= tdesc_numbered_register (feature, tdesc_data, reg_start + i, register_names[i]); return valid_p; @@ -1847,9 +1809,9 @@ sparc32_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) set_gdbarch_pseudo_register_write (gdbarch, sparc32_pseudo_register_write); /* Register numbers of various important registers. */ - set_gdbarch_sp_regnum (gdbarch, SPARC_SP_REGNUM); /* %sp */ + set_gdbarch_sp_regnum (gdbarch, SPARC_SP_REGNUM); /* %sp */ set_gdbarch_pc_regnum (gdbarch, SPARC32_PC_REGNUM); /* %pc */ - set_gdbarch_fp0_regnum (gdbarch, SPARC_F0_REGNUM); /* %f0 */ + set_gdbarch_fp0_regnum (gdbarch, SPARC_F0_REGNUM); /* %f0 */ /* Call dummy code. */ set_gdbarch_frame_align (gdbarch, sparc32_frame_align); @@ -1858,8 +1820,8 @@ sparc32_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) set_gdbarch_push_dummy_call (gdbarch, sparc32_push_dummy_call); set_gdbarch_return_value_as_value (gdbarch, sparc32_return_value); - set_gdbarch_stabs_argument_has_addr - (gdbarch, sparc32_stabs_argument_has_addr); + set_gdbarch_stabs_argument_has_addr (gdbarch, + sparc32_stabs_argument_has_addr); set_gdbarch_skip_prologue (gdbarch, sparc32_skip_prologue); @@ -1899,22 +1861,23 @@ sparc32_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) /* Validate that the descriptor provides the mandatory registers and allocate their numbers. */ - valid_p &= validate_tdesc_registers (tdesc, tdesc_data.get (), - "org.gnu.gdb.sparc.cpu", - sparc_core_register_names, - ARRAY_SIZE (sparc_core_register_names), - SPARC_G0_REGNUM); - valid_p &= validate_tdesc_registers (tdesc, tdesc_data.get (), - "org.gnu.gdb.sparc.fpu", - tdep->fpu_register_names, - tdep->fpu_registers_num, - SPARC_F0_REGNUM); + valid_p + &= validate_tdesc_registers (tdesc, tdesc_data.get (), + "org.gnu.gdb.sparc.cpu", + sparc_core_register_names, + ARRAY_SIZE (sparc_core_register_names), + SPARC_G0_REGNUM); + valid_p + &= validate_tdesc_registers (tdesc, tdesc_data.get (), + "org.gnu.gdb.sparc.fpu", + tdep->fpu_register_names, + tdep->fpu_registers_num, SPARC_F0_REGNUM); valid_p &= validate_tdesc_registers (tdesc, tdesc_data.get (), "org.gnu.gdb.sparc.cp0", tdep->cp0_register_names, tdep->cp0_registers_num, SPARC_F0_REGNUM - + tdep->fpu_registers_num); + + tdep->fpu_registers_num); if (!valid_p) return NULL; @@ -1925,14 +1888,14 @@ sparc32_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) /* If we have register sets, enable the generic core file support. */ if (tdep->gregset) - set_gdbarch_iterate_over_regset_sections - (gdbarch, sparc_iterate_over_regset_sections); + set_gdbarch_iterate_over_regset_sections ( + gdbarch, sparc_iterate_over_regset_sections); register_sparc_ravenscar_ops (gdbarch); return gdbarch; } - + /* Helper functions for dealing with register windows. */ void @@ -2012,8 +1975,8 @@ sparc_supply_rwindow (struct regcache *regcache, CORE_ADDR sp, int regnum) } void -sparc_collect_rwindow (const struct regcache *regcache, - CORE_ADDR sp, int regnum) +sparc_collect_rwindow (const struct regcache *regcache, CORE_ADDR sp, + int regnum) { struct gdbarch *gdbarch = regcache->arch (); enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); @@ -2087,8 +2050,8 @@ sparc_collect_rwindow (const struct regcache *regcache, void sparc32_supply_gregset (const struct sparc_gregmap *gregmap, - struct regcache *regcache, - int regnum, const void *gregs) + struct regcache *regcache, int regnum, + const void *gregs) { const gdb_byte *regs = (const gdb_byte *) gregs; gdb_byte zero[4] = { 0 }; @@ -2148,8 +2111,8 @@ sparc32_supply_gregset (const struct sparc_gregmap *gregmap, void sparc32_collect_gregset (const struct sparc_gregmap *gregmap, - const struct regcache *regcache, - int regnum, void *gregs) + const struct regcache *regcache, int regnum, + void *gregs) { gdb_byte *regs = (gdb_byte *) gregs; int i; @@ -2199,8 +2162,8 @@ sparc32_collect_gregset (const struct sparc_gregmap *gregmap, void sparc32_supply_fpregset (const struct sparc_fpregmap *fpregmap, - struct regcache *regcache, - int regnum, const void *fpregs) + struct regcache *regcache, int regnum, + const void *fpregs) { const gdb_byte *regs = (const gdb_byte *) fpregs; int i; @@ -2218,8 +2181,8 @@ sparc32_supply_fpregset (const struct sparc_fpregmap *fpregmap, void sparc32_collect_fpregset (const struct sparc_fpregmap *fpregmap, - const struct regcache *regcache, - int regnum, void *fpregs) + const struct regcache *regcache, int regnum, + void *fpregs) { gdb_byte *regs = (gdb_byte *) fpregs; int i; @@ -2232,39 +2195,35 @@ sparc32_collect_fpregset (const struct sparc_fpregmap *fpregmap, } if (regnum == SPARC32_FSR_REGNUM || regnum == -1) - regcache->raw_collect (SPARC32_FSR_REGNUM, - regs + fpregmap->r_fsr_offset); + regcache->raw_collect (SPARC32_FSR_REGNUM, regs + fpregmap->r_fsr_offset); } - /* SunOS 4. */ /* From <machine/reg.h>. */ -const struct sparc_gregmap sparc32_sunos4_gregmap = -{ - 0 * 4, /* %psr */ - 1 * 4, /* %pc */ - 2 * 4, /* %npc */ - 3 * 4, /* %y */ - -1, /* %wim */ - -1, /* %tbr */ - 4 * 4, /* %g1 */ - -1 /* %l0 */ +const struct sparc_gregmap sparc32_sunos4_gregmap = { + 0 * 4, /* %psr */ + 1 * 4, /* %pc */ + 2 * 4, /* %npc */ + 3 * 4, /* %y */ + -1, /* %wim */ + -1, /* %tbr */ + 4 * 4, /* %g1 */ + -1 /* %l0 */ }; -const struct sparc_fpregmap sparc32_sunos4_fpregmap = -{ - 0 * 4, /* %f0 */ - 33 * 4, /* %fsr */ +const struct sparc_fpregmap sparc32_sunos4_fpregmap = { + 0 * 4, /* %f0 */ + 33 * 4, /* %fsr */ }; -const struct sparc_fpregmap sparc32_bsd_fpregmap = -{ - 0 * 4, /* %f0 */ - 32 * 4, /* %fsr */ +const struct sparc_fpregmap sparc32_bsd_fpregmap = { + 0 * 4, /* %f0 */ + 32 * 4, /* %fsr */ }; void _initialize_sparc_tdep (); + void _initialize_sparc_tdep () { |