diff options
Diffstat (limited to 'gdb/mips-tdep.c')
| -rw-r--r-- | gdb/mips-tdep.c | 2322 |
1 files changed, 1090 insertions, 1232 deletions
diff --git a/gdb/mips-tdep.c b/gdb/mips-tdep.c index 6088587..c6b2c48 100644 --- a/gdb/mips-tdep.c +++ b/gdb/mips-tdep.c @@ -96,16 +96,8 @@ enum static const char *mips_abi_string; -static const char *const mips_abi_strings[] = { - "auto", - "n32", - "o32", - "n64", - "o64", - "eabi32", - "eabi64", - NULL -}; +static const char *const mips_abi_strings[] + = { "auto", "n32", "o32", "n64", "o64", "eabi32", "eabi64", NULL }; /* Enum describing the different kinds of breakpoints. */ @@ -129,12 +121,8 @@ enum mips_breakpoint_kind compressed ISA encoding used. */ static const char mips_compression_mips16[] = "mips16"; static const char mips_compression_micromips[] = "micromips"; -static const char *const mips_compression_strings[] = -{ - mips_compression_mips16, - mips_compression_micromips, - NULL -}; +static const char *const mips_compression_strings[] + = { mips_compression_mips16, mips_compression_micromips, NULL }; static const char *mips_compression_string = mips_compression_mips16; @@ -146,30 +134,53 @@ struct register_alias }; /* Aliases for o32 and most other ABIs. */ -const struct register_alias mips_o32_aliases[] = { - { "ta0", 12 }, - { "ta1", 13 }, - { "ta2", 14 }, - { "ta3", 15 } -}; +const struct register_alias mips_o32_aliases[] + = { { "ta0", 12 }, { "ta1", 13 }, { "ta2", 14 }, { "ta3", 15 } }; /* Aliases for n32 and n64. */ -const struct register_alias mips_n32_n64_aliases[] = { - { "ta0", 8 }, - { "ta1", 9 }, - { "ta2", 10 }, - { "ta3", 11 } -}; +const struct register_alias mips_n32_n64_aliases[] + = { { "ta0", 8 }, { "ta1", 9 }, { "ta2", 10 }, { "ta3", 11 } }; /* Aliases for ABI-independent registers. */ const struct register_alias mips_register_aliases[] = { - /* The architecture manuals specify these ABI-independent names for +/* The architecture manuals specify these ABI-independent names for the GPRs. */ -#define R(n) { "r" #n, n } - R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7), - R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15), - R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23), - R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31), +#define R(n) \ + { \ + "r" #n, n \ + } + R (0), + R (1), + R (2), + R (3), + R (4), + R (5), + R (6), + R (7), + R (8), + R (9), + R (10), + R (11), + R (12), + R (13), + R (14), + R (15), + R (16), + R (17), + R (18), + R (19), + R (20), + R (21), + R (22), + R (23), + R (24), + R (25), + R (26), + R (27), + R (28), + R (29), + R (30), + R (31), #undef R /* k0 and k1 are sometimes called these instead (for "kernel @@ -188,11 +199,14 @@ const struct register_alias mips_register_aliases[] = { }; const struct register_alias mips_numeric_register_aliases[] = { -#define R(n) { #n, n } - R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7), - R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15), - R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23), - R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31), +#define R(n) \ + { \ +#n, n \ + } + R (0), R (1), R (2), R (3), R (4), R (5), R (6), R (7), + R (8), R (9), R (10), R (11), R (12), R (13), R (14), R (15), + R (16), R (17), R (18), R (19), R (20), R (21), R (22), R (23), + R (24), R (25), R (26), R (27), R (28), R (29), R (30), R (31), #undef R }; @@ -253,7 +267,7 @@ static bool mips_eabi (gdbarch *arch) { mips_gdbarch_tdep *tdep = gdbarch_tdep<mips_gdbarch_tdep> (arch); - return (tdep->mips_abi == MIPS_ABI_EABI32 \ + return (tdep->mips_abi == MIPS_ABI_EABI32 || tdep->mips_abi == MIPS_ABI_EABI64); } @@ -321,7 +335,7 @@ mips_abi_regsize (struct gdbarch *gdbarch) case MIPS_ABI_UNKNOWN: case MIPS_ABI_LAST: default: - internal_error (_("bad switch")); + internal_error (_ ("bad switch")); } } @@ -353,7 +367,7 @@ is_micromips_isa (struct gdbarch *gdbarch) static int is_compact_addr (CORE_ADDR addr) { - return ((addr) & 1); + return ((addr) &1); } /* Return one iff ADDR denotes standard ISA code. */ @@ -421,7 +435,7 @@ mips_unmake_compact_addr (CORE_ADDR addr) in a minimal symbol. */ static void -mips_elf_make_msymbol_special (asymbol * sym, struct minimal_symbol *msym) +mips_elf_make_msymbol_special (asymbol *sym, struct minimal_symbol *msym) { elf_symbol_type *elfsym = (elf_symbol_type *) sym; unsigned char st_other; @@ -506,9 +520,8 @@ mips_make_symbol_special (struct symbol *sym, struct objfile *objfile) static void mips_xfer_register (struct gdbarch *gdbarch, struct regcache *regcache, - int reg_num, int length, - enum bfd_endian endian, gdb_byte *in, - const gdb_byte *out, int buf_offset) + int reg_num, int length, enum bfd_endian endian, + gdb_byte *in, const gdb_byte *out, int buf_offset) { int reg_offset = 0; @@ -523,16 +536,16 @@ mips_xfer_register (struct gdbarch *gdbarch, struct regcache *regcache, case BFD_ENDIAN_LITTLE: reg_offset = 0; break; - case BFD_ENDIAN_UNKNOWN: /* Indicates no alignment. */ + case BFD_ENDIAN_UNKNOWN: /* Indicates no alignment. */ reg_offset = 0; break; default: - internal_error (_("bad switch")); + internal_error (_ ("bad switch")); } if (mips_debug) gdb_printf (gdb_stderr, - "xfer $%d, reg offset %d, buf offset %d, length %d, ", - reg_num, reg_offset, buf_offset, length); + "xfer $%d, reg offset %d, buf offset %d, length %d, ", reg_num, + reg_offset, buf_offset, length); if (mips_debug && out != NULL) { int i; @@ -543,7 +556,8 @@ mips_xfer_register (struct gdbarch *gdbarch, struct regcache *regcache, if (in != NULL) regcache->cooked_read_part (reg_num, reg_offset, length, in + buf_offset); if (out != NULL) - regcache->cooked_write_part (reg_num, reg_offset, length, out + buf_offset); + regcache->cooked_write_part (reg_num, reg_offset, length, + out + buf_offset); if (mips_debug && in != NULL) { int i; @@ -581,7 +595,7 @@ mips2_fp_compat (frame_info_ptr frame) return 0; } -#define VM_MIN_ADDRESS (CORE_ADDR)0x400000 +#define VM_MIN_ADDRESS (CORE_ADDR) 0x400000 static CORE_ADDR heuristic_proc_start (struct gdbarch *, CORE_ADDR); @@ -595,42 +609,36 @@ static struct cmd_list_element *showmipscmdlist = NULL; are listed in the following tables. */ enum -{ NUM_MIPS_PROCESSOR_REGS = (90 - 32) }; +{ + NUM_MIPS_PROCESSOR_REGS = (90 - 32) +}; /* Generic MIPS. */ -static const char * const mips_generic_reg_names[NUM_MIPS_PROCESSOR_REGS] = { - "sr", "lo", "hi", "bad", "cause", "pc", - "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", - "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", - "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", - "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", - "fsr", "fir", +static const char *const mips_generic_reg_names[NUM_MIPS_PROCESSOR_REGS] = { + "sr", "lo", "hi", "bad", "cause", "pc", "f0", "f1", "f2", "f3", + "f4", "f5", "f6", "f7", "f8", "f9", "f10", "f11", "f12", "f13", + "f14", "f15", "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", + "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", "fsr", "fir", }; /* Names of tx39 registers. */ -static const char * const mips_tx39_reg_names[NUM_MIPS_PROCESSOR_REGS] = { - "sr", "lo", "hi", "bad", "cause", "pc", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "", "", - "", "", "", "", "", "", "", "", - "", "", "config", "cache", "debug", "depc", "epc", +static const char *const mips_tx39_reg_names[NUM_MIPS_PROCESSOR_REGS] = { + "sr", "lo", "hi", "bad", "cause", "pc", "", "", "", "", + "", "", "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", "", "", + "", "", "config", "cache", "debug", "depc", "epc", }; /* Names of registers with Linux kernels. */ -static const char * const mips_linux_reg_names[NUM_MIPS_PROCESSOR_REGS] = { - "sr", "lo", "hi", "bad", "cause", "pc", - "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", - "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", - "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", - "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", - "fsr", "fir" -}; - +static const char *const mips_linux_reg_names[NUM_MIPS_PROCESSOR_REGS] + = { "sr", "lo", "hi", "bad", "cause", "pc", "f0", "f1", "f2", "f3", + "f4", "f5", "f6", "f7", "f8", "f9", "f10", "f11", "f12", "f13", + "f14", "f15", "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", + "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", "fsr", "fir" }; /* Return the name of the register corresponding to REGNO. */ static const char * @@ -639,19 +647,16 @@ mips_register_name (struct gdbarch *gdbarch, int regno) mips_gdbarch_tdep *tdep = gdbarch_tdep<mips_gdbarch_tdep> (gdbarch); /* GPR names for all ABIs other than n32/n64. */ static const char *mips_gpr_names[] = { - "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", - "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", - "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", - "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", + "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", "t0", "t1", "t2", + "t3", "t4", "t5", "t6", "t7", "s0", "s1", "s2", "s3", "s4", "s5", + "s6", "s7", "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", }; /* GPR names for n32 and n64 ABIs. */ - static const char *mips_n32_n64_gpr_names[] = { - "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", - "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3", - "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", - "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" - }; + static const char *mips_n32_n64_gpr_names[] + = { "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", "a4", "a5", "a6", + "a7", "t0", "t1", "t2", "t3", "s0", "s1", "s2", "s3", "s4", "s5", + "s6", "s7", "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" }; enum mips_abi abi = mips_abi (gdbarch); @@ -690,7 +695,7 @@ mips_register_name (struct gdbarch *gdbarch, int regno) return ""; } else - internal_error (_("mips_register_name: bad register number %d"), rawnum); + internal_error (_ ("mips_register_name: bad register number %d"), rawnum); } /* Return the groups that a MIPS register can be categorised into. */ @@ -764,16 +769,17 @@ mips_tdesc_register_reggroup_p (struct gdbarch *gdbarch, int regnum, registers. Take care of alignment and size problems. */ static enum register_status -mips_pseudo_register_read (struct gdbarch *gdbarch, readable_regcache *regcache, - int cookednum, gdb_byte *buf) +mips_pseudo_register_read (struct gdbarch *gdbarch, + readable_regcache *regcache, int cookednum, + gdb_byte *buf) { int rawnum = cookednum % gdbarch_num_regs (gdbarch); gdb_assert (cookednum >= gdbarch_num_regs (gdbarch) && cookednum < 2 * gdbarch_num_regs (gdbarch)); if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum)) return regcache->raw_read (rawnum, buf); - else if (register_size (gdbarch, rawnum) > - register_size (gdbarch, cookednum)) + else if (register_size (gdbarch, rawnum) + > register_size (gdbarch, cookednum)) { mips_gdbarch_tdep *tdep = gdbarch_tdep<mips_gdbarch_tdep> (gdbarch); @@ -792,21 +798,20 @@ mips_pseudo_register_read (struct gdbarch *gdbarch, readable_regcache *regcache, } } else - internal_error (_("bad register size")); + internal_error (_ ("bad register size")); } static void -mips_pseudo_register_write (struct gdbarch *gdbarch, - struct regcache *regcache, int cookednum, - const gdb_byte *buf) +mips_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, + int cookednum, const gdb_byte *buf) { int rawnum = cookednum % gdbarch_num_regs (gdbarch); gdb_assert (cookednum >= gdbarch_num_regs (gdbarch) && cookednum < 2 * gdbarch_num_regs (gdbarch)); if (register_size (gdbarch, rawnum) == register_size (gdbarch, cookednum)) regcache->raw_write (rawnum, buf); - else if (register_size (gdbarch, rawnum) > - register_size (gdbarch, cookednum)) + else if (register_size (gdbarch, rawnum) + > register_size (gdbarch, cookednum)) { mips_gdbarch_tdep *tdep = gdbarch_tdep<mips_gdbarch_tdep> (gdbarch); @@ -823,7 +828,7 @@ mips_pseudo_register_write (struct gdbarch *gdbarch, } } else - internal_error (_("bad register size")); + internal_error (_ ("bad register size")); } static int @@ -852,8 +857,7 @@ mips_ax_pseudo_register_push_stack (struct gdbarch *gdbarch, if (register_size (gdbarch, rawnum) > register_size (gdbarch, reg)) { - mips_gdbarch_tdep *tdep - = gdbarch_tdep<mips_gdbarch_tdep> (gdbarch); + mips_gdbarch_tdep *tdep = gdbarch_tdep<mips_gdbarch_tdep> (gdbarch); if (!tdep->mips64_transfers_32bit_regs_p || gdbarch_byte_order (gdbarch) != BFD_ENDIAN_BIG) @@ -866,7 +870,7 @@ mips_ax_pseudo_register_push_stack (struct gdbarch *gdbarch, } } else - internal_error (_("bad register size")); + internal_error (_ ("bad register size")); return 0; } @@ -897,7 +901,7 @@ set_mips64_transfers_32bit_regs (const char *args, int from_tty, if (!gdbarch_update_p (info)) { mips64_transfers_32bit_regs_p = 0; - error (_("32-bit compatibility mode not supported")); + error (_ ("32-bit compatibility mode not supported")); } } @@ -926,23 +930,21 @@ mips_convert_register_gpreg_case_p (struct gdbarch *gdbarch, int regnum, { int num_regs = gdbarch_num_regs (gdbarch); - return (register_size (gdbarch, regnum) == 8 - && regnum % num_regs > 0 && regnum % num_regs < 32 - && type->length () < 8); + return (register_size (gdbarch, regnum) == 8 && regnum % num_regs > 0 + && regnum % num_regs < 32 && type->length () < 8); } static int -mips_convert_register_p (struct gdbarch *gdbarch, - int regnum, struct type *type) +mips_convert_register_p (struct gdbarch *gdbarch, int regnum, + struct type *type) { return (mips_convert_register_float_case_p (gdbarch, regnum, type) || mips_convert_register_gpreg_case_p (gdbarch, regnum, type)); } static int -mips_register_to_value (frame_info_ptr frame, int regnum, - struct type *type, gdb_byte *to, - int *optimizedp, int *unavailablep) +mips_register_to_value (frame_info_ptr frame, int regnum, struct type *type, + gdb_byte *to, int *optimizedp, int *unavailablep) { struct gdbarch *gdbarch = get_frame_arch (frame); @@ -951,11 +953,11 @@ mips_register_to_value (frame_info_ptr frame, int regnum, get_frame_register (frame, regnum + 0, to + 4); get_frame_register (frame, regnum + 1, to + 0); - if (!get_frame_register_bytes (frame, regnum + 0, 0, {to + 4, 4}, + if (!get_frame_register_bytes (frame, regnum + 0, 0, { to + 4, 4 }, optimizedp, unavailablep)) return 0; - if (!get_frame_register_bytes (frame, regnum + 1, 0, {to + 0, 4}, + if (!get_frame_register_bytes (frame, regnum + 1, 0, { to + 0, 4 }, optimizedp, unavailablep)) return 0; *optimizedp = *unavailablep = 0; @@ -967,7 +969,7 @@ mips_register_to_value (frame_info_ptr frame, int regnum, CORE_ADDR offset; offset = gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG ? 8 - len : 0; - if (!get_frame_register_bytes (frame, regnum, offset, {to, len}, + if (!get_frame_register_bytes (frame, regnum, offset, { to, len }, optimizedp, unavailablep)) return 0; @@ -976,13 +978,13 @@ mips_register_to_value (frame_info_ptr frame, int regnum, } else { - internal_error (_("mips_register_to_value: unrecognized case")); + internal_error (_ ("mips_register_to_value: unrecognized case")); } } static void -mips_value_to_register (frame_info_ptr frame, int regnum, - struct type *type, const gdb_byte *from) +mips_value_to_register (frame_info_ptr frame, int regnum, struct type *type, + const gdb_byte *from) { struct gdbarch *gdbarch = get_frame_arch (frame); @@ -995,7 +997,7 @@ mips_value_to_register (frame_info_ptr frame, int regnum, { gdb_byte fill[8]; size_t len = type->length (); - + /* Sign extend values, irrespective of type, that are stored to a 64-bit general purpose register. (32-bit unsigned values are stored as signed quantities within a 64-bit register. @@ -1008,22 +1010,22 @@ mips_value_to_register (frame_info_ptr frame, int regnum, store_signed_integer (fill, 8, BFD_ENDIAN_BIG, -1); else store_signed_integer (fill, 8, BFD_ENDIAN_BIG, 0); - put_frame_register_bytes (frame, regnum, 0, {fill, 8 - len}); - put_frame_register_bytes (frame, regnum, 8 - len, {from, len}); + put_frame_register_bytes (frame, regnum, 0, { fill, 8 - len }); + put_frame_register_bytes (frame, regnum, 8 - len, { from, len }); } else { - if (from[len-1] & 0x80) + if (from[len - 1] & 0x80) store_signed_integer (fill, 8, BFD_ENDIAN_LITTLE, -1); else store_signed_integer (fill, 8, BFD_ENDIAN_LITTLE, 0); - put_frame_register_bytes (frame, regnum, 0, {from, len}); - put_frame_register_bytes (frame, regnum, len, {fill, 8 - len}); + put_frame_register_bytes (frame, regnum, 0, { from, len }); + put_frame_register_bytes (frame, regnum, len, { fill, 8 - len }); } } else { - internal_error (_("mips_value_to_register: unrecognized case")); + internal_error (_ ("mips_value_to_register: unrecognized case")); } } @@ -1117,7 +1119,7 @@ mips_pseudo_register_type (struct gdbarch *gdbarch, int regnum) /* Use pointer types for registers if we can. For n32 we can not, since we do not have a 64-bit pointer type. */ if (mips_abi_regsize (gdbarch) - == builtin_type (gdbarch)->builtin_data_ptr->length()) + == builtin_type (gdbarch)->builtin_data_ptr->length ()) { if (rawnum == MIPS_SP_REGNUM || rawnum == mips_regnum (gdbarch)->badvaddr) @@ -1145,8 +1147,7 @@ mips_pseudo_register_type (struct gdbarch *gdbarch, int regnum) so allow the target to provide 64 bits without interfering with the displayed type. */ if (gdbarch_osabi (gdbarch) != GDB_OSABI_LINUX - && rawnum >= MIPS_FIRST_EMBED_REGNUM - && rawnum <= MIPS_LAST_EMBED_REGNUM) + && rawnum >= MIPS_FIRST_EMBED_REGNUM && rawnum <= MIPS_LAST_EMBED_REGNUM) return builtin_type (gdbarch)->builtin_int32; /* For all other registers, pass through the hardware type. */ @@ -1169,7 +1170,7 @@ mips_mask_address_p (mips_gdbarch_tdep *tdep) case AUTO_BOOLEAN_AUTO: return tdep->default_mask_address_p; default: - internal_error (_("mips_mask_address_p: bad switch")); + internal_error (_ ("mips_mask_address_p: bad switch")); return -1; } } @@ -1182,21 +1183,22 @@ show_mask_address (struct ui_file *file, int from_tty, if (mask_address_var == AUTO_BOOLEAN_AUTO) { if (gdbarch_bfd_arch_info (target_gdbarch ())->arch != bfd_arch_mips) - additional_text = _(" (current architecture is not MIPS)"); + additional_text = _ (" (current architecture is not MIPS)"); else { mips_gdbarch_tdep *tdep = gdbarch_tdep<mips_gdbarch_tdep> (target_gdbarch ()); if (mips_mask_address_p (tdep)) - additional_text = _(" (currently \"on\")"); + additional_text = _ (" (currently \"on\")"); else - additional_text = _(" (currently \"off\")"); + additional_text = _ (" (currently \"off\")"); } } - gdb_printf (file, _("Zeroing of upper 32 bits of 64-bit addresses is \"%s\"%s.\n"), - value, additional_text); + gdb_printf ( + file, _ ("Zeroing of upper 32 bits of 64-bit addresses is \"%s\"%s.\n"), + value, additional_text); } /* Tell if the program counter value in MEMADDR is in a standard ISA @@ -1385,7 +1387,7 @@ mips_in_frame_stub (CORE_ADDR pc) if (startswith (name, mips_str_fn_stub)) return 1; - return 0; /* Not a stub. */ + return 0; /* Not a stub. */ } /* MIPS believes that the PC has a sign extended value. Perhaps the @@ -1414,11 +1416,12 @@ mips_unwind_pc (struct gdbarch *gdbarch, frame_info_ptr next_frame) and thus the caller's address is in $s2. */ if (frame_relative_level (next_frame) >= 0 && mips_in_frame_stub (pc)) { - pc = frame_unwind_register_signed - (next_frame, gdbarch_num_regs (gdbarch) + MIPS_RA_REGNUM); + pc = frame_unwind_register_signed (next_frame, gdbarch_num_regs (gdbarch) + + MIPS_RA_REGNUM); if (mips_in_frame_stub (pc)) - pc = frame_unwind_register_signed - (next_frame, gdbarch_num_regs (gdbarch) + MIPS_S2_REGNUM); + pc = frame_unwind_register_signed (next_frame, + gdbarch_num_regs (gdbarch) + + MIPS_S2_REGNUM); } return pc; } @@ -1426,8 +1429,8 @@ mips_unwind_pc (struct gdbarch *gdbarch, frame_info_ptr next_frame) static CORE_ADDR mips_unwind_sp (struct gdbarch *gdbarch, frame_info_ptr next_frame) { - return frame_unwind_register_signed - (next_frame, gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM); + return frame_unwind_register_signed (next_frame, gdbarch_num_regs (gdbarch) + + MIPS_SP_REGNUM); } /* Assuming THIS_FRAME is a dummy, return the frame ID of that @@ -1438,11 +1441,10 @@ mips_unwind_sp (struct gdbarch *gdbarch, frame_info_ptr next_frame) static struct frame_id mips_dummy_id (struct gdbarch *gdbarch, frame_info_ptr this_frame) { - return frame_id_build - (get_frame_register_signed (this_frame, - gdbarch_num_regs (gdbarch) - + MIPS_SP_REGNUM), - get_frame_pc (this_frame)); + return frame_id_build (get_frame_register_signed (this_frame, + gdbarch_num_regs (gdbarch) + + MIPS_SP_REGNUM), + get_frame_pc (this_frame)); } /* Implement the "write_pc" gdbarch method. */ @@ -1459,8 +1461,8 @@ mips_write_pc (struct regcache *regcache, CORE_ADDR pc) MIPS16/microMIPS as appropriate. */ static ULONGEST -mips_fetch_instruction (struct gdbarch *gdbarch, - enum mips_isa isa, CORE_ADDR addr, int *errp) +mips_fetch_instruction (struct gdbarch *gdbarch, enum mips_isa isa, + CORE_ADDR addr, int *errp) { enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); gdb_byte buf[MIPS_INSN32_SIZE]; @@ -1478,7 +1480,7 @@ mips_fetch_instruction (struct gdbarch *gdbarch, instlen = MIPS_INSN32_SIZE; break; default: - internal_error (_("invalid ISA")); + internal_error (_ ("invalid ISA")); break; } err = target_read_memory (addr, buf, instlen); @@ -1515,11 +1517,11 @@ mips_fetch_instruction (struct gdbarch *gdbarch, /* 16-bit/32-bit-high-part instruction formats, B and S refer to the lowest bit and the size respectively of the field extracted. */ -#define b0s4_imm(x) ((x) & 0xf) -#define b0s5_imm(x) ((x) & 0x1f) -#define b0s5_reg(x) ((x) & 0x1f) -#define b0s7_imm(x) ((x) & 0x7f) -#define b0s10_imm(x) ((x) & 0x3ff) +#define b0s4_imm(x) ((x) &0xf) +#define b0s5_imm(x) ((x) &0x1f) +#define b0s5_reg(x) ((x) &0x1f) +#define b0s7_imm(x) ((x) &0x7f) +#define b0s10_imm(x) ((x) &0x3ff) #define b1s4_imm(x) (((x) >> 1) & 0xf) #define b1s9_imm(x) (((x) >> 1) & 0x1ff) #define b2s3_cc(x) (((x) >> 2) & 0x7) @@ -1531,11 +1533,11 @@ mips_fetch_instruction (struct gdbarch *gdbarch, /* 32-bit instruction formats, B and S refer to the lowest bit and the size respectively of the field extracted. */ -#define b0s6_op(x) ((x) & 0x3f) -#define b0s11_op(x) ((x) & 0x7ff) -#define b0s12_imm(x) ((x) & 0xfff) -#define b0s16_imm(x) ((x) & 0xffff) -#define b0s26_imm(x) ((x) & 0x3ffffff) +#define b0s6_op(x) ((x) &0x3f) +#define b0s11_op(x) ((x) &0x7ff) +#define b0s12_imm(x) ((x) &0xfff) +#define b0s16_imm(x) ((x) &0xffff) +#define b0s26_imm(x) ((x) &0x3ffffff) #define b6s10_ext(x) (((x) >> 6) & 0x3ff) #define b11s5_reg(x) (((x) >> 11) & 0x1f) #define b12s4_op(x) (((x) >> 12) & 0xf) @@ -1560,9 +1562,9 @@ mips_insn_size (enum mips_isa isa, ULONGEST insn) else return MIPS_INSN16_SIZE; case ISA_MIPS: - return MIPS_INSN32_SIZE; + return MIPS_INSN32_SIZE; } - internal_error (_("invalid ISA")); + internal_error (_ ("invalid ISA")); } static LONGEST @@ -1609,8 +1611,8 @@ is_octeon (struct gdbarch *gdbarch) const struct bfd_arch_info *info = gdbarch_bfd_arch_info (gdbarch); return (info->mach == bfd_mach_mips_octeon - || info->mach == bfd_mach_mips_octeonp - || info->mach == bfd_mach_mips_octeon2); + || info->mach == bfd_mach_mips_octeonp + || info->mach == bfd_mach_mips_octeon2); } /* Return true if the OP represents the Octeon's BBIT instruction. */ @@ -1629,7 +1631,6 @@ is_octeon_bbit_op (int op, struct gdbarch *gdbarch) return 0; } - /* Determine where to set a single step breakpoint while considering branch prediction. */ @@ -1641,7 +1642,7 @@ mips32_next_pc (struct regcache *regcache, CORE_ADDR pc) int op; inst = mips_fetch_instruction (gdbarch, ISA_MIPS, pc, NULL); op = itype_op (inst); - if ((inst & 0xe0000000) != 0) /* Not a special, jump or branch + if ((inst & 0xe0000000) != 0) /* Not a special, jump or branch instruction. */ { if (op >> 2 == 5) @@ -1649,13 +1650,13 @@ mips32_next_pc (struct regcache *regcache, CORE_ADDR pc) { switch (op & 0x03) { - case 0: /* BEQL */ + case 0: /* BEQL */ goto equal_branch; - case 1: /* BNEL */ + case 1: /* BNEL */ goto neq_branch; - case 2: /* BLEZL */ + case 2: /* BLEZL */ goto less_branch; - case 3: /* BGTZL */ + case 3: /* BGTZL */ goto greater_branch; default: pc += 4; @@ -1664,12 +1665,10 @@ mips32_next_pc (struct regcache *regcache, CORE_ADDR pc) else if (op == 17 && itype_rs (inst) == 8) /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */ pc = mips32_bc1_pc (gdbarch, regcache, inst, pc + 4, 1); - else if (op == 17 && itype_rs (inst) == 9 - && (itype_rt (inst) & 2) == 0) + else if (op == 17 && itype_rs (inst) == 9 && (itype_rt (inst) & 2) == 0) /* BC1ANY2F, BC1ANY2T: 010001 01001 xxx0x */ pc = mips32_bc1_pc (gdbarch, regcache, inst, pc + 4, 2); - else if (op == 17 && itype_rs (inst) == 10 - && (itype_rt (inst) & 2) == 0) + else if (op == 17 && itype_rs (inst) == 10 && (itype_rt (inst) & 2) == 0) /* BC1ANY4F, BC1ANY4T: 010001 01010 xxx0x */ pc = mips32_bc1_pc (gdbarch, regcache, inst, pc + 4, 4); else if (op == 29) @@ -1693,33 +1692,33 @@ mips32_next_pc (struct regcache *regcache, CORE_ADDR pc) if (op == 54 || op == 62) bit += 32; - if (((regcache_raw_get_signed (regcache, - itype_rs (inst)) >> bit) & 1) + if (((regcache_raw_get_signed (regcache, itype_rs (inst)) >> bit) + & 1) == branch_if) pc += mips32_relative_offset (inst) + 4; else - pc += 8; /* After the delay slot. */ + pc += 8; /* After the delay slot. */ } else - pc += 4; /* Not a branch, next instruction is easy. */ + pc += 4; /* Not a branch, next instruction is easy. */ } else - { /* This gets way messy. */ + { /* This gets way messy. */ /* Further subdivide into SPECIAL, REGIMM and other. */ - switch (op & 0x07) /* Extract bits 28,27,26. */ + switch (op & 0x07) /* Extract bits 28,27,26. */ { - case 0: /* SPECIAL */ + case 0: /* SPECIAL */ op = rtype_funct (inst); switch (op) { - case 8: /* JR */ - case 9: /* JALR */ + case 8: /* JR */ + case 9: /* JALR */ /* Set PC to that address. */ pc = regcache_raw_get_signed (regcache, rtype_rs (inst)); break; - case 12: /* SYSCALL */ + case 12: /* SYSCALL */ { mips_gdbarch_tdep *tdep = gdbarch_tdep<mips_gdbarch_tdep> (gdbarch); @@ -1734,33 +1733,33 @@ mips32_next_pc (struct regcache *regcache, CORE_ADDR pc) pc += 4; } - break; /* end SPECIAL */ - case 1: /* REGIMM */ + break; /* end SPECIAL */ + case 1: /* REGIMM */ { - op = itype_rt (inst); /* branch condition */ + op = itype_rt (inst); /* branch condition */ switch (op) { - case 0: /* BLTZ */ - case 2: /* BLTZL */ - case 16: /* BLTZAL */ - case 18: /* BLTZALL */ + case 0: /* BLTZ */ + case 2: /* BLTZL */ + case 16: /* BLTZAL */ + case 18: /* BLTZALL */ less_branch: if (regcache_raw_get_signed (regcache, itype_rs (inst)) < 0) pc += mips32_relative_offset (inst) + 4; else - pc += 8; /* after the delay slot */ + pc += 8; /* after the delay slot */ break; - case 1: /* BGEZ */ - case 3: /* BGEZL */ - case 17: /* BGEZAL */ - case 19: /* BGEZALL */ + case 1: /* BGEZ */ + case 3: /* BGEZL */ + case 17: /* BGEZAL */ + case 19: /* BGEZALL */ if (regcache_raw_get_signed (regcache, itype_rs (inst)) >= 0) pc += mips32_relative_offset (inst) + 4; else - pc += 8; /* after the delay slot */ + pc += 8; /* after the delay slot */ break; - case 0x1c: /* BPOSGE32 */ - case 0x1e: /* BPOSGE64 */ + case 0x1c: /* BPOSGE32 */ + case 0x1e: /* BPOSGE64 */ pc += 4; if (itype_rs (inst) == 0) { @@ -1771,8 +1770,8 @@ mips32_next_pc (struct regcache *regcache, CORE_ADDR pc) /* No way to handle; it'll most likely trap anyway. */ break; - if ((regcache_raw_get_unsigned (regcache, - dspctl) & 0x7f) >= pos) + if ((regcache_raw_get_unsigned (regcache, dspctl) & 0x7f) + >= pos) pc += mips32_relative_offset (inst); else pc += 4; @@ -1783,9 +1782,9 @@ mips32_next_pc (struct regcache *regcache, CORE_ADDR pc) pc += 4; } } - break; /* end REGIMM */ - case 2: /* J */ - case 3: /* JAL */ + break; /* end REGIMM */ + case 2: /* J */ + case 3: /* JAL */ { unsigned long reg; reg = jtype_target (inst) << 2; @@ -1793,23 +1792,23 @@ mips32_next_pc (struct regcache *regcache, CORE_ADDR pc) pc = reg + ((pc + 4) & ~(CORE_ADDR) 0x0fffffff); } break; - case 4: /* BEQ, BEQL */ + case 4: /* BEQ, BEQL */ equal_branch: - if (regcache_raw_get_signed (regcache, itype_rs (inst)) == - regcache_raw_get_signed (regcache, itype_rt (inst))) + if (regcache_raw_get_signed (regcache, itype_rs (inst)) + == regcache_raw_get_signed (regcache, itype_rt (inst))) pc += mips32_relative_offset (inst) + 4; else pc += 8; break; - case 5: /* BNE, BNEL */ + case 5: /* BNE, BNEL */ neq_branch: - if (regcache_raw_get_signed (regcache, itype_rs (inst)) != - regcache_raw_get_signed (regcache, itype_rt (inst))) + if (regcache_raw_get_signed (regcache, itype_rs (inst)) + != regcache_raw_get_signed (regcache, itype_rt (inst))) pc += mips32_relative_offset (inst) + 4; else pc += 8; break; - case 6: /* BLEZ, BLEZL */ + case 6: /* BLEZ, BLEZL */ if (regcache_raw_get_signed (regcache, itype_rs (inst)) <= 0) pc += mips32_relative_offset (inst) + 4; else @@ -1817,16 +1816,16 @@ mips32_next_pc (struct regcache *regcache, CORE_ADDR pc) break; case 7: default: - greater_branch: /* BGTZ, BGTZL */ + greater_branch: /* BGTZ, BGTZL */ if (regcache_raw_get_signed (regcache, itype_rs (inst)) > 0) pc += mips32_relative_offset (inst) + 4; else pc += 8; break; - } /* switch */ - } /* else */ + } /* switch */ + } /* else */ return pc; -} /* mips32_next_pc */ +} /* mips32_next_pc */ /* Extract the 7-bit signed immediate offset from the microMIPS instruction INSN. */ @@ -1950,8 +1949,8 @@ micromips_next_pc (struct regcache *regcache, CORE_ADDR pc) case 0x00: /* BLTZ: bits 010000 00000 */ case 0x01: /* BLTZAL: bits 010000 00001 */ case 0x11: /* BLTZALS: bits 010000 10001 */ - if (regcache_raw_get_signed (regcache, - b0s5_reg (insn >> 16)) < 0) + if (regcache_raw_get_signed (regcache, b0s5_reg (insn >> 16)) + < 0) pc += micromips_relative_offset16 (insn); else pc += micromips_pc_insn_size (gdbarch, pc); @@ -1960,38 +1959,38 @@ micromips_next_pc (struct regcache *regcache, CORE_ADDR pc) case 0x02: /* BGEZ: bits 010000 00010 */ case 0x03: /* BGEZAL: bits 010000 00011 */ case 0x13: /* BGEZALS: bits 010000 10011 */ - if (regcache_raw_get_signed (regcache, - b0s5_reg (insn >> 16)) >= 0) + if (regcache_raw_get_signed (regcache, b0s5_reg (insn >> 16)) + >= 0) pc += micromips_relative_offset16 (insn); else pc += micromips_pc_insn_size (gdbarch, pc); break; case 0x04: /* BLEZ: bits 010000 00100 */ - if (regcache_raw_get_signed (regcache, - b0s5_reg (insn >> 16)) <= 0) + if (regcache_raw_get_signed (regcache, b0s5_reg (insn >> 16)) + <= 0) pc += micromips_relative_offset16 (insn); else pc += micromips_pc_insn_size (gdbarch, pc); break; case 0x05: /* BNEZC: bits 010000 00101 */ - if (regcache_raw_get_signed (regcache, - b0s5_reg (insn >> 16)) != 0) + if (regcache_raw_get_signed (regcache, b0s5_reg (insn >> 16)) + != 0) pc += micromips_relative_offset16 (insn); break; case 0x06: /* BGTZ: bits 010000 00110 */ - if (regcache_raw_get_signed (regcache, - b0s5_reg (insn >> 16)) > 0) + if (regcache_raw_get_signed (regcache, b0s5_reg (insn >> 16)) + > 0) pc += micromips_relative_offset16 (insn); else pc += micromips_pc_insn_size (gdbarch, pc); break; case 0x07: /* BEQZC: bits 010000 00111 */ - if (regcache_raw_get_signed (regcache, - b0s5_reg (insn >> 16)) == 0) + if (regcache_raw_get_signed (regcache, b0s5_reg (insn >> 16)) + == 0) pc += micromips_relative_offset16 (insn); break; @@ -2012,8 +2011,8 @@ micromips_next_pc (struct regcache *regcache, CORE_ADDR pc) /* No way to handle; it'll most likely trap anyway. */ break; - if ((regcache_raw_get_unsigned (regcache, - dspctl) & 0x7f) >= pos) + if ((regcache_raw_get_unsigned (regcache, dspctl) & 0x7f) + >= pos) pc += micromips_relative_offset16 (insn); else pc += micromips_pc_insn_size (gdbarch, pc); @@ -2023,7 +2022,7 @@ micromips_next_pc (struct regcache *regcache, CORE_ADDR pc) case 0x1c: /* BC1F: bits 010000 11100 xxx00 */ /* BC1ANY2F: bits 010000 11100 xxx01 */ case 0x1d: /* BC1T: bits 010000 11101 xxx00 */ - /* BC1ANY2T: bits 010000 11101 xxx01 */ + /* BC1ANY2T: bits 010000 11101 xxx01 */ if (((insn >> 16) & 0x2) == 0x0) pc = micromips_bc1_pc (gdbarch, regcache, insn, pc, ((insn >> 16) & 0x1) + 1); @@ -2040,27 +2039,27 @@ micromips_next_pc (struct regcache *regcache, CORE_ADDR pc) case 0x1d: /* JALS: bits 011101 */ case 0x35: /* J: bits 110101 */ case 0x3d: /* JAL: bits 111101 */ - pc = ((pc | 0x7fffffe) ^ 0x7fffffe) | (b0s26_imm (insn) << 1); + pc = ((pc | 0x7fffffe) ^ 0x7fffffe) | (b0s26_imm (insn) << 1); break; case 0x25: /* BEQ: bits 100101 */ - if (regcache_raw_get_signed (regcache, b0s5_reg (insn >> 16)) - == regcache_raw_get_signed (regcache, b5s5_reg (insn >> 16))) - pc += micromips_relative_offset16 (insn); - else - pc += micromips_pc_insn_size (gdbarch, pc); + if (regcache_raw_get_signed (regcache, b0s5_reg (insn >> 16)) + == regcache_raw_get_signed (regcache, b5s5_reg (insn >> 16))) + pc += micromips_relative_offset16 (insn); + else + pc += micromips_pc_insn_size (gdbarch, pc); break; case 0x2d: /* BNE: bits 101101 */ if (regcache_raw_get_signed (regcache, b0s5_reg (insn >> 16)) - != regcache_raw_get_signed (regcache, b5s5_reg (insn >> 16))) - pc += micromips_relative_offset16 (insn); + != regcache_raw_get_signed (regcache, b5s5_reg (insn >> 16))) + pc += micromips_relative_offset16 (insn); else - pc += micromips_pc_insn_size (gdbarch, pc); + pc += micromips_pc_insn_size (gdbarch, pc); break; case 0x3c: /* JALX: bits 111100 */ - pc = ((pc | 0xfffffff) ^ 0xfffffff) | (b0s26_imm (insn) << 2); + pc = ((pc | 0xfffffff) ^ 0xfffffff) | (b0s26_imm (insn) << 2); break; } break; @@ -2121,39 +2120,39 @@ micromips_next_pc (struct regcache *regcache, CORE_ADDR pc) and their extensions extItype,extritype,extI8type. */ enum mips16_inst_fmts { - itype, /* 0 immediate 5,10 */ - ritype, /* 1 5,3,8 */ - rrtype, /* 2 5,3,3,5 */ - rritype, /* 3 5,3,3,5 */ - rrrtype, /* 4 5,3,3,3,2 */ - rriatype, /* 5 5,3,3,1,4 */ - shifttype, /* 6 5,3,3,3,2 */ - i8type, /* 7 5,3,8 */ - i8movtype, /* 8 5,3,3,5 */ - i8mov32rtype, /* 9 5,3,5,3 */ - i64type, /* 10 5,3,8 */ - ri64type, /* 11 5,3,3,5 */ - jalxtype, /* 12 5,1,5,5,16 - a 32 bit instruction */ - exiItype, /* 13 5,6,5,5,1,1,1,1,1,1,5 */ - extRitype, /* 14 5,6,5,5,3,1,1,1,5 */ - extRRItype, /* 15 5,5,5,5,3,3,5 */ - extRRIAtype, /* 16 5,7,4,5,3,3,1,4 */ - EXTshifttype, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */ - extI8type, /* 18 5,6,5,5,3,1,1,1,5 */ - extI64type, /* 19 5,6,5,5,3,1,1,1,5 */ - extRi64type, /* 20 5,6,5,5,3,3,5 */ - extshift64type /* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */ + itype, /* 0 immediate 5,10 */ + ritype, /* 1 5,3,8 */ + rrtype, /* 2 5,3,3,5 */ + rritype, /* 3 5,3,3,5 */ + rrrtype, /* 4 5,3,3,3,2 */ + rriatype, /* 5 5,3,3,1,4 */ + shifttype, /* 6 5,3,3,3,2 */ + i8type, /* 7 5,3,8 */ + i8movtype, /* 8 5,3,3,5 */ + i8mov32rtype, /* 9 5,3,5,3 */ + i64type, /* 10 5,3,8 */ + ri64type, /* 11 5,3,3,5 */ + jalxtype, /* 12 5,1,5,5,16 - a 32 bit instruction */ + exiItype, /* 13 5,6,5,5,1,1,1,1,1,1,5 */ + extRitype, /* 14 5,6,5,5,3,1,1,1,5 */ + extRRItype, /* 15 5,5,5,5,3,3,5 */ + extRRIAtype, /* 16 5,7,4,5,3,3,1,4 */ + EXTshifttype, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */ + extI8type, /* 18 5,6,5,5,3,1,1,1,5 */ + extI64type, /* 19 5,6,5,5,3,1,1,1,5 */ + extRi64type, /* 20 5,6,5,5,3,3,5 */ + extshift64type /* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */ }; + /* I am heaping all the fields of the formats into one structure and then, only the fields which are involved in instruction extension. */ struct upk_mips16 { CORE_ADDR offset; - unsigned int regx; /* Function in i8 type. */ + unsigned int regx; /* Function in i8 type. */ unsigned int regy; }; - /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format for the bits which make up the immediate extension. */ @@ -2162,11 +2161,11 @@ extended_offset (unsigned int extension) { CORE_ADDR value; - value = (extension >> 16) & 0x1f; /* Extract 15:11. */ + value = (extension >> 16) & 0x1f; /* Extract 15:11. */ value = value << 6; - value |= (extension >> 21) & 0x3f; /* Extract 10:5. */ + value |= (extension >> 21) & 0x3f; /* Extract 10:5. */ value = value << 5; - value |= extension & 0x1f; /* Extract 4:0. */ + value |= extension & 0x1f; /* Extract 4:0. */ return value; } @@ -2184,16 +2183,15 @@ fetch_mips_16 (struct gdbarch *gdbarch, CORE_ADDR pc) enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); gdb_byte buf[8]; - pc = unmake_compact_addr (pc); /* Clear the low order bit. */ + pc = unmake_compact_addr (pc); /* Clear the low order bit. */ target_read_memory (pc, buf, 2); return extract_unsigned_integer (buf, 2, byte_order); } static void -unpack_mips16 (struct gdbarch *gdbarch, CORE_ADDR pc, - unsigned int extension, - unsigned int inst, - enum mips16_inst_fmts insn_format, struct upk_mips16 *upk) +unpack_mips16 (struct gdbarch *gdbarch, CORE_ADDR pc, unsigned int extension, + unsigned int inst, enum mips16_inst_fmts insn_format, + struct upk_mips16 *upk) { CORE_ADDR offset; int regx; @@ -2206,12 +2204,12 @@ unpack_mips16 (struct gdbarch *gdbarch, CORE_ADDR pc, if (extension) { value = extended_offset ((extension << 16) | inst); - value = (value ^ 0x8000) - 0x8000; /* Sign-extend. */ + value = (value ^ 0x8000) - 0x8000; /* Sign-extend. */ } else { value = inst & 0x7ff; - value = (value ^ 0x400) - 0x400; /* Sign-extend. */ + value = (value ^ 0x400) - 0x400; /* Sign-extend. */ } offset = value; regx = -1; @@ -2220,22 +2218,22 @@ unpack_mips16 (struct gdbarch *gdbarch, CORE_ADDR pc, break; case ritype: case i8type: - { /* A register identifier and an offset. */ + { /* A register identifier and an offset. */ /* Most of the fields are the same as I type but the immediate value is of a different length. */ CORE_ADDR value; if (extension) { value = extended_offset ((extension << 16) | inst); - value = (value ^ 0x8000) - 0x8000; /* Sign-extend. */ + value = (value ^ 0x8000) - 0x8000; /* Sign-extend. */ } else { - value = inst & 0xff; /* 8 bits */ - value = (value ^ 0x80) - 0x80; /* Sign-extend. */ + value = inst & 0xff; /* 8 bits */ + value = (value ^ 0x80) - 0x80; /* Sign-extend. */ } offset = value; - regx = (inst >> 8) & 0x07; /* i8 funct */ + regx = (inst >> 8) & 0x07; /* i8 funct */ regy = -1; break; } @@ -2246,7 +2244,7 @@ unpack_mips16 (struct gdbarch *gdbarch, CORE_ADDR pc, value = ((inst & 0x1f) << 5) | ((inst >> 5) & 0x1f); value = value << 16; nexthalf = mips_fetch_instruction (gdbarch, ISA_MIPS16, pc + 2, NULL); - /* Low bit still set. */ + /* Low bit still set. */ value |= nexthalf; offset = value; regx = -1; @@ -2254,14 +2252,13 @@ unpack_mips16 (struct gdbarch *gdbarch, CORE_ADDR pc, break; } default: - internal_error (_("bad switch")); + internal_error (_ ("bad switch")); } upk->offset = offset; upk->regx = regx; upk->regy = regy; } - /* Calculate the destination of a branch whose 16-bit opcode word is at PC, and having a signed 16-bit OFFSET. */ @@ -2279,26 +2276,26 @@ extended_mips16_next_pc (regcache *regcache, CORE_ADDR pc, int op = (insn >> 11); switch (op) { - case 2: /* Branch */ + case 2: /* Branch */ { struct upk_mips16 upk; unpack_mips16 (gdbarch, pc, extension, insn, itype, &upk); pc = add_offset_16 (pc, upk.offset); break; } - case 3: /* JAL , JALX - Watch out, these are 32 bit + case 3: /* JAL , JALX - Watch out, these are 32 bit instructions. */ { struct upk_mips16 upk; unpack_mips16 (gdbarch, pc, extension, insn, jalxtype, &upk); pc = ((pc + 2) & (~(CORE_ADDR) 0x0fffffff)) | (upk.offset << 2); - if ((insn >> 10) & 0x01) /* Exchange mode */ - pc = pc & ~0x01; /* Clear low bit, indicate 32 bit mode. */ + if ((insn >> 10) & 0x01) /* Exchange mode */ + pc = pc & ~0x01; /* Clear low bit, indicate 32 bit mode. */ else pc |= 0x01; break; } - case 4: /* beqz */ + case 4: /* beqz */ { struct upk_mips16 upk; int reg; @@ -2310,7 +2307,7 @@ extended_mips16_next_pc (regcache *regcache, CORE_ADDR pc, pc += 2; break; } - case 5: /* bnez */ + case 5: /* bnez */ { struct upk_mips16 upk; int reg; @@ -2322,7 +2319,7 @@ extended_mips16_next_pc (regcache *regcache, CORE_ADDR pc, pc += 2; break; } - case 12: /* I8 Formats btez btnez */ + case 12: /* I8 Formats btez btnez */ { struct upk_mips16 upk; int reg; @@ -2331,13 +2328,13 @@ extended_mips16_next_pc (regcache *regcache, CORE_ADDR pc, /* Test register is 24 */ reg = regcache_raw_get_signed (regcache, 24); if (((upk.regx == 0) && (reg == 0)) /* BTEZ */ - || ((upk.regx == 1) && (reg != 0))) /* BTNEZ */ + || ((upk.regx == 1) && (reg != 0))) /* BTNEZ */ pc = add_offset_16 (pc, upk.offset); else pc += 2; break; } - case 29: /* RR Formats JR, JALR, JALR-RA */ + case 29: /* RR Formats JR, JALR, JALR-RA */ { struct upk_mips16 upk; /* upk.fmt = rrtype; */ @@ -2350,7 +2347,7 @@ extended_mips16_next_pc (regcache *regcache, CORE_ADDR pc, if ((upk.regy & 1) == 0) reg = mips_reg3_to_reg[upk.regx]; else - reg = 31; /* Function return instruction. */ + reg = 31; /* Function return instruction. */ pc = regcache_raw_get_signed (regcache, reg); } else @@ -2411,12 +2408,12 @@ mips16_instruction_is_compact_branch (unsigned short insn) switch (insn & 0xf800) { case 0xe800: - return (insn & 0x009f) == 0x80; /* JALRC/JRC */ + return (insn & 0x009f) == 0x80; /* JALRC/JRC */ case 0x6000: - return (insn & 0x0600) == 0; /* BTNEZ/BTEQZ */ - case 0x2800: /* BNEZ */ - case 0x2000: /* BEQZ */ - case 0x1000: /* B */ + return (insn & 0x0600) == 0; /* BTNEZ/BTEQZ */ + case 0x2800: /* BNEZ */ + case 0x2000: /* BEQZ */ + case 0x1000: /* B */ return 1; default: return 0; @@ -2431,14 +2428,14 @@ micromips_instruction_is_compact_branch (unsigned short insn) { switch (micromips_op (insn)) { - case 0x11: /* POOL16C: bits 010001 */ + case 0x11: /* POOL16C: bits 010001 */ return (b5s5_op (insn) == 0x18 - /* JRADDIUSP: bits 010001 11000 */ + /* JRADDIUSP: bits 010001 11000 */ || b5s5_op (insn) == 0xd); - /* JRC: bits 010011 01101 */ - case 0x10: /* POOL32I: bits 010000 */ + /* JRC: bits 010011 01101 */ + case 0x10: /* POOL32I: bits 010000 */ return (b5s5_op (insn) & 0x1d) == 0x5; - /* BEQZC/BNEZC: bits 010000 001x1 */ + /* BEQZC/BNEZC: bits 010000 001x1 */ default: return 0; } @@ -2465,36 +2462,34 @@ static void set_reg_offset (struct gdbarch *gdbarch, struct mips_frame_cache *this_cache, int regnum, CORE_ADDR offset) { - if (this_cache != NULL - && this_cache->saved_regs[regnum].is_realreg () + if (this_cache != NULL && this_cache->saved_regs[regnum].is_realreg () && this_cache->saved_regs[regnum].realreg () == regnum) { - this_cache->saved_regs[regnum + 0 - * gdbarch_num_regs (gdbarch)].set_addr (offset); - this_cache->saved_regs[regnum + 1 - * gdbarch_num_regs (gdbarch)].set_addr (offset); + this_cache->saved_regs[regnum + 0 * gdbarch_num_regs (gdbarch)] + .set_addr (offset); + this_cache->saved_regs[regnum + 1 * gdbarch_num_regs (gdbarch)] + .set_addr (offset); } } - /* Fetch the immediate value from a MIPS16 instruction. If the previous instruction was an EXTEND, use it to extend the upper bits of the immediate value. This is a helper function for mips16_scan_prologue. */ static int -mips16_get_imm (unsigned short prev_inst, /* previous instruction */ - unsigned short inst, /* current instruction */ - int nbits, /* number of bits in imm field */ - int scale, /* scale factor to be applied to imm */ - int is_signed) /* is the imm field signed? */ +mips16_get_imm (unsigned short prev_inst, /* previous instruction */ + unsigned short inst, /* current instruction */ + int nbits, /* number of bits in imm field */ + int scale, /* scale factor to be applied to imm */ + int is_signed) /* is the imm field signed? */ { int offset; - if ((prev_inst & 0xf800) == 0xf000) /* prev instruction was EXTEND? */ + if ((prev_inst & 0xf800) == 0xf000) /* prev instruction was EXTEND? */ { offset = ((prev_inst & 0x1f) << 11) | (prev_inst & 0x7e0); - if (offset & 0x8000) /* check for negative extend */ + if (offset & 0x8000) /* check for negative extend */ offset = 0 - (0x10000 - (offset & 0xffff)); return offset | (inst & 0x1f); } @@ -2511,15 +2506,13 @@ mips16_get_imm (unsigned short prev_inst, /* previous instruction */ } } - /* Analyze the function prologue from START_PC to LIMIT_PC. Builds the associated FRAME_CACHE if not null. Return the address of the first instruction past the prologue. */ static CORE_ADDR -mips16_scan_prologue (struct gdbarch *gdbarch, - CORE_ADDR start_pc, CORE_ADDR limit_pc, - frame_info_ptr this_frame, +mips16_scan_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc, + CORE_ADDR limit_pc, frame_info_ptr this_frame, struct mips_frame_cache *this_cache) { int prev_non_prologue_insn = 0; @@ -2527,12 +2520,12 @@ mips16_scan_prologue (struct gdbarch *gdbarch, int non_prologue_insns = 0; CORE_ADDR prev_pc; CORE_ADDR cur_pc; - CORE_ADDR frame_addr = 0; /* Value of $r17, used as frame pointer. */ + CORE_ADDR frame_addr = 0; /* Value of $r17, used as frame pointer. */ CORE_ADDR sp; - long frame_offset = 0; /* Size of stack frame. */ - long frame_adjust = 0; /* Offset of FP from SP. */ + long frame_offset = 0; /* Size of stack frame. */ + long frame_adjust = 0; /* Offset of FP from SP. */ int frame_reg = MIPS_SP_REGNUM; - unsigned short prev_inst = 0; /* saved copy of previous instruction. */ + unsigned short prev_inst = 0; /* saved copy of previous instruction. */ unsigned inst = 0; /* current instruction */ unsigned entry_inst = 0; /* the entry instruction */ unsigned save_inst = 0; /* the save instruction */ @@ -2547,9 +2540,8 @@ mips16_scan_prologue (struct gdbarch *gdbarch, /* Can be called when there's no process, and hence when there's no THIS_FRAME. */ if (this_frame != NULL) - sp = get_frame_register_signed (this_frame, - gdbarch_num_regs (gdbarch) - + MIPS_SP_REGNUM); + sp = get_frame_register_signed (this_frame, gdbarch_num_regs (gdbarch) + + MIPS_SP_REGNUM); else sp = 0; @@ -2578,7 +2570,7 @@ mips16_scan_prologue (struct gdbarch *gdbarch, instruction is not part of the prologue either. We must remember in this case to adjust the end_prologue_addr back over the extend. */ - if ((inst & 0xf800) == 0xf000) /* extend */ + if ((inst & 0xf800) == 0xf000) /* extend */ { extend_bytes = MIPS_INSN16_SIZE; continue; @@ -2588,10 +2580,10 @@ mips16_scan_prologue (struct gdbarch *gdbarch, extend_bytes = 0; if ((inst & 0xff00) == 0x6300 /* addiu sp */ - || (inst & 0xff00) == 0xfb00) /* daddiu sp */ + || (inst & 0xff00) == 0xfb00) /* daddiu sp */ { offset = mips16_get_imm (prev_inst, inst, 8, 8, 1); - if (offset < 0) /* Negative stack adjustment? */ + if (offset < 0) /* Negative stack adjustment? */ frame_offset -= offset; else /* Exit loop if a positive stack adjustment is found, which @@ -2599,77 +2591,77 @@ mips16_scan_prologue (struct gdbarch *gdbarch, epilogue is reached. */ break; } - else if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */ + else if ((inst & 0xf800) == 0xd000) /* sw reg,n($sp) */ { offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); reg = mips_reg3_to_reg[(inst & 0x700) >> 8]; set_reg_offset (gdbarch, this_cache, reg, sp + offset); } - else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */ + else if ((inst & 0xff00) == 0xf900) /* sd reg,n($sp) */ { offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); reg = mips_reg3_to_reg[(inst & 0xe0) >> 5]; set_reg_offset (gdbarch, this_cache, reg, sp + offset); } - else if ((inst & 0xff00) == 0x6200) /* sw $ra,n($sp) */ + else if ((inst & 0xff00) == 0x6200) /* sw $ra,n($sp) */ { offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); } - else if ((inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */ + else if ((inst & 0xff00) == 0xfa00) /* sd $ra,n($sp) */ { offset = mips16_get_imm (prev_inst, inst, 8, 8, 0); set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, sp + offset); } - else if (inst == 0x673d) /* move $s1, $sp */ + else if (inst == 0x673d) /* move $s1, $sp */ { frame_addr = sp; frame_reg = 17; } - else if ((inst & 0xff00) == 0x0100) /* addiu $s1,sp,n */ + else if ((inst & 0xff00) == 0x0100) /* addiu $s1,sp,n */ { offset = mips16_get_imm (prev_inst, inst, 8, 4, 0); frame_addr = sp + offset; frame_reg = 17; frame_adjust = offset; } - else if ((inst & 0xFF00) == 0xd900) /* sw reg,offset($s1) */ + else if ((inst & 0xFF00) == 0xd900) /* sw reg,offset($s1) */ { offset = mips16_get_imm (prev_inst, inst, 5, 4, 0); reg = mips_reg3_to_reg[(inst & 0xe0) >> 5]; set_reg_offset (gdbarch, this_cache, reg, frame_addr + offset); } - else if ((inst & 0xFF00) == 0x7900) /* sd reg,offset($s1) */ + else if ((inst & 0xFF00) == 0x7900) /* sd reg,offset($s1) */ { offset = mips16_get_imm (prev_inst, inst, 5, 8, 0); reg = mips_reg3_to_reg[(inst & 0xe0) >> 5]; set_reg_offset (gdbarch, this_cache, reg, frame_addr + offset); } else if ((inst & 0xf81f) == 0xe809 - && (inst & 0x700) != 0x700) /* entry */ - entry_inst = inst; /* Save for later processing. */ - else if ((inst & 0xff80) == 0x6480) /* save */ + && (inst & 0x700) != 0x700) /* entry */ + entry_inst = inst; /* Save for later processing. */ + else if ((inst & 0xff80) == 0x6480) /* save */ { - save_inst = inst; /* Save for later processing. */ - if (prev_extend_bytes) /* extend */ + save_inst = inst; /* Save for later processing. */ + if (prev_extend_bytes) /* extend */ save_inst |= prev_inst << 16; } - else if ((inst & 0xff1c) == 0x6704) /* move reg,$a0-$a3 */ + else if ((inst & 0xff1c) == 0x6704) /* move reg,$a0-$a3 */ { /* This instruction is part of the prologue, but we don't need to do anything special to handle it. */ } else if (mips16_instruction_has_delay_slot (inst, 0)) - /* JAL/JALR/JALX/JR */ + /* JAL/JALR/JALX/JR */ { /* The instruction in the delay slot can be a part of the prologue, so move forward once more. */ in_delay_slot = 1; if (mips16_instruction_has_delay_slot (inst, 1)) - /* JAL/JALX */ + /* JAL/JALX */ { prev_extend_bytes = MIPS_INSN16_SIZE; - cur_pc += MIPS_INSN16_SIZE; /* 32-bit instruction */ + cur_pc += MIPS_INSN16_SIZE; /* 32-bit instruction */ } } else @@ -2740,12 +2732,10 @@ mips16_scan_prologue (struct gdbarch *gdbarch, if (save_inst != 0 && mips_abi_regsize (gdbarch) == 4) { static int args_table[16] = { - 0, 0, 0, 0, 1, 1, 1, 1, - 2, 2, 2, 0, 3, 3, 4, -1, + 0, 0, 0, 0, 1, 1, 1, 1, 2, 2, 2, 0, 3, 3, 4, -1, }; static int astatic_table[16] = { - 0, 1, 2, 3, 0, 1, 2, 3, - 0, 1, 2, 4, 0, 1, 0, -1, + 0, 1, 2, 3, 0, 1, 2, 3, 0, 1, 2, 4, 0, 1, 0, -1, }; int aregs = (save_inst >> 16) & 0xf; int xsregs = (save_inst >> 24) & 0x7; @@ -2755,12 +2745,13 @@ mips16_scan_prologue (struct gdbarch *gdbarch, if (args < 0) { - warning (_("Invalid number of argument registers encoded in SAVE.")); + warning ( + _ ("Invalid number of argument registers encoded in SAVE.")); args = 0; } if (astatic < 0) { - warning (_("Invalid number of static registers encoded in SAVE.")); + warning (_ ("Invalid number of static registers encoded in SAVE.")); astatic = 0; } @@ -2828,15 +2819,15 @@ mips16_scan_prologue (struct gdbarch *gdbarch, if (this_cache != NULL) { - this_cache->base = - (get_frame_register_signed (this_frame, - gdbarch_num_regs (gdbarch) + frame_reg) - + frame_offset - frame_adjust); + this_cache->base + = (get_frame_register_signed (this_frame, + gdbarch_num_regs (gdbarch) + frame_reg) + + frame_offset - frame_adjust); /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should be able to get rid of the assignment below, evetually. But it's still needed for now. */ - this_cache->saved_regs[gdbarch_num_regs (gdbarch) - + mips_regnum (gdbarch)->pc] + this_cache + ->saved_regs[gdbarch_num_regs (gdbarch) + mips_regnum (gdbarch)->pc] = this_cache->saved_regs[gdbarch_num_regs (gdbarch) + MIPS_RA_REGNUM]; } @@ -2844,8 +2835,9 @@ mips16_scan_prologue (struct gdbarch *gdbarch, after the last one we scanned. Unless the last one looked like a non-prologue instruction (and we looked ahead), in which case use its address instead. */ - end_prologue_addr = (prev_non_prologue_insn || prev_delay_slot - ? prev_pc : cur_pc - prev_extend_bytes); + end_prologue_addr + = (prev_non_prologue_insn || prev_delay_slot ? prev_pc + : cur_pc - prev_extend_bytes); return end_prologue_addr; } @@ -2882,10 +2874,10 @@ mips_insn16_frame_cache (frame_info_ptr this_frame, void **this_cache) mips16_scan_prologue (gdbarch, start_addr, pc, this_frame, (struct mips_frame_cache *) *this_cache); } - + /* gdbarch_sp_regnum contains the value and not the address. */ - cache->saved_regs[gdbarch_num_regs (gdbarch) - + MIPS_SP_REGNUM].set_value (cache->base); + cache->saved_regs[gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM].set_value ( + cache->base); return (struct mips_frame_cache *) (*this_cache); } @@ -2894,8 +2886,8 @@ static void mips_insn16_frame_this_id (frame_info_ptr this_frame, void **this_cache, struct frame_id *this_id) { - struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame, - this_cache); + struct mips_frame_cache *info + = mips_insn16_frame_cache (this_frame, this_cache); /* This marks the outermost frame. */ if (info->base == 0) return; @@ -2903,11 +2895,11 @@ mips_insn16_frame_this_id (frame_info_ptr this_frame, void **this_cache, } static struct value * -mips_insn16_frame_prev_register (frame_info_ptr this_frame, - void **this_cache, int regnum) +mips_insn16_frame_prev_register (frame_info_ptr this_frame, void **this_cache, + int regnum) { - struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame, - this_cache); + struct mips_frame_cache *info + = mips_insn16_frame_cache (this_frame, this_cache); return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); } @@ -2922,33 +2914,23 @@ mips_insn16_frame_sniffer (const struct frame_unwind *self, return 0; } -static const struct frame_unwind mips_insn16_frame_unwind = -{ - "mips insn16 prologue", - NORMAL_FRAME, - default_frame_unwind_stop_reason, - mips_insn16_frame_this_id, - mips_insn16_frame_prev_register, - NULL, - mips_insn16_frame_sniffer -}; +static const struct frame_unwind mips_insn16_frame_unwind + = { "mips insn16 prologue", NORMAL_FRAME, + default_frame_unwind_stop_reason, mips_insn16_frame_this_id, + mips_insn16_frame_prev_register, NULL, + mips_insn16_frame_sniffer }; static CORE_ADDR -mips_insn16_frame_base_address (frame_info_ptr this_frame, - void **this_cache) +mips_insn16_frame_base_address (frame_info_ptr this_frame, void **this_cache) { - struct mips_frame_cache *info = mips_insn16_frame_cache (this_frame, - this_cache); + struct mips_frame_cache *info + = mips_insn16_frame_cache (this_frame, this_cache); return info->base; } -static const struct frame_base mips_insn16_frame_base = -{ - &mips_insn16_frame_unwind, - mips_insn16_frame_base_address, - mips_insn16_frame_base_address, - mips_insn16_frame_base_address -}; +static const struct frame_base mips_insn16_frame_base + = { &mips_insn16_frame_unwind, mips_insn16_frame_base_address, + mips_insn16_frame_base_address, mips_insn16_frame_base_address }; static const struct frame_base * mips_insn16_frame_base_sniffer (frame_info_ptr this_frame) @@ -2978,9 +2960,8 @@ micromips_decode_imm9 (int imm) the address of the first instruction past the prologue. */ static CORE_ADDR -micromips_scan_prologue (struct gdbarch *gdbarch, - CORE_ADDR start_pc, CORE_ADDR limit_pc, - frame_info_ptr this_frame, +micromips_scan_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc, + CORE_ADDR limit_pc, frame_info_ptr this_frame, struct mips_frame_cache *this_cache) { CORE_ADDR end_prologue_addr; @@ -2988,17 +2969,17 @@ micromips_scan_prologue (struct gdbarch *gdbarch, int frame_reg = MIPS_SP_REGNUM; int this_non_prologue_insn; int non_prologue_insns = 0; - long frame_offset = 0; /* Size of stack frame. */ - long frame_adjust = 0; /* Offset of FP from SP. */ + long frame_offset = 0; /* Size of stack frame. */ + long frame_adjust = 0; /* Offset of FP from SP. */ int prev_delay_slot = 0; int in_delay_slot; CORE_ADDR prev_pc; CORE_ADDR cur_pc; - ULONGEST insn; /* current instruction */ + ULONGEST insn; /* current instruction */ CORE_ADDR sp; long offset; long sp_adj; - long v1_off = 0; /* The assumption is LUI will replace it. */ + long v1_off = 0; /* The assumption is LUI will replace it. */ int reglist; int breg; int dreg; @@ -3012,9 +2993,8 @@ micromips_scan_prologue (struct gdbarch *gdbarch, /* Can be called when there's no process, and hence when there's no THIS_FRAME. */ if (this_frame != NULL) - sp = get_frame_register_signed (this_frame, - gdbarch_num_regs (gdbarch) - + MIPS_SP_REGNUM); + sp = get_frame_register_signed (this_frame, gdbarch_num_regs (gdbarch) + + MIPS_SP_REGNUM); else sp = 0; @@ -3038,29 +3018,29 @@ micromips_scan_prologue (struct gdbarch *gdbarch, /* 32-bit instructions. */ case 2 * MIPS_INSN16_SIZE: insn <<= 16; - insn |= mips_fetch_instruction (gdbarch, - ISA_MICROMIPS, cur_pc + loc, NULL); + insn |= mips_fetch_instruction (gdbarch, ISA_MICROMIPS, cur_pc + loc, + NULL); loc += MIPS_INSN16_SIZE; switch (micromips_op (insn >> 16)) { /* Record $sp/$fp adjustment. */ /* Discard (D)ADDU $gp,$jp used for PIC code. */ - case 0x0: /* POOL32A: bits 000000 */ + case 0x0: /* POOL32A: bits 000000 */ case 0x16: /* POOL32S: bits 010110 */ op = b0s11_op (insn); sreg = b0s5_reg (insn >> 16); treg = b5s5_reg (insn >> 16); dreg = b11s5_reg (insn); if (op == 0x1d0 - /* SUBU: bits 000000 00111010000 */ - /* DSUBU: bits 010110 00111010000 */ + /* SUBU: bits 000000 00111010000 */ + /* DSUBU: bits 010110 00111010000 */ && dreg == MIPS_SP_REGNUM && sreg == MIPS_SP_REGNUM && treg == 3) - /* (D)SUBU $sp, $v1 */ - sp_adj = v1_off; + /* (D)SUBU $sp, $v1 */ + sp_adj = v1_off; else if (op != 0x150 - /* ADDU: bits 000000 00101010000 */ - /* DADDU: bits 010110 00101010000 */ + /* ADDU: bits 000000 00101010000 */ + /* DADDU: bits 010110 00101010000 */ || dreg != 28 || sreg != 28 || treg != MIPS_T9_REGNUM) this_non_prologue_insn = 1; break; @@ -3071,26 +3051,25 @@ micromips_scan_prologue (struct gdbarch *gdbarch, reglist = sreg = b5s5_reg (insn >> 16); offset = (b0s12_imm (insn) ^ 0x800) - 0x800; if ((op == 0x9 || op == 0xc) - /* SWP: bits 001000 1001 */ - /* SDP: bits 001000 1100 */ + /* SWP: bits 001000 1001 */ + /* SDP: bits 001000 1100 */ && breg == MIPS_SP_REGNUM && sreg < MIPS_RA_REGNUM) - /* S[DW]P reg,offset($sp) */ + /* S[DW]P reg,offset($sp) */ { s = 4 << ((b12s4_op (insn) & 0x4) == 0x4); - set_reg_offset (gdbarch, this_cache, - sreg, sp + offset); - set_reg_offset (gdbarch, this_cache, - sreg + 1, sp + offset + s); + set_reg_offset (gdbarch, this_cache, sreg, sp + offset); + set_reg_offset (gdbarch, this_cache, sreg + 1, + sp + offset + s); } else if ((op == 0xd || op == 0xf) - /* SWM: bits 001000 1101 */ - /* SDM: bits 001000 1111 */ + /* SWM: bits 001000 1101 */ + /* SDM: bits 001000 1111 */ && breg == MIPS_SP_REGNUM - /* SWM reglist,offset($sp) */ + /* SWM reglist,offset($sp) */ && ((reglist >= 1 && reglist <= 9) || (reglist >= 16 && reglist <= 25))) { - int sreglist = std::min(reglist & 0xf, 8); + int sreglist = std::min (reglist & 0xf, 8); s = 4 << ((b12s4_op (insn) & 0x2) == 0x2); for (i = 0; i < sreglist; i++) @@ -3098,8 +3077,8 @@ micromips_scan_prologue (struct gdbarch *gdbarch, if ((reglist & 0xf) > 8) set_reg_offset (gdbarch, this_cache, 30, sp + s * i++); if ((reglist & 0x10) == 0x10) - set_reg_offset (gdbarch, this_cache, - MIPS_RA_REGNUM, sp + s * i++); + set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, + sp + s * i++); } else this_non_prologue_insn = 1; @@ -3107,22 +3086,22 @@ micromips_scan_prologue (struct gdbarch *gdbarch, /* Record $sp/$fp adjustment. */ /* Discard (D)ADDIU $gp used for PIC code. */ - case 0xc: /* ADDIU: bits 001100 */ + case 0xc: /* ADDIU: bits 001100 */ case 0x17: /* DADDIU: bits 010111 */ sreg = b0s5_reg (insn >> 16); dreg = b5s5_reg (insn >> 16); offset = (b0s16_imm (insn) ^ 0x8000) - 0x8000; if (sreg == MIPS_SP_REGNUM && dreg == MIPS_SP_REGNUM) - /* (D)ADDIU $sp, imm */ + /* (D)ADDIU $sp, imm */ sp_adj = offset; else if (sreg == MIPS_SP_REGNUM && dreg == 30) - /* (D)ADDIU $fp, $sp, imm */ + /* (D)ADDIU $fp, $sp, imm */ { frame_adjust = offset; frame_reg = 30; } else if (sreg != 28 || dreg != 28) - /* (D)ADDIU $gp, imm */ + /* (D)ADDIU $gp, imm */ this_non_prologue_insn = 1; break; @@ -3130,14 +3109,14 @@ micromips_scan_prologue (struct gdbarch *gdbarch, /* Discard LUI $gp used for PIC code. */ case 0x10: /* POOL32I: bits 010000 */ if (b5s5_op (insn >> 16) == 0xd - /* LUI: bits 010000 001101 */ + /* LUI: bits 010000 001101 */ && b0s5_reg (insn >> 16) == 3) - /* LUI $v1, imm */ + /* LUI $v1, imm */ v1_off = ((b0s16_imm (insn) << 16) ^ 0x80000000) - 0x80000000; else if (b5s5_op (insn >> 16) != 0xd - /* LUI: bits 010000 001101 */ + /* LUI: bits 010000 001101 */ || b0s5_reg (insn >> 16) != 28) - /* LUI $gp, imm */ + /* LUI $gp, imm */ this_non_prologue_insn = 1; break; @@ -3146,7 +3125,7 @@ micromips_scan_prologue (struct gdbarch *gdbarch, sreg = b0s5_reg (insn >> 16); dreg = b5s5_reg (insn >> 16); if (sreg == 3 && dreg == 3) - /* ORI $v1, imm */ + /* ORI $v1, imm */ v1_off |= b0s16_imm (insn); else this_non_prologue_insn = 1; @@ -3156,7 +3135,7 @@ micromips_scan_prologue (struct gdbarch *gdbarch, case 0x2e: /* SDC1: bits 101110 */ breg = b0s5_reg (insn >> 16); if (breg != MIPS_SP_REGNUM) - /* S[DW]C1 reg,offset($sp) */ + /* S[DW]C1 reg,offset($sp) */ this_non_prologue_insn = 1; break; @@ -3166,7 +3145,7 @@ micromips_scan_prologue (struct gdbarch *gdbarch, sreg = b5s5_reg (insn >> 16); offset = (b0s16_imm (insn) ^ 0x8000) - 0x8000; if (breg == MIPS_SP_REGNUM) - /* S[DW] reg,offset($sp) */ + /* S[DW] reg,offset($sp) */ set_reg_offset (gdbarch, this_cache, sreg, sp + offset); else this_non_prologue_insn = 1; @@ -3192,23 +3171,23 @@ micromips_scan_prologue (struct gdbarch *gdbarch, sreg = b0s5_reg (insn); dreg = b5s5_reg (insn); if (sreg == MIPS_SP_REGNUM && dreg == 30) - /* MOVE $fp, $sp */ + /* MOVE $fp, $sp */ frame_reg = 30; else if ((sreg & 0x1c) != 0x4) - /* MOVE reg, $a0-$a3 */ + /* MOVE reg, $a0-$a3 */ this_non_prologue_insn = 1; break; case 0x11: /* POOL16C: bits 010001 */ if (b6s4_op (insn) == 0x5) - /* SWM: bits 010001 0101 */ + /* SWM: bits 010001 0101 */ { offset = ((b0s4_imm (insn) << 2) ^ 0x20) - 0x20; reglist = b4s2_regl (insn); for (i = 0; i <= reglist; i++) set_reg_offset (gdbarch, this_cache, 16 + i, sp + 4 * i); - set_reg_offset (gdbarch, this_cache, - MIPS_RA_REGNUM, sp + 4 * i++); + set_reg_offset (gdbarch, this_cache, MIPS_RA_REGNUM, + sp + 4 * i++); } else this_non_prologue_insn = 1; @@ -3216,11 +3195,11 @@ micromips_scan_prologue (struct gdbarch *gdbarch, case 0x13: /* POOL16D: bits 010011 */ if ((insn & 0x1) == 0x1) - /* ADDIUSP: bits 010011 1 */ + /* ADDIUSP: bits 010011 1 */ sp_adj = micromips_decode_imm9 (b1s9_imm (insn)); else if (b5s5_reg (insn) == MIPS_SP_REGNUM) - /* ADDIUS5: bits 010011 0 */ - /* ADDIUS5 $sp, imm */ + /* ADDIUS5: bits 010011 0 */ + /* ADDIUS5 $sp, imm */ sp_adj = (b1s4_imm (insn) ^ 8) - 8; else this_non_prologue_insn = 1; @@ -3262,15 +3241,15 @@ micromips_scan_prologue (struct gdbarch *gdbarch, if (this_cache != NULL) { - this_cache->base = - (get_frame_register_signed (this_frame, - gdbarch_num_regs (gdbarch) + frame_reg) - + frame_offset - frame_adjust); + this_cache->base + = (get_frame_register_signed (this_frame, + gdbarch_num_regs (gdbarch) + frame_reg) + + frame_offset - frame_adjust); /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should be able to get rid of the assignment below, evetually. But it's still needed for now. */ - this_cache->saved_regs[gdbarch_num_regs (gdbarch) - + mips_regnum (gdbarch)->pc] + this_cache + ->saved_regs[gdbarch_num_regs (gdbarch) + mips_regnum (gdbarch)->pc] = this_cache->saved_regs[gdbarch_num_regs (gdbarch) + MIPS_RA_REGNUM]; } @@ -3319,8 +3298,8 @@ mips_micro_frame_cache (frame_info_ptr this_frame, void **this_cache) } /* gdbarch_sp_regnum contains the value and not the address. */ - cache->saved_regs[gdbarch_num_regs (gdbarch) - + MIPS_SP_REGNUM].set_value (cache->base); + cache->saved_regs[gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM].set_value ( + cache->base); return (struct mips_frame_cache *) (*this_cache); } @@ -3329,8 +3308,8 @@ static void mips_micro_frame_this_id (frame_info_ptr this_frame, void **this_cache, struct frame_id *this_id) { - struct mips_frame_cache *info = mips_micro_frame_cache (this_frame, - this_cache); + struct mips_frame_cache *info + = mips_micro_frame_cache (this_frame, this_cache); /* This marks the outermost frame. */ if (info->base == 0) return; @@ -3338,11 +3317,11 @@ mips_micro_frame_this_id (frame_info_ptr this_frame, void **this_cache, } static struct value * -mips_micro_frame_prev_register (frame_info_ptr this_frame, - void **this_cache, int regnum) +mips_micro_frame_prev_register (frame_info_ptr this_frame, void **this_cache, + int regnum) { - struct mips_frame_cache *info = mips_micro_frame_cache (this_frame, - this_cache); + struct mips_frame_cache *info + = mips_micro_frame_cache (this_frame, this_cache); return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); } @@ -3358,33 +3337,26 @@ mips_micro_frame_sniffer (const struct frame_unwind *self, return 0; } -static const struct frame_unwind mips_micro_frame_unwind = -{ - "mips micro prologue", - NORMAL_FRAME, - default_frame_unwind_stop_reason, - mips_micro_frame_this_id, - mips_micro_frame_prev_register, - NULL, - mips_micro_frame_sniffer -}; +static const struct frame_unwind mips_micro_frame_unwind + = { "mips micro prologue", + NORMAL_FRAME, + default_frame_unwind_stop_reason, + mips_micro_frame_this_id, + mips_micro_frame_prev_register, + NULL, + mips_micro_frame_sniffer }; static CORE_ADDR -mips_micro_frame_base_address (frame_info_ptr this_frame, - void **this_cache) +mips_micro_frame_base_address (frame_info_ptr this_frame, void **this_cache) { - struct mips_frame_cache *info = mips_micro_frame_cache (this_frame, - this_cache); + struct mips_frame_cache *info + = mips_micro_frame_cache (this_frame, this_cache); return info->base; } -static const struct frame_base mips_micro_frame_base = -{ - &mips_micro_frame_unwind, - mips_micro_frame_base_address, - mips_micro_frame_base_address, - mips_micro_frame_base_address -}; +static const struct frame_base mips_micro_frame_base + = { &mips_micro_frame_unwind, mips_micro_frame_base_address, + mips_micro_frame_base_address, mips_micro_frame_base_address }; static const struct frame_base * mips_micro_frame_base_sniffer (frame_info_ptr this_frame) @@ -3423,9 +3395,8 @@ reset_saved_regs (struct gdbarch *gdbarch, struct mips_frame_cache *this_cache) Return the address of the first instruction past the prologue. */ static CORE_ADDR -mips32_scan_prologue (struct gdbarch *gdbarch, - CORE_ADDR start_pc, CORE_ADDR limit_pc, - frame_info_ptr this_frame, +mips32_scan_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc, + CORE_ADDR limit_pc, frame_info_ptr this_frame, struct mips_frame_cache *this_cache) { int prev_non_prologue_insn; @@ -3438,7 +3409,7 @@ mips32_scan_prologue (struct gdbarch *gdbarch, CORE_ADDR cur_pc; CORE_ADDR sp; long frame_offset; - int frame_reg = MIPS_SP_REGNUM; + int frame_reg = MIPS_SP_REGNUM; CORE_ADDR end_prologue_addr; int seen_sp_adjust = 0; @@ -3449,9 +3420,8 @@ mips32_scan_prologue (struct gdbarch *gdbarch, /* Can be called when there's no process, and hence when there's no THIS_FRAME. */ if (this_frame != NULL) - sp = get_frame_register_signed (this_frame, - gdbarch_num_regs (gdbarch) - + MIPS_SP_REGNUM); + sp = get_frame_register_signed (this_frame, gdbarch_num_regs (gdbarch) + + MIPS_SP_REGNUM); else sp = 0; @@ -3478,19 +3448,19 @@ restart: in_delay_slot = 0; /* Fetch the instruction. */ - inst = (unsigned long) mips_fetch_instruction (gdbarch, ISA_MIPS, - cur_pc, NULL); + inst = (unsigned long) mips_fetch_instruction (gdbarch, ISA_MIPS, cur_pc, + NULL); /* Save some code by pre-extracting some useful fields. */ high_word = (inst >> 16) & 0xffff; offset = ((inst & 0xffff) ^ 0x8000) - 0x8000; reg = high_word & 0x1f; - if (high_word == 0x27bd /* addiu $sp,$sp,-i */ - || high_word == 0x23bd /* addi $sp,$sp,-i */ - || high_word == 0x67bd) /* daddiu $sp,$sp,-i */ + if (high_word == 0x27bd /* addiu $sp,$sp,-i */ + || high_word == 0x23bd /* addi $sp,$sp,-i */ + || high_word == 0x67bd) /* daddiu $sp,$sp,-i */ { - if (offset < 0) /* Negative stack adjustment? */ + if (offset < 0) /* Negative stack adjustment? */ frame_offset -= offset; else /* Exit loop if a positive stack adjustment is found, which @@ -3504,13 +3474,13 @@ restart: { set_reg_offset (gdbarch, this_cache, reg, sp + offset); } - else if (((high_word & 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */ + else if (((high_word & 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */ && regsize_is_64_bits) { /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */ set_reg_offset (gdbarch, this_cache, reg, sp + offset); } - else if (high_word == 0x27be) /* addiu $30,$sp,size */ + else if (high_word == 0x27be) /* addiu $30,$sp,size */ { /* Old gcc frame, r30 is virtual frame pointer. */ if (offset != frame_offset) @@ -3520,8 +3490,9 @@ restart: unsigned alloca_adjust; frame_reg = 30; - frame_addr = get_frame_register_signed - (this_frame, gdbarch_num_regs (gdbarch) + 30); + frame_addr + = get_frame_register_signed (this_frame, + gdbarch_num_regs (gdbarch) + 30); frame_offset = 0; alloca_adjust = (unsigned) (frame_addr - (sp + offset)); @@ -3551,8 +3522,9 @@ restart: unsigned alloca_adjust; frame_reg = 30; - frame_addr = get_frame_register_signed - (this_frame, gdbarch_num_regs (gdbarch) + 30); + frame_addr + = get_frame_register_signed (this_frame, + gdbarch_num_regs (gdbarch) + 30); alloca_adjust = (unsigned) (frame_addr - sp); if (alloca_adjust > 0) @@ -3570,22 +3542,22 @@ restart: } } } - else if ((high_word & 0xFFE0) == 0xafc0 /* sw reg,offset($30) */ + else if ((high_word & 0xFFE0) == 0xafc0 /* sw reg,offset($30) */ && !regsize_is_64_bits) { set_reg_offset (gdbarch, this_cache, reg, frame_addr + offset); } - else if ((high_word & 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */ - || (high_word & 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */ + else if ((high_word & 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */ + || (high_word & 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */ || (inst & 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */ - || high_word == 0x3c1c /* lui $gp,n */ - || high_word == 0x279c /* addiu $gp,$gp,n */ - || high_word == 0x679c /* daddiu $gp,$gp,n */ - || inst == 0x0399e021 /* addu $gp,$gp,$t9 */ - || inst == 0x033ce021 /* addu $gp,$t9,$gp */ - || inst == 0x0399e02d /* daddu $gp,$gp,$t9 */ - || inst == 0x033ce02d /* daddu $gp,$t9,$gp */ - ) + || high_word == 0x3c1c /* lui $gp,n */ + || high_word == 0x279c /* addiu $gp,$gp,n */ + || high_word == 0x679c /* daddiu $gp,$gp,n */ + || inst == 0x0399e021 /* addu $gp,$gp,$t9 */ + || inst == 0x033ce021 /* addu $gp,$t9,$gp */ + || inst == 0x0399e02d /* daddu $gp,$gp,$t9 */ + || inst == 0x033ce02d /* daddu $gp,$t9,$gp */ + ) { /* These instructions are part of the prologue, but we don't need to do anything special to handle them. */ @@ -3595,17 +3567,16 @@ restart: subu $sp,$sp,[$at,$t0]. These instructions could also initialize a local variable, so we accept them only before a stack adjustment instruction was seen. */ - else if (!seen_sp_adjust - && !prev_delay_slot - && (high_word == 0x3c01 /* lui $at,n */ + else if (!seen_sp_adjust && !prev_delay_slot + && (high_word == 0x3c01 /* lui $at,n */ || high_word == 0x3c08 /* lui $t0,n */ || high_word == 0x3421 /* ori $at,$at,n */ || high_word == 0x3508 /* ori $t0,$t0,n */ || high_word == 0x3401 /* ori $at,$zero,n */ || high_word == 0x3408 /* ori $t0,$zero,n */ - )) + )) { - load_immediate_bytes += MIPS_INSN32_SIZE; /* FIXME! */ + load_immediate_bytes += MIPS_INSN32_SIZE; /* FIXME! */ } /* Check for branches and jumps. The instruction in the delay slot can be a part of the prologue, so move forward once more. */ @@ -3635,17 +3606,16 @@ restart: if (this_cache != NULL) { - this_cache->base = - (get_frame_register_signed (this_frame, - gdbarch_num_regs (gdbarch) + frame_reg) - + frame_offset); + this_cache->base + = (get_frame_register_signed (this_frame, + gdbarch_num_regs (gdbarch) + frame_reg) + + frame_offset); /* FIXME: brobecker/2004-09-15: We should be able to get rid of this assignment below, eventually. But it's still needed for now. */ - this_cache->saved_regs[gdbarch_num_regs (gdbarch) - + mips_regnum (gdbarch)->pc] - = this_cache->saved_regs[gdbarch_num_regs (gdbarch) - + MIPS_RA_REGNUM]; + this_cache + ->saved_regs[gdbarch_num_regs (gdbarch) + mips_regnum (gdbarch)->pc] + = this_cache->saved_regs[gdbarch_num_regs (gdbarch) + MIPS_RA_REGNUM]; } /* Set end_prologue_addr to the address of the instruction immediately @@ -3654,7 +3624,7 @@ restart: its address instead. */ end_prologue_addr = prev_non_prologue_insn || prev_delay_slot ? prev_pc : cur_pc; - + /* In a frameless function, we might have incorrectly skipped some load immediate instructions. Undo the skipping if the load immediate was not followed by a stack adjustment. */ @@ -3698,10 +3668,10 @@ mips_insn32_frame_cache (frame_info_ptr this_frame, void **this_cache) mips32_scan_prologue (gdbarch, start_addr, pc, this_frame, (struct mips_frame_cache *) *this_cache); } - + /* gdbarch_sp_regnum contains the value and not the address. */ - cache->saved_regs[gdbarch_num_regs (gdbarch) - + MIPS_SP_REGNUM].set_value (cache->base); + cache->saved_regs[gdbarch_num_regs (gdbarch) + MIPS_SP_REGNUM].set_value ( + cache->base); return (struct mips_frame_cache *) (*this_cache); } @@ -3710,8 +3680,8 @@ static void mips_insn32_frame_this_id (frame_info_ptr this_frame, void **this_cache, struct frame_id *this_id) { - struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame, - this_cache); + struct mips_frame_cache *info + = mips_insn32_frame_cache (this_frame, this_cache); /* This marks the outermost frame. */ if (info->base == 0) return; @@ -3719,11 +3689,11 @@ mips_insn32_frame_this_id (frame_info_ptr this_frame, void **this_cache, } static struct value * -mips_insn32_frame_prev_register (frame_info_ptr this_frame, - void **this_cache, int regnum) +mips_insn32_frame_prev_register (frame_info_ptr this_frame, void **this_cache, + int regnum) { - struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame, - this_cache); + struct mips_frame_cache *info + = mips_insn32_frame_cache (this_frame, this_cache); return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum); } @@ -3737,33 +3707,23 @@ mips_insn32_frame_sniffer (const struct frame_unwind *self, return 0; } -static const struct frame_unwind mips_insn32_frame_unwind = -{ - "mips insn32 prologue", - NORMAL_FRAME, - default_frame_unwind_stop_reason, - mips_insn32_frame_this_id, - mips_insn32_frame_prev_register, - NULL, - mips_insn32_frame_sniffer -}; +static const struct frame_unwind mips_insn32_frame_unwind + = { "mips insn32 prologue", NORMAL_FRAME, + default_frame_unwind_stop_reason, mips_insn32_frame_this_id, + mips_insn32_frame_prev_register, NULL, + mips_insn32_frame_sniffer }; static CORE_ADDR -mips_insn32_frame_base_address (frame_info_ptr this_frame, - void **this_cache) +mips_insn32_frame_base_address (frame_info_ptr this_frame, void **this_cache) { - struct mips_frame_cache *info = mips_insn32_frame_cache (this_frame, - this_cache); + struct mips_frame_cache *info + = mips_insn32_frame_cache (this_frame, this_cache); return info->base; } -static const struct frame_base mips_insn32_frame_base = -{ - &mips_insn32_frame_unwind, - mips_insn32_frame_base_address, - mips_insn32_frame_base_address, - mips_insn32_frame_base_address -}; +static const struct frame_base mips_insn32_frame_base + = { &mips_insn32_frame_unwind, mips_insn32_frame_base_address, + mips_insn32_frame_base_address, mips_insn32_frame_base_address }; static const struct frame_base * mips_insn32_frame_base_sniffer (frame_info_ptr this_frame) @@ -3791,16 +3751,15 @@ mips_stub_frame_cache (frame_info_ptr this_frame, void **this_cache) (*this_cache) = this_trad_cache; /* The return address is in the link register. */ - trad_frame_set_reg_realreg (this_trad_cache, - gdbarch_pc_regnum (gdbarch), + trad_frame_set_reg_realreg (this_trad_cache, gdbarch_pc_regnum (gdbarch), num_regs + MIPS_RA_REGNUM); /* Frame ID, since it's a frameless / stackless function, no stack space is allocated and SP on entry is the current SP. */ pc = get_frame_pc (this_frame); find_pc_partial_function (pc, NULL, &start_addr, NULL); - stack_addr = get_frame_register_signed (this_frame, - num_regs + MIPS_SP_REGNUM); + stack_addr + = get_frame_register_signed (this_frame, num_regs + MIPS_SP_REGNUM); trad_frame_set_id (this_trad_cache, frame_id_build (stack_addr, start_addr)); /* Assume that the frame's base is the same as the @@ -3820,8 +3779,8 @@ mips_stub_frame_this_id (frame_info_ptr this_frame, void **this_cache, } static struct value * -mips_stub_frame_prev_register (frame_info_ptr this_frame, - void **this_cache, int regnum) +mips_stub_frame_prev_register (frame_info_ptr this_frame, void **this_cache, + int regnum) { struct trad_frame_cache *this_trad_cache = mips_stub_frame_cache (this_frame, this_cache); @@ -3846,41 +3805,33 @@ mips_stub_frame_sniffer (const struct frame_unwind *self, /* Calling a PIC function from a non-PIC function passes through a stub. The stub for foo is named ".pic.foo". */ msym = lookup_minimal_symbol_by_pc (pc); - if (msym.minsym != NULL - && msym.minsym->linkage_name () != NULL + if (msym.minsym != NULL && msym.minsym->linkage_name () != NULL && startswith (msym.minsym->linkage_name (), ".pic.")) return 1; return 0; } -static const struct frame_unwind mips_stub_frame_unwind = -{ - "mips stub", - NORMAL_FRAME, - default_frame_unwind_stop_reason, - mips_stub_frame_this_id, - mips_stub_frame_prev_register, - NULL, - mips_stub_frame_sniffer -}; +static const struct frame_unwind mips_stub_frame_unwind + = { "mips stub", + NORMAL_FRAME, + default_frame_unwind_stop_reason, + mips_stub_frame_this_id, + mips_stub_frame_prev_register, + NULL, + mips_stub_frame_sniffer }; static CORE_ADDR -mips_stub_frame_base_address (frame_info_ptr this_frame, - void **this_cache) +mips_stub_frame_base_address (frame_info_ptr this_frame, void **this_cache) { struct trad_frame_cache *this_trad_cache = mips_stub_frame_cache (this_frame, this_cache); return trad_frame_get_this_base (this_trad_cache); } -static const struct frame_base mips_stub_frame_base = -{ - &mips_stub_frame_unwind, - mips_stub_frame_base_address, - mips_stub_frame_base_address, - mips_stub_frame_base_address -}; +static const struct frame_base mips_stub_frame_base + = { &mips_stub_frame_unwind, mips_stub_frame_base_address, + mips_stub_frame_base_address, mips_stub_frame_base_address }; static const struct frame_base * mips_stub_frame_base_sniffer (frame_info_ptr this_frame) @@ -3919,7 +3870,6 @@ mips_addr_bits_remove (struct gdbarch *gdbarch, CORE_ADDR addr) return addr; } - /* Checks for an atomic sequence of instructions beginning with a LL/LLD instruction and ending with a SC/SCD instruction. If such a sequence is found, attempt to step through it. A breakpoint is placed at the end of @@ -3935,13 +3885,13 @@ mips_addr_bits_remove (struct gdbarch *gdbarch, CORE_ADDR addr) static std::vector<CORE_ADDR> mips_deal_with_atomic_sequence (struct gdbarch *gdbarch, CORE_ADDR pc) { - CORE_ADDR breaks[2] = {CORE_ADDR_MAX, CORE_ADDR_MAX}; + CORE_ADDR breaks[2] = { CORE_ADDR_MAX, CORE_ADDR_MAX }; CORE_ADDR loc = pc; CORE_ADDR branch_bp; /* Breakpoint at branch instruction's destination. */ ULONGEST insn; int insn_count; int index; - int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */ + int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */ const int atomic_sequence_length = 16; /* Instruction sequence length. */ insn = mips_fetch_instruction (gdbarch, ISA_MIPS, loc, NULL); @@ -3962,26 +3912,26 @@ mips_deal_with_atomic_sequence (struct gdbarch *gdbarch, CORE_ADDR pc) destination address. */ switch (itype_op (insn)) { - case 0: /* SPECIAL */ + case 0: /* SPECIAL */ if (rtype_funct (insn) >> 1 == 4) /* JR, JALR */ return {}; /* fallback to the standard single-step code. */ break; - case 1: /* REGIMM */ + case 1: /* REGIMM */ is_branch = ((itype_rt (insn) & 0xc) == 0 /* B{LT,GE}Z* */ || ((itype_rt (insn) & 0x1e) == 0 && itype_rs (insn) == 0)); /* BPOSGE* */ break; - case 2: /* J */ - case 3: /* JAL */ + case 2: /* J */ + case 3: /* JAL */ return {}; /* fallback to the standard single-step code. */ - case 4: /* BEQ */ - case 5: /* BNE */ - case 6: /* BLEZ */ - case 7: /* BGTZ */ - case 20: /* BEQL */ - case 21: /* BNEL */ - case 22: /* BLEZL */ - case 23: /* BGTTL */ + case 4: /* BEQ */ + case 5: /* BNE */ + case 6: /* BLEZ */ + case 7: /* BGTZ */ + case 20: /* BEQL */ + case 21: /* BNEL */ + case 22: /* BLEZL */ + case 23: /* BGTTL */ is_branch = 1; break; case 17: /* COP1 */ @@ -3990,8 +3940,8 @@ mips_deal_with_atomic_sequence (struct gdbarch *gdbarch, CORE_ADDR pc) if (is_branch) /* BC1ANY2F, BC1ANY2T, BC1ANY4F, BC1ANY4T */ break; /* Fall through. */ - case 18: /* COP2 */ - case 19: /* COP3 */ + case 18: /* COP2 */ + case 19: /* COP3 */ is_branch = (itype_rs (insn) == 8); /* BCzF, BCzFL, BCzT, BCzTL */ break; } @@ -4033,12 +3983,11 @@ mips_deal_with_atomic_sequence (struct gdbarch *gdbarch, CORE_ADDR pc) } static std::vector<CORE_ADDR> -micromips_deal_with_atomic_sequence (struct gdbarch *gdbarch, - CORE_ADDR pc) +micromips_deal_with_atomic_sequence (struct gdbarch *gdbarch, CORE_ADDR pc) { const int atomic_sequence_length = 16; /* Instruction sequence length. */ int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */ - CORE_ADDR breaks[2] = {CORE_ADDR_MAX, CORE_ADDR_MAX}; + CORE_ADDR breaks[2] = { CORE_ADDR_MAX, CORE_ADDR_MAX }; CORE_ADDR branch_bp = 0; /* Breakpoint at branch instruction's destination. */ CORE_ADDR loc = pc; @@ -4049,20 +3998,19 @@ micromips_deal_with_atomic_sequence (struct gdbarch *gdbarch, /* Assume all atomic sequences start with a ll/lld instruction. */ insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, loc, NULL); - if (micromips_op (insn) != 0x18) /* POOL32C: bits 011000 */ + if (micromips_op (insn) != 0x18) /* POOL32C: bits 011000 */ return {}; loc += MIPS_INSN16_SIZE; insn <<= 16; insn |= mips_fetch_instruction (gdbarch, ISA_MICROMIPS, loc, NULL); - if ((b12s4_op (insn) & 0xb) != 0x3) /* LL, LLD: bits 011000 0x11 */ + if ((b12s4_op (insn) & 0xb) != 0x3) /* LL, LLD: bits 011000 0x11 */ return {}; loc += MIPS_INSN16_SIZE; /* Assume all atomic sequences end with an sc/scd instruction. Assume that no atomic sequence is longer than "atomic_sequence_length" instructions. */ - for (insn_count = 0; - !sc_found && insn_count < atomic_sequence_length; + for (insn_count = 0; !sc_found && insn_count < atomic_sequence_length; ++insn_count) { int is_branch = 0; @@ -4081,29 +4029,26 @@ micromips_deal_with_atomic_sequence (struct gdbarch *gdbarch, { case 0x10: /* POOL32I: bits 010000 */ if ((b5s5_op (insn) & 0x18) != 0x0 - /* BLTZ, BLTZAL, BGEZ, BGEZAL: 010000 000xx */ - /* BLEZ, BNEZC, BGTZ, BEQZC: 010000 001xx */ + /* BLTZ, BLTZAL, BGEZ, BGEZAL: 010000 000xx */ + /* BLEZ, BNEZC, BGTZ, BEQZC: 010000 001xx */ && (b5s5_op (insn) & 0x1d) != 0x11 - /* BLTZALS, BGEZALS: bits 010000 100x1 */ - && ((b5s5_op (insn) & 0x1e) != 0x14 - || (insn & 0x3) != 0x0) - /* BC2F, BC2T: bits 010000 1010x xxx00 */ + /* BLTZALS, BGEZALS: bits 010000 100x1 */ + && ((b5s5_op (insn) & 0x1e) != 0x14 || (insn & 0x3) != 0x0) + /* BC2F, BC2T: bits 010000 1010x xxx00 */ && (b5s5_op (insn) & 0x1e) != 0x1a - /* BPOSGE64, BPOSGE32: bits 010000 1101x */ - && ((b5s5_op (insn) & 0x1e) != 0x1c - || (insn & 0x3) != 0x0) - /* BC1F, BC1T: bits 010000 1110x xxx00 */ - && ((b5s5_op (insn) & 0x1c) != 0x1c - || (insn & 0x3) != 0x1)) - /* BC1ANY*: bits 010000 111xx xxx01 */ + /* BPOSGE64, BPOSGE32: bits 010000 1101x */ + && ((b5s5_op (insn) & 0x1e) != 0x1c || (insn & 0x3) != 0x0) + /* BC1F, BC1T: bits 010000 1110x xxx00 */ + && ((b5s5_op (insn) & 0x1c) != 0x1c || (insn & 0x3) != 0x1)) + /* BC1ANY*: bits 010000 111xx xxx01 */ break; /* Fall through. */ case 0x25: /* BEQ: bits 100101 */ case 0x2d: /* BNE: bits 101101 */ insn <<= 16; - insn |= mips_fetch_instruction (gdbarch, - ISA_MICROMIPS, loc, NULL); + insn + |= mips_fetch_instruction (gdbarch, ISA_MICROMIPS, loc, NULL); branch_bp = (loc + MIPS_INSN16_SIZE + micromips_relative_offset16 (insn)); is_branch = 1; @@ -4111,25 +4056,25 @@ micromips_deal_with_atomic_sequence (struct gdbarch *gdbarch, case 0x00: /* POOL32A: bits 000000 */ insn <<= 16; - insn |= mips_fetch_instruction (gdbarch, - ISA_MICROMIPS, loc, NULL); + insn + |= mips_fetch_instruction (gdbarch, ISA_MICROMIPS, loc, NULL); if (b0s6_op (insn) != 0x3c - /* POOL32Axf: bits 000000 ... 111100 */ + /* POOL32Axf: bits 000000 ... 111100 */ || (b6s10_ext (insn) & 0x2bf) != 0x3c) - /* JALR, JALR.HB: 000000 000x111100 111100 */ - /* JALRS, JALRS.HB: 000000 010x111100 111100 */ + /* JALR, JALR.HB: 000000 000x111100 111100 */ + /* JALRS, JALRS.HB: 000000 010x111100 111100 */ break; /* Fall through. */ - case 0x1d: /* JALS: bits 011101 */ - case 0x35: /* J: bits 110101 */ - case 0x3d: /* JAL: bits 111101 */ - case 0x3c: /* JALX: bits 111100 */ + case 0x1d: /* JALS: bits 011101 */ + case 0x35: /* J: bits 110101 */ + case 0x3d: /* JAL: bits 111101 */ + case 0x3c: /* JALX: bits 111100 */ return {}; /* Fall back to the standard single-step code. */ case 0x18: /* POOL32C: bits 011000 */ if ((b12s4_op (insn) & 0xb) == 0xb) - /* SC, SCD: bits 011000 1x11 */ + /* SC, SCD: bits 011000 1x11 */ sc_found = 1; break; } @@ -4148,13 +4093,13 @@ micromips_deal_with_atomic_sequence (struct gdbarch *gdbarch, case 0x11: /* POOL16C: bits 010001 */ if ((b5s5_op (insn) & 0x1c) != 0xc - /* JR16, JRC, JALR16, JALRS16: 010001 011xx */ + /* JR16, JRC, JALR16, JALRS16: 010001 011xx */ && b5s5_op (insn) != 0x18) - /* JRADDIUSP: bits 010001 11000 */ + /* JRADDIUSP: bits 010001 11000 */ break; return {}; /* Fall back to the standard single-step code. */ - case 0x33: /* B16: bits 110011 */ + case 0x33: /* B16: bits 110011 */ return {}; /* Fall back to the standard single-step code. */ } break; @@ -4218,7 +4163,7 @@ mips_software_single_step (struct regcache *regcache) next_pc = mips_next_pc (regcache, pc); - return {next_pc}; + return { next_pc }; } /* Test whether the PC points to the return instruction at the @@ -4236,10 +4181,9 @@ mips_about_to_return (struct gdbarch *gdbarch, CORE_ADDR pc) insn = mips_fetch_instruction (gdbarch, ISA_MIPS, pc, NULL); hint = 0x7c0; - return (insn & ~hint) == 0x3e00008; /* jr(.hb) $ra */ + return (insn & ~hint) == 0x3e00008; /* jr(.hb) $ra */ } - /* This fencepost looks highly suspicious to me. Removing it also seems suspicious as it could affect remote debugging across serial lines. */ @@ -4278,7 +4222,7 @@ heuristic_proc_start (struct gdbarch *gdbarch, CORE_ADDR pc) { static int blurb_printed = 0; - warning (_("GDB can't find the start of the function at %s."), + warning (_ ("GDB can't find the start of the function at %s."), paddress (gdbarch, pc)); if (!blurb_printed) @@ -4320,25 +4264,25 @@ heuristic-fence-post' command.\n", daddiu sp,-n extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n'. */ inst = mips_fetch_instruction (gdbarch, ISA_MIPS16, start_pc, NULL); - if ((inst & 0xff80) == 0x6480) /* save */ + if ((inst & 0xff80) == 0x6480) /* save */ { if (start_pc - instlen >= fence) { inst = mips_fetch_instruction (gdbarch, ISA_MIPS16, start_pc - instlen, NULL); - if ((inst & 0xf800) == 0xf000) /* extend */ + if ((inst & 0xf800) == 0xf000) /* extend */ start_pc -= instlen; } break; } else if (((inst & 0xf81f) == 0xe809 - && (inst & 0x700) != 0x700) /* entry */ - || (inst & 0xff80) == 0x6380 /* addiu sp,-n */ - || (inst & 0xff80) == 0xfb80 /* daddiu sp,-n */ - || ((inst & 0xf810) == 0xf010 && seen_adjsp)) /* extend -n */ + && (inst & 0x700) != 0x700) /* entry */ + || (inst & 0xff80) == 0x6380 /* addiu sp,-n */ + || (inst & 0xff80) == 0xfb80 /* daddiu sp,-n */ + || ((inst & 0xf810) == 0xf010 && seen_adjsp)) /* extend -n */ break; - else if ((inst & 0xff00) == 0x6300 /* addiu sp */ - || (inst & 0xff00) == 0xfb00) /* daddiu sp */ + else if ((inst & 0xff00) == 0x6300 /* addiu sp */ + || (inst & 0xff00) == 0xfb00) /* daddiu sp */ seen_adjsp = 1; else seen_adjsp = 0; @@ -4359,7 +4303,7 @@ heuristic-fence-post' command.\n", insn = mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc, NULL); switch (micromips_op (insn)) { - case 0xc: /* ADDIU: bits 001100 */ + case 0xc: /* ADDIU: bits 001100 */ case 0x17: /* DADDIU: bits 010111 */ sreg = b0s5_reg (insn); dreg = b5s5_reg (insn); @@ -4367,36 +4311,37 @@ heuristic-fence-post' command.\n", insn |= mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc + MIPS_INSN16_SIZE, NULL); offset = (b0s16_imm (insn) ^ 0x8000) - 0x8000; - if (sreg == MIPS_SP_REGNUM && dreg == MIPS_SP_REGNUM - /* (D)ADDIU $sp, imm */ + if (sreg == MIPS_SP_REGNUM + && dreg == MIPS_SP_REGNUM + /* (D)ADDIU $sp, imm */ && offset < 0) stop = 1; break; case 0x10: /* POOL32I: bits 010000 */ if (b5s5_op (insn) == 0xd - /* LUI: bits 010000 001101 */ + /* LUI: bits 010000 001101 */ && b0s5_reg (insn >> 16) == 28) - /* LUI $gp, imm */ + /* LUI $gp, imm */ stop = 1; break; case 0x13: /* POOL16D: bits 010011 */ if ((insn & 0x1) == 0x1) - /* ADDIUSP: bits 010011 1 */ + /* ADDIUSP: bits 010011 1 */ { offset = micromips_decode_imm9 (b1s9_imm (insn)); if (offset < 0) - /* ADDIUSP -imm */ + /* ADDIUSP -imm */ stop = 1; } else - /* ADDIUS5: bits 010011 0 */ + /* ADDIUS5: bits 010011 0 */ { dreg = b5s5_reg (insn); offset = (b1s4_imm (insn) ^ 8) - 8; if (dreg == MIPS_SP_REGNUM && offset < 0) - /* ADDIUS5 $sp, -imm */ + /* ADDIUS5 $sp, -imm */ stop = 1; } break; @@ -4432,11 +4377,10 @@ fp_register_arg_p (struct gdbarch *gdbarch, enum type_code typecode, { return ((typecode == TYPE_CODE_FLT || (mips_eabi (gdbarch) - && (typecode == TYPE_CODE_STRUCT - || typecode == TYPE_CODE_UNION) + && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION) && arg_type->num_fields () == 1 && check_typedef (arg_type->field (0).type ())->code () - == TYPE_CODE_FLT)) + == TYPE_CODE_FLT)) && mips_get_fpu_type (gdbarch) != MIPS_FPU_NONE); } @@ -4480,9 +4424,8 @@ mips_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr) /* Implement the "push_dummy_code" gdbarch method. */ static CORE_ADDR -mips_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, - CORE_ADDR funaddr, struct value **args, - int nargs, struct type *value_type, +mips_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, CORE_ADDR funaddr, + struct value **args, int nargs, struct type *value_type, CORE_ADDR *real_pc, CORE_ADDR *bp_addr, struct regcache *regcache) { @@ -4496,8 +4439,9 @@ mips_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, /* Return to microMIPS mode if calling microMIPS code to avoid triggering an address error exception on processors that only support microMIPS execution. */ - *bp_addr = (mips_pc_is_micromips (gdbarch, funaddr) - ? make_compact_addr (bp_slot) : bp_slot); + *bp_addr + = (mips_pc_is_micromips (gdbarch, funaddr) ? make_compact_addr (bp_slot) + : bp_slot); /* The breakpoint layer automatically adjusts the address of breakpoints inserted in a branch delay slot. With enough @@ -4553,15 +4497,12 @@ mips_eabi_push_dummy_call (struct gdbarch *gdbarch, struct value *function, than necessary for EABI, because the first few arguments are passed in registers, but that's OK. */ for (argnum = 0; argnum < nargs; argnum++) - arg_space += align_up (value_type (args[argnum])->length (), - abi_regsize); + arg_space += align_up (value_type (args[argnum])->length (), abi_regsize); sp -= align_up (arg_space, 16); if (mips_debug) - gdb_printf (gdb_stdlog, - "mips_eabi_push_dummy_call: sp=%s allocated %ld\n", - paddress (gdbarch, sp), - (long) align_up (arg_space, 16)); + gdb_printf (gdb_stdlog, "mips_eabi_push_dummy_call: sp=%s allocated %ld\n", + paddress (gdbarch, sp), (long) align_up (arg_space, 16)); /* Initialize the integer and float register pointers. */ argreg = MIPS_A0_REGNUM; @@ -4593,8 +4534,7 @@ mips_eabi_push_dummy_call (struct gdbarch *gdbarch, struct value *function, enum type_code typecode = arg_type->code (); if (mips_debug) - gdb_printf (gdb_stdlog, - "mips_eabi_push_dummy_call: %d len=%d type=%d", + gdb_printf (gdb_stdlog, "mips_eabi_push_dummy_call: %d len=%d type=%d", argnum + 1, len, (int) typecode); /* The EABI passes structures that do not fit in a register by @@ -4647,24 +4587,24 @@ mips_eabi_push_dummy_call (struct gdbarch *gdbarch, struct value *function, making the ABI determination. */ if (len == 8 && mips_abi (gdbarch) == MIPS_ABI_EABI32) { - int low_offset = gdbarch_byte_order (gdbarch) - == BFD_ENDIAN_BIG ? 4 : 0; + int low_offset + = gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG ? 4 : 0; long regval; /* Write the low word of the double to the even register(s). */ - regval = extract_signed_integer (val + low_offset, - 4, byte_order); + regval + = extract_signed_integer (val + low_offset, 4, byte_order); if (mips_debug) - gdb_printf (gdb_stdlog, " - fpreg=%d val=%s", - float_argreg, phex (regval, 4)); + gdb_printf (gdb_stdlog, " - fpreg=%d val=%s", float_argreg, + phex (regval, 4)); regcache_cooked_write_signed (regcache, float_argreg++, regval); /* Write the high word of the double to the odd register(s). */ - regval = extract_signed_integer (val + 4 - low_offset, - 4, byte_order); + regval + = extract_signed_integer (val + 4 - low_offset, 4, byte_order); if (mips_debug) - gdb_printf (gdb_stdlog, " - fpreg=%d val=%s", - float_argreg, phex (regval, 4)); + gdb_printf (gdb_stdlog, " - fpreg=%d val=%s", float_argreg, + phex (regval, 4)); regcache_cooked_write_signed (regcache, float_argreg++, regval); } else @@ -4675,8 +4615,8 @@ mips_eabi_push_dummy_call (struct gdbarch *gdbarch, struct value *function, above to ensure that it is even register aligned. */ LONGEST regval = extract_signed_integer (val, len, byte_order); if (mips_debug) - gdb_printf (gdb_stdlog, " - fpreg=%d val=%s", - float_argreg, phex (regval, len)); + gdb_printf (gdb_stdlog, " - fpreg=%d val=%s", float_argreg, + phex (regval, len)); regcache_cooked_write_signed (regcache, float_argreg++, regval); } } @@ -4701,12 +4641,10 @@ mips_eabi_push_dummy_call (struct gdbarch *gdbarch, struct value *function, int partial_len = (len < abi_regsize ? len : abi_regsize); if (mips_debug) - gdb_printf (gdb_stdlog, " -- partial=%d", - partial_len); + gdb_printf (gdb_stdlog, " -- partial=%d", partial_len); /* Write this portion of the argument to the stack. */ - if (argreg > mips_last_arg_regnum (gdbarch) - || odd_sized_struct + if (argreg > mips_last_arg_regnum (gdbarch) || odd_sized_struct || fp_register_arg_p (gdbarch, typecode, arg_type)) { /* Should shorter than int integer values be @@ -4719,7 +4657,8 @@ mips_eabi_push_dummy_call (struct gdbarch *gdbarch, struct value *function, if (abi_regsize == 8 && (typecode == TYPE_CODE_INT || typecode == TYPE_CODE_PTR - || typecode == TYPE_CODE_FLT) && len <= 4) + || typecode == TYPE_CODE_FLT) + && len <= 4) longword_offset = abi_regsize - len; else if ((typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION) @@ -4744,8 +4683,7 @@ mips_eabi_push_dummy_call (struct gdbarch *gdbarch, struct value *function, paddress (gdbarch, addr)); for (i = 0; i < partial_len; i++) { - gdb_printf (gdb_stdlog, "%02x", - val[i] & 0xff); + gdb_printf (gdb_stdlog, "%02x", val[i] & 0xff); } } write_memory (addr, val, partial_len); @@ -4759,12 +4697,11 @@ mips_eabi_push_dummy_call (struct gdbarch *gdbarch, struct value *function, if (argreg <= mips_last_arg_regnum (gdbarch) && !fp_register_arg_p (gdbarch, typecode, arg_type)) { - LONGEST regval = - extract_signed_integer (val, partial_len, byte_order); + LONGEST regval + = extract_signed_integer (val, partial_len, byte_order); if (mips_debug) - gdb_printf (gdb_stdlog, " - reg=%d val=%s", - argreg, + gdb_printf (gdb_stdlog, " - reg=%d val=%s", argreg, phex (regval, abi_regsize)); regcache_cooked_write_signed (regcache, argreg, regval); argreg++; @@ -4825,7 +4762,7 @@ mips_eabi_return_value (struct gdbarch *gdbarch, struct value *function, } } - if (fp_return_type) + if (fp_return_type) { /* A floating-point value belongs in the least significant part of FP0/FP1. */ @@ -4833,15 +4770,14 @@ mips_eabi_return_value (struct gdbarch *gdbarch, struct value *function, gdb_printf (gdb_stderr, "Return float in $fp0\n"); regnum = mips_regnum (gdbarch)->fp0; } - else + else { /* An integer value goes in V0/V1. */ if (mips_debug) gdb_printf (gdb_stderr, "Return scalar in $v0\n"); regnum = MIPS_V0_REGNUM; } - for (offset = 0; - offset < type->length (); + for (offset = 0; offset < type->length (); offset += mips_abi_regsize (gdbarch), regnum++) { xfer = mips_abi_regsize (gdbarch); @@ -4856,7 +4792,6 @@ mips_eabi_return_value (struct gdbarch *gdbarch, struct value *function, return RETURN_VALUE_REGISTER_CONVENTION; } - /* N32/N64 ABI stuff. */ /* Search for a naturally aligned double at OFFSET inside a struct @@ -4947,15 +4882,14 @@ mips_n32n64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, /* Now make space on the stack for the args. */ for (argnum = 0; argnum < nargs; argnum++) - arg_space += align_up (value_type (args[argnum])->length (), - MIPS64_REGSIZE); + arg_space + += align_up (value_type (args[argnum])->length (), MIPS64_REGSIZE); sp -= align_up (arg_space, 16); if (mips_debug) gdb_printf (gdb_stdlog, "mips_n32n64_push_dummy_call: sp=%s allocated %ld\n", - paddress (gdbarch, sp), - (long) align_up (arg_space, 16)); + paddress (gdbarch, sp), (long) align_up (arg_space, 16)); /* Initialize the integer and float register pointers. */ argreg = MIPS_A0_REGNUM; @@ -4992,8 +4926,7 @@ mips_n32n64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, /* A 128-bit long double value requires an even-odd pair of floating-point registers. */ - if (len == 16 - && fp_register_arg_p (gdbarch, typecode, arg_type) + if (len == 16 && fp_register_arg_p (gdbarch, typecode, arg_type) && (float_argreg & 1)) { float_argreg++; @@ -5008,28 +4941,28 @@ mips_n32n64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, int reglen = (len <= MIPS64_REGSIZE ? len : MIPS64_REGSIZE); LONGEST regval = extract_unsigned_integer (val, reglen, byte_order); if (mips_debug) - gdb_printf (gdb_stdlog, " - fpreg=%d val=%s", - float_argreg, phex (regval, reglen)); + gdb_printf (gdb_stdlog, " - fpreg=%d val=%s", float_argreg, + phex (regval, reglen)); regcache_cooked_write_unsigned (regcache, float_argreg, regval); if (mips_debug) - gdb_printf (gdb_stdlog, " - reg=%d val=%s", - argreg, phex (regval, reglen)); + gdb_printf (gdb_stdlog, " - reg=%d val=%s", argreg, + phex (regval, reglen)); regcache_cooked_write_unsigned (regcache, argreg, regval); float_argreg++; argreg++; if (len == 16) { - regval = extract_unsigned_integer (val + reglen, - reglen, byte_order); + regval + = extract_unsigned_integer (val + reglen, reglen, byte_order); if (mips_debug) - gdb_printf (gdb_stdlog, " - fpreg=%d val=%s", - float_argreg, phex (regval, reglen)); + gdb_printf (gdb_stdlog, " - fpreg=%d val=%s", float_argreg, + phex (regval, reglen)); regcache_cooked_write_unsigned (regcache, float_argreg, regval); if (mips_debug) - gdb_printf (gdb_stdlog, " - reg=%d val=%s", - argreg, phex (regval, reglen)); + gdb_printf (gdb_stdlog, " - reg=%d val=%s", argreg, + phex (regval, reglen)); regcache_cooked_write_unsigned (regcache, argreg, regval); float_argreg++; argreg++; @@ -5057,8 +4990,7 @@ mips_n32n64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, int partial_len = (len < MIPS64_REGSIZE ? len : MIPS64_REGSIZE); if (mips_debug) - gdb_printf (gdb_stdlog, " -- partial=%d", - partial_len); + gdb_printf (gdb_stdlog, " -- partial=%d", partial_len); if (fp_register_arg_p (gdbarch, typecode, arg_type)) gdb_assert (argreg > mips_last_arg_regnum (gdbarch)); @@ -5096,8 +5028,7 @@ mips_n32n64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, paddress (gdbarch, addr)); for (i = 0; i < partial_len; i++) { - gdb_printf (gdb_stdlog, "%02x", - val[i] & 0xff); + gdb_printf (gdb_stdlog, "%02x", val[i] & 0xff); } } write_memory (addr, val, partial_len); @@ -5118,11 +5049,10 @@ mips_n32n64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, if ((partial_len == 4 && (typecode == TYPE_CODE_PTR || typecode == TYPE_CODE_INT)) - || (partial_len < 4 - && typecode == TYPE_CODE_INT + || (partial_len < 4 && typecode == TYPE_CODE_INT && !arg_type->is_unsigned ())) - regval = extract_signed_integer (val, partial_len, - byte_order); + regval + = extract_signed_integer (val, partial_len, byte_order); else regval = extract_unsigned_integer (val, partial_len, byte_order); @@ -5140,12 +5070,11 @@ mips_n32n64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, && partial_len < MIPS64_REGSIZE && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)) - regval <<= ((MIPS64_REGSIZE - partial_len) - * TARGET_CHAR_BIT); + regval + <<= ((MIPS64_REGSIZE - partial_len) * TARGET_CHAR_BIT); if (mips_debug) - gdb_printf (gdb_stdlog, " - reg=%d val=%s", - argreg, + gdb_printf (gdb_stdlog, " - reg=%d val=%s", argreg, phex (regval, MIPS64_REGSIZE)); regcache_cooked_write_unsigned (regcache, argreg, regval); @@ -5245,13 +5174,12 @@ mips_n32n64_return_value (struct gdbarch *gdbarch, struct value *function, + mips_regnum (gdbarch)->fp0), type->length () / 2, gdbarch_byte_order (gdbarch), readbuf, writebuf, 0); - mips_xfer_register (gdbarch, regcache, - (gdbarch_num_regs (gdbarch) - + mips_regnum (gdbarch)->fp0 + 2), - type->length () / 2, gdbarch_byte_order (gdbarch), - readbuf ? readbuf + type->length () / 2 : readbuf, - (writebuf - ? writebuf + type->length () / 2 : writebuf), 0); + mips_xfer_register ( + gdbarch, regcache, + (gdbarch_num_regs (gdbarch) + mips_regnum (gdbarch)->fp0 + 2), + type->length () / 2, gdbarch_byte_order (gdbarch), + readbuf ? readbuf + type->length () / 2 : readbuf, + (writebuf ? writebuf + type->length () / 2 : writebuf), 0); return RETURN_VALUE_REGISTER_CONVENTION; } else if (type->code () == TYPE_CODE_FLT @@ -5263,13 +5191,11 @@ mips_n32n64_return_value (struct gdbarch *gdbarch, struct value *function, mips_xfer_register (gdbarch, regcache, (gdbarch_num_regs (gdbarch) + mips_regnum (gdbarch)->fp0), - type->length (), - gdbarch_byte_order (gdbarch), + type->length (), gdbarch_byte_order (gdbarch), readbuf, writebuf, 0); return RETURN_VALUE_REGISTER_CONVENTION; } - else if (type->code () == TYPE_CODE_STRUCT - && type->num_fields () <= 2 + else if (type->code () == TYPE_CODE_STRUCT && type->num_fields () <= 2 && type->num_fields () >= 1 && ((type->num_fields () == 1 && (check_typedef (type->field (0).type ())->code () @@ -5286,35 +5212,32 @@ mips_n32n64_return_value (struct gdbarch *gdbarch, struct value *function, int regnum; int field; for (field = 0, regnum = (tdep->mips_fpu_type != MIPS_FPU_NONE - ? mips_regnum (gdbarch)->fp0 - : MIPS_V0_REGNUM); + ? mips_regnum (gdbarch)->fp0 + : MIPS_V0_REGNUM); field < type->num_fields (); field++, regnum += 2) { int offset = type->field (field).loc_bitpos () / TARGET_CHAR_BIT; if (mips_debug) - gdb_printf (gdb_stderr, "Return float struct+%d\n", - offset); + gdb_printf (gdb_stderr, "Return float struct+%d\n", offset); if (type->field (field).type ()->length () == 16) { /* A 16-byte long double field goes in two consecutive registers. */ mips_xfer_register (gdbarch, regcache, - gdbarch_num_regs (gdbarch) + regnum, - 8, - gdbarch_byte_order (gdbarch), - readbuf, writebuf, offset); + gdbarch_num_regs (gdbarch) + regnum, 8, + gdbarch_byte_order (gdbarch), readbuf, + writebuf, offset); mips_xfer_register (gdbarch, regcache, - gdbarch_num_regs (gdbarch) + regnum + 1, - 8, - gdbarch_byte_order (gdbarch), - readbuf, writebuf, offset + 8); + gdbarch_num_regs (gdbarch) + regnum + 1, 8, + gdbarch_byte_order (gdbarch), readbuf, + writebuf, offset + 8); } else mips_xfer_register (gdbarch, regcache, gdbarch_num_regs (gdbarch) + regnum, type->field (field).type ()->length (), - gdbarch_byte_order (gdbarch), - readbuf, writebuf, offset); + gdbarch_byte_order (gdbarch), readbuf, + writebuf, offset); } return RETURN_VALUE_REGISTER_CONVENTION; } @@ -5327,20 +5250,18 @@ mips_n32n64_return_value (struct gdbarch *gdbarch, struct value *function, mips_xfer_lower. */ int offset; int regnum; - for (offset = 0, regnum = MIPS_V0_REGNUM; - offset < type->length (); + for (offset = 0, regnum = MIPS_V0_REGNUM; offset < type->length (); offset += register_size (gdbarch, regnum), regnum++) { int xfer = register_size (gdbarch, regnum); if (offset + xfer > type->length ()) xfer = type->length () - offset; if (mips_debug) - gdb_printf (gdb_stderr, "Return struct+%d:%d in $%d\n", - offset, xfer, regnum); + gdb_printf (gdb_stderr, "Return struct+%d:%d in $%d\n", offset, + xfer, regnum); mips_xfer_register (gdbarch, regcache, - gdbarch_num_regs (gdbarch) + regnum, - xfer, BFD_ENDIAN_UNKNOWN, readbuf, writebuf, - offset); + gdbarch_num_regs (gdbarch) + regnum, xfer, + BFD_ENDIAN_UNKNOWN, readbuf, writebuf, offset); } return RETURN_VALUE_REGISTER_CONVENTION; } @@ -5350,20 +5271,19 @@ mips_n32n64_return_value (struct gdbarch *gdbarch, struct value *function, justified. */ int offset; int regnum; - for (offset = 0, regnum = MIPS_V0_REGNUM; - offset < type->length (); + for (offset = 0, regnum = MIPS_V0_REGNUM; offset < type->length (); offset += register_size (gdbarch, regnum), regnum++) { int xfer = register_size (gdbarch, regnum); if (offset + xfer > type->length ()) xfer = type->length () - offset; if (mips_debug) - gdb_printf (gdb_stderr, "Return scalar+%d:%d in $%d\n", - offset, xfer, regnum); + gdb_printf (gdb_stderr, "Return scalar+%d:%d in $%d\n", offset, + xfer, regnum); mips_xfer_register (gdbarch, regcache, - gdbarch_num_regs (gdbarch) + regnum, - xfer, gdbarch_byte_order (gdbarch), - readbuf, writebuf, offset); + gdbarch_num_regs (gdbarch) + regnum, xfer, + gdbarch_byte_order (gdbarch), readbuf, writebuf, + offset); } return RETURN_VALUE_REGISTER_CONVENTION; } @@ -5431,10 +5351,8 @@ mips_o32_push_dummy_call (struct gdbarch *gdbarch, struct value *function, sp -= align_up (arg_space, 16); if (mips_debug) - gdb_printf (gdb_stdlog, - "mips_o32_push_dummy_call: sp=%s allocated %ld\n", - paddress (gdbarch, sp), - (long) align_up (arg_space, 16)); + gdb_printf (gdb_stdlog, "mips_o32_push_dummy_call: sp=%s allocated %ld\n", + paddress (gdbarch, sp), (long) align_up (arg_space, 16)); /* Initialize the integer and float register pointers. */ argreg = MIPS_A0_REGNUM; @@ -5464,8 +5382,7 @@ mips_o32_push_dummy_call (struct gdbarch *gdbarch, struct value *function, enum type_code typecode = arg_type->code (); if (mips_debug) - gdb_printf (gdb_stdlog, - "mips_o32_push_dummy_call: %d len=%d type=%d", + gdb_printf (gdb_stdlog, "mips_o32_push_dummy_call: %d len=%d type=%d", argnum + 1, len, (int) typecode); val = value_contents (arg).data (); @@ -5497,36 +5414,34 @@ mips_o32_push_dummy_call (struct gdbarch *gdbarch, struct value *function, { if (register_size (gdbarch, float_argreg) < 8 && len == 8) { - int freg_offset = gdbarch_byte_order (gdbarch) - == BFD_ENDIAN_BIG ? 1 : 0; + int freg_offset + = gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG ? 1 : 0; unsigned long regval; /* First word. */ regval = extract_unsigned_integer (val, 4, byte_order); if (mips_debug) gdb_printf (gdb_stdlog, " - fpreg=%d val=%s", - float_argreg + freg_offset, - phex (regval, 4)); + float_argreg + freg_offset, phex (regval, 4)); regcache_cooked_write_unsigned (regcache, float_argreg++ + freg_offset, regval); if (mips_debug) - gdb_printf (gdb_stdlog, " - reg=%d val=%s", - argreg, phex (regval, 4)); + gdb_printf (gdb_stdlog, " - reg=%d val=%s", argreg, + phex (regval, 4)); regcache_cooked_write_unsigned (regcache, argreg++, regval); /* Second word. */ regval = extract_unsigned_integer (val + 4, 4, byte_order); if (mips_debug) gdb_printf (gdb_stdlog, " - fpreg=%d val=%s", - float_argreg - freg_offset, - phex (regval, 4)); + float_argreg - freg_offset, phex (regval, 4)); regcache_cooked_write_unsigned (regcache, float_argreg++ - freg_offset, regval); if (mips_debug) - gdb_printf (gdb_stdlog, " - reg=%d val=%s", - argreg, phex (regval, 4)); + gdb_printf (gdb_stdlog, " - reg=%d val=%s", argreg, + phex (regval, 4)); regcache_cooked_write_unsigned (regcache, argreg++, regval); } else @@ -5537,16 +5452,16 @@ mips_o32_push_dummy_call (struct gdbarch *gdbarch, struct value *function, above to ensure that it is even register aligned. */ LONGEST regval = extract_unsigned_integer (val, len, byte_order); if (mips_debug) - gdb_printf (gdb_stdlog, " - fpreg=%d val=%s", - float_argreg, phex (regval, len)); - regcache_cooked_write_unsigned (regcache, - float_argreg++, regval); + gdb_printf (gdb_stdlog, " - fpreg=%d val=%s", float_argreg, + phex (regval, len)); + regcache_cooked_write_unsigned (regcache, float_argreg++, + regval); /* Although two FP registers are reserved for each argument, only one corresponding integer register is reserved. */ if (mips_debug) - gdb_printf (gdb_stdlog, " - reg=%d val=%s", - argreg, phex (regval, len)); + gdb_printf (gdb_stdlog, " - reg=%d val=%s", argreg, + phex (regval, len)); regcache_cooked_write_unsigned (regcache, argreg++, regval); } /* Reserve space for the FP register. */ @@ -5562,8 +5477,8 @@ mips_o32_push_dummy_call (struct gdbarch *gdbarch, struct value *function, them in registers where gcc sometimes puts them on the stack. For maximum compatibility, we will put them in both places. */ - int odd_sized_struct = (len > MIPS32_REGSIZE - && len % MIPS32_REGSIZE != 0); + int odd_sized_struct + = (len > MIPS32_REGSIZE && len % MIPS32_REGSIZE != 0); /* Structures should be aligned to eight bytes (even arg registers) on MIPS_ABI_O32, if their first member has double precision. */ if (mips_type_needs_double_align (arg_type)) @@ -5579,12 +5494,10 @@ mips_o32_push_dummy_call (struct gdbarch *gdbarch, struct value *function, int partial_len = (len < MIPS32_REGSIZE ? len : MIPS32_REGSIZE); if (mips_debug) - gdb_printf (gdb_stdlog, " -- partial=%d", - partial_len); + gdb_printf (gdb_stdlog, " -- partial=%d", partial_len); /* Write this portion of the argument to the stack. */ - if (argreg > mips_last_arg_regnum (gdbarch) - || odd_sized_struct) + if (argreg > mips_last_arg_regnum (gdbarch) || odd_sized_struct) { /* Should shorter than int integer values be promoted to int before being stored? */ @@ -5608,8 +5521,7 @@ mips_o32_push_dummy_call (struct gdbarch *gdbarch, struct value *function, paddress (gdbarch, addr)); for (i = 0; i < partial_len; i++) { - gdb_printf (gdb_stdlog, "%02x", - val[i] & 0xff); + gdb_printf (gdb_stdlog, "%02x", val[i] & 0xff); } } write_memory (addr, val, partial_len); @@ -5621,8 +5533,8 @@ mips_o32_push_dummy_call (struct gdbarch *gdbarch, struct value *function, purpose register. */ if (argreg <= mips_last_arg_regnum (gdbarch)) { - LONGEST regval = extract_signed_integer (val, partial_len, - byte_order); + LONGEST regval + = extract_signed_integer (val, partial_len, byte_order); /* Value may need to be sign extended, because mips_isa_regsize() != mips_abi_regsize(). */ @@ -5655,12 +5567,11 @@ mips_o32_push_dummy_call (struct gdbarch *gdbarch, struct value *function, && partial_len < MIPS32_REGSIZE && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)) - regval <<= ((MIPS32_REGSIZE - partial_len) - * TARGET_CHAR_BIT); + regval + <<= ((MIPS32_REGSIZE - partial_len) * TARGET_CHAR_BIT); if (mips_debug) - gdb_printf (gdb_stdlog, " - reg=%d val=%s", - argreg, + gdb_printf (gdb_stdlog, " - reg=%d val=%s", argreg, phex (regval, MIPS32_REGSIZE)); regcache_cooked_write_unsigned (regcache, argreg, regval); argreg++; @@ -5705,12 +5616,11 @@ mips_o32_return_value (struct gdbarch *gdbarch, struct value *function, enum mips_fval_reg fval_reg; fval_reg = readbuf ? mips16 ? mips_fval_gpr : mips_fval_fpr : mips_fval_both; - if (type->code () == TYPE_CODE_STRUCT - || type->code () == TYPE_CODE_UNION + if (type->code () == TYPE_CODE_STRUCT || type->code () == TYPE_CODE_UNION || type->code () == TYPE_CODE_ARRAY) return RETURN_VALUE_STRUCT_CONVENTION; - else if (type->code () == TYPE_CODE_FLT - && type->length () == 4 && tdep->mips_fpu_type != MIPS_FPU_NONE) + else if (type->code () == TYPE_CODE_FLT && type->length () == 4 + && tdep->mips_fpu_type != MIPS_FPU_NONE) { /* A single-precision floating-point value. If reading in or copying, then we get it from/put it to FP0 for standard MIPS code or GPR2 @@ -5735,19 +5645,16 @@ mips_o32_return_value (struct gdbarch *gdbarch, struct value *function, mips_xfer_register (gdbarch, regcache, (gdbarch_num_regs (gdbarch) + mips_regnum (gdbarch)->fp0), - type->length (), - gdbarch_byte_order (gdbarch), + type->length (), gdbarch_byte_order (gdbarch), readbuf, writebuf, 0); if (fval_reg != mips_fval_fpr) - mips_xfer_register (gdbarch, regcache, - gdbarch_num_regs (gdbarch) + 2, - type->length (), - gdbarch_byte_order (gdbarch), + mips_xfer_register (gdbarch, regcache, gdbarch_num_regs (gdbarch) + 2, + type->length (), gdbarch_byte_order (gdbarch), readbuf, writebuf, 0); return RETURN_VALUE_REGISTER_CONVENTION; } - else if (type->code () == TYPE_CODE_FLT - && type->length () == 8 && tdep->mips_fpu_type != MIPS_FPU_NONE) + else if (type->code () == TYPE_CODE_FLT && type->length () == 8 + && tdep->mips_fpu_type != MIPS_FPU_NONE) { /* A double-precision floating-point value. If reading in or copying, then we get it from/put it to FP1 and FP0 for standard MIPS code or @@ -5766,8 +5673,7 @@ mips_o32_return_value (struct gdbarch *gdbarch, struct value *function, gdb_printf (gdb_stderr, "Return float in $2/$3\n"); break; case mips_fval_both: - gdb_printf (gdb_stderr, - "Return float in $fp1/$fp0 and $2/$3\n"); + gdb_printf (gdb_stderr, "Return float in $fp1/$fp0 and $2/$3\n"); break; } if (fval_reg != mips_fval_gpr) @@ -5780,28 +5686,28 @@ mips_o32_return_value (struct gdbarch *gdbarch, struct value *function, mips_xfer_register (gdbarch, regcache, (gdbarch_num_regs (gdbarch) + mips_regnum (gdbarch)->fp0 + 0), - 4, gdbarch_byte_order (gdbarch), - readbuf, writebuf, 0); + 4, gdbarch_byte_order (gdbarch), readbuf, + writebuf, 0); mips_xfer_register (gdbarch, regcache, (gdbarch_num_regs (gdbarch) + mips_regnum (gdbarch)->fp0 + 1), - 4, gdbarch_byte_order (gdbarch), - readbuf, writebuf, 4); + 4, gdbarch_byte_order (gdbarch), readbuf, + writebuf, 4); break; case BFD_ENDIAN_BIG: mips_xfer_register (gdbarch, regcache, (gdbarch_num_regs (gdbarch) + mips_regnum (gdbarch)->fp0 + 1), - 4, gdbarch_byte_order (gdbarch), - readbuf, writebuf, 0); + 4, gdbarch_byte_order (gdbarch), readbuf, + writebuf, 0); mips_xfer_register (gdbarch, regcache, (gdbarch_num_regs (gdbarch) + mips_regnum (gdbarch)->fp0 + 0), - 4, gdbarch_byte_order (gdbarch), - readbuf, writebuf, 4); + 4, gdbarch_byte_order (gdbarch), readbuf, + writebuf, 4); break; default: - internal_error (_("bad switch")); + internal_error (_ ("bad switch")); } } if (fval_reg != mips_fval_fpr) @@ -5809,13 +5715,13 @@ mips_o32_return_value (struct gdbarch *gdbarch, struct value *function, /* The two 32-bit parts are always placed in GPR2 and GPR3 following these registers' memory order. */ mips_xfer_register (gdbarch, regcache, - gdbarch_num_regs (gdbarch) + 2, - 4, gdbarch_byte_order (gdbarch), - readbuf, writebuf, 0); + gdbarch_num_regs (gdbarch) + 2, 4, + gdbarch_byte_order (gdbarch), readbuf, writebuf, + 0); mips_xfer_register (gdbarch, regcache, - gdbarch_num_regs (gdbarch) + 3, - 4, gdbarch_byte_order (gdbarch), - readbuf, writebuf, 4); + gdbarch_num_regs (gdbarch) + 3, 4, + gdbarch_byte_order (gdbarch), readbuf, writebuf, + 4); } return RETURN_VALUE_REGISTER_CONVENTION; } @@ -5887,20 +5793,19 @@ mips_o32_return_value (struct gdbarch *gdbarch, struct value *function, the ISA. */ int offset; int regnum; - for (offset = 0, regnum = MIPS_V0_REGNUM; - offset < type->length (); + for (offset = 0, regnum = MIPS_V0_REGNUM; offset < type->length (); offset += MIPS32_REGSIZE, regnum++) { int xfer = MIPS32_REGSIZE; if (offset + xfer > type->length ()) xfer = type->length () - offset; if (mips_debug) - gdb_printf (gdb_stderr, "Return scalar+%d:%d in $%d\n", - offset, xfer, regnum); + gdb_printf (gdb_stderr, "Return scalar+%d:%d in $%d\n", offset, + xfer, regnum); mips_xfer_register (gdbarch, regcache, gdbarch_num_regs (gdbarch) + regnum, xfer, - gdbarch_byte_order (gdbarch), - readbuf, writebuf, offset); + gdbarch_byte_order (gdbarch), readbuf, writebuf, + offset); } return RETURN_VALUE_REGISTER_CONVENTION; } @@ -5912,9 +5817,9 @@ mips_o32_return_value (struct gdbarch *gdbarch, struct value *function, static CORE_ADDR mips_o64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, struct regcache *regcache, CORE_ADDR bp_addr, - int nargs, - struct value **args, CORE_ADDR sp, - function_call_return_method return_method, CORE_ADDR struct_addr) + int nargs, struct value **args, CORE_ADDR sp, + function_call_return_method return_method, + CORE_ADDR struct_addr) { int argreg; int float_argreg; @@ -5952,10 +5857,8 @@ mips_o64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, sp -= align_up (arg_space, 16); if (mips_debug) - gdb_printf (gdb_stdlog, - "mips_o64_push_dummy_call: sp=%s allocated %ld\n", - paddress (gdbarch, sp), - (long) align_up (arg_space, 16)); + gdb_printf (gdb_stdlog, "mips_o64_push_dummy_call: sp=%s allocated %ld\n", + paddress (gdbarch, sp), (long) align_up (arg_space, 16)); /* Initialize the integer and float register pointers. */ argreg = MIPS_A0_REGNUM; @@ -5985,8 +5888,7 @@ mips_o64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, enum type_code typecode = arg_type->code (); if (mips_debug) - gdb_printf (gdb_stdlog, - "mips_o64_push_dummy_call: %d len=%d type=%d", + gdb_printf (gdb_stdlog, "mips_o64_push_dummy_call: %d len=%d type=%d", argnum + 1, len, (int) typecode); val = value_contents (arg).data (); @@ -6006,12 +5908,12 @@ mips_o64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, { LONGEST regval = extract_unsigned_integer (val, len, byte_order); if (mips_debug) - gdb_printf (gdb_stdlog, " - fpreg=%d val=%s", - float_argreg, phex (regval, len)); + gdb_printf (gdb_stdlog, " - fpreg=%d val=%s", float_argreg, + phex (regval, len)); regcache_cooked_write_unsigned (regcache, float_argreg++, regval); if (mips_debug) - gdb_printf (gdb_stdlog, " - reg=%d val=%s", - argreg, phex (regval, len)); + gdb_printf (gdb_stdlog, " - reg=%d val=%s", argreg, + phex (regval, len)); regcache_cooked_write_unsigned (regcache, argreg, regval); argreg++; /* Reserve space for the FP register. */ @@ -6026,19 +5928,17 @@ mips_o64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, are treated specially: Irix cc passes them in registers where gcc sometimes puts them on the stack. For maximum compatibility, we will put them in both places. */ - int odd_sized_struct = (len > MIPS64_REGSIZE - && len % MIPS64_REGSIZE != 0); + int odd_sized_struct + = (len > MIPS64_REGSIZE && len % MIPS64_REGSIZE != 0); while (len > 0) { int partial_len = (len < MIPS64_REGSIZE ? len : MIPS64_REGSIZE); if (mips_debug) - gdb_printf (gdb_stdlog, " -- partial=%d", - partial_len); + gdb_printf (gdb_stdlog, " -- partial=%d", partial_len); /* Write this portion of the argument to the stack. */ - if (argreg > mips_last_arg_regnum (gdbarch) - || odd_sized_struct) + if (argreg > mips_last_arg_regnum (gdbarch) || odd_sized_struct) { /* Should shorter than int integer values be promoted to int before being stored? */ @@ -6070,8 +5970,7 @@ mips_o64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, paddress (gdbarch, addr)); for (i = 0; i < partial_len; i++) { - gdb_printf (gdb_stdlog, "%02x", - val[i] & 0xff); + gdb_printf (gdb_stdlog, "%02x", val[i] & 0xff); } } write_memory (addr, val, partial_len); @@ -6083,8 +5982,8 @@ mips_o64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, purpose register. */ if (argreg <= mips_last_arg_regnum (gdbarch)) { - LONGEST regval = extract_signed_integer (val, partial_len, - byte_order); + LONGEST regval + = extract_signed_integer (val, partial_len, byte_order); /* Value may need to be sign extended, because mips_isa_regsize() != mips_abi_regsize(). */ @@ -6101,12 +6000,11 @@ mips_o64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, && partial_len < MIPS64_REGSIZE && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)) - regval <<= ((MIPS64_REGSIZE - partial_len) - * TARGET_CHAR_BIT); + regval + <<= ((MIPS64_REGSIZE - partial_len) * TARGET_CHAR_BIT); if (mips_debug) - gdb_printf (gdb_stdlog, " - reg=%d val=%s", - argreg, + gdb_printf (gdb_stdlog, " - reg=%d val=%s", argreg, phex (regval, MIPS64_REGSIZE)); regcache_cooked_write_unsigned (regcache, argreg, regval); argreg++; @@ -6150,8 +6048,7 @@ mips_o64_return_value (struct gdbarch *gdbarch, struct value *function, enum mips_fval_reg fval_reg; fval_reg = readbuf ? mips16 ? mips_fval_gpr : mips_fval_fpr : mips_fval_both; - if (type->code () == TYPE_CODE_STRUCT - || type->code () == TYPE_CODE_UNION + if (type->code () == TYPE_CODE_STRUCT || type->code () == TYPE_CODE_UNION || type->code () == TYPE_CODE_ARRAY) return RETURN_VALUE_STRUCT_CONVENTION; else if (fp_register_arg_p (gdbarch, type->code (), type)) @@ -6179,14 +6076,11 @@ mips_o64_return_value (struct gdbarch *gdbarch, struct value *function, mips_xfer_register (gdbarch, regcache, (gdbarch_num_regs (gdbarch) + mips_regnum (gdbarch)->fp0), - type->length (), - gdbarch_byte_order (gdbarch), + type->length (), gdbarch_byte_order (gdbarch), readbuf, writebuf, 0); if (fval_reg != mips_fval_fpr) - mips_xfer_register (gdbarch, regcache, - gdbarch_num_regs (gdbarch) + 2, - type->length (), - gdbarch_byte_order (gdbarch), + mips_xfer_register (gdbarch, regcache, gdbarch_num_regs (gdbarch) + 2, + type->length (), gdbarch_byte_order (gdbarch), readbuf, writebuf, 0); return RETURN_VALUE_REGISTER_CONVENTION; } @@ -6196,20 +6090,19 @@ mips_o64_return_value (struct gdbarch *gdbarch, struct value *function, justified. */ int offset; int regnum; - for (offset = 0, regnum = MIPS_V0_REGNUM; - offset < type->length (); + for (offset = 0, regnum = MIPS_V0_REGNUM; offset < type->length (); offset += MIPS64_REGSIZE, regnum++) { int xfer = MIPS64_REGSIZE; if (offset + xfer > type->length ()) xfer = type->length () - offset; if (mips_debug) - gdb_printf (gdb_stderr, "Return scalar+%d:%d in $%d\n", - offset, xfer, regnum); + gdb_printf (gdb_stderr, "Return scalar+%d:%d in $%d\n", offset, + xfer, regnum); mips_xfer_register (gdbarch, regcache, - gdbarch_num_regs (gdbarch) + regnum, - xfer, gdbarch_byte_order (gdbarch), - readbuf, writebuf, offset); + gdbarch_num_regs (gdbarch) + regnum, xfer, + gdbarch_byte_order (gdbarch), readbuf, writebuf, + offset); } return RETURN_VALUE_REGISTER_CONVENTION; } @@ -6257,8 +6150,8 @@ mips_read_fp_register_single (frame_info_ptr frame, int regno, gdb_byte *raw_buffer = (gdb_byte *) alloca (raw_size); if (!deprecated_frame_register_read (frame, regno, raw_buffer)) - error (_("can't read register %d (%s)"), - regno, gdbarch_register_name (gdbarch, regno)); + error (_ ("can't read register %d (%s)"), regno, + gdbarch_register_name (gdbarch, regno)); if (raw_size == 8) { /* We have a 64-bit value for this register. Find the low-order @@ -6294,16 +6187,16 @@ mips_read_fp_register_double (frame_info_ptr frame, int regno, /* We have a 64-bit value for this register, and we should use all 64 bits. */ if (!deprecated_frame_register_read (frame, regno, rare_buffer)) - error (_("can't read register %d (%s)"), - regno, gdbarch_register_name (gdbarch, regno)); + error (_ ("can't read register %d (%s)"), regno, + gdbarch_register_name (gdbarch, regno)); } else { int rawnum = regno % gdbarch_num_regs (gdbarch); if ((rawnum - mips_regnum (gdbarch)->fp0) & 1) - internal_error (_("mips_read_fp_register_double: bad access to " - "odd-numbered FP register")); + internal_error (_ ("mips_read_fp_register_double: bad access to " + "odd-numbered FP register")); /* mips_read_fp_register_single will find the correct 32 bits from each register. */ @@ -6321,9 +6214,8 @@ mips_read_fp_register_double (frame_info_ptr frame, int regno, } static void -mips_print_fp_register (struct ui_file *file, frame_info_ptr frame, - int regnum) -{ /* Do values for FP (float) regs. */ +mips_print_fp_register (struct ui_file *file, frame_info_ptr frame, int regnum) +{ /* Do values for FP (float) regs. */ struct gdbarch *gdbarch = get_frame_arch (frame); gdb_byte *raw_buffer; std::string flt_str, dbl_str; @@ -6331,14 +6223,12 @@ mips_print_fp_register (struct ui_file *file, frame_info_ptr frame, const struct type *flt_type = builtin_type (gdbarch)->builtin_float; const struct type *dbl_type = builtin_type (gdbarch)->builtin_double; - raw_buffer - = ((gdb_byte *) - alloca (2 * register_size (gdbarch, mips_regnum (gdbarch)->fp0))); + raw_buffer = ((gdb_byte *) alloca ( + 2 * register_size (gdbarch, mips_regnum (gdbarch)->fp0))); gdb_printf (file, "%s:", gdbarch_register_name (gdbarch, regnum)); gdb_printf (file, "%*s", - 4 - (int) strlen (gdbarch_register_name (gdbarch, regnum)), - ""); + 4 - (int) strlen (gdbarch_register_name (gdbarch, regnum)), ""); if (register_size (gdbarch, regnum) == 4 || mips2_fp_compat (frame)) { @@ -6351,8 +6241,8 @@ mips_print_fp_register (struct ui_file *file, frame_info_ptr frame, get_formatted_print_options (&opts, 'x'); print_scalar_formatted (raw_buffer, - builtin_type (gdbarch)->builtin_uint32, - &opts, 'w', file); + builtin_type (gdbarch)->builtin_uint32, &opts, + 'w', file); gdb_printf (file, " flt: %s", flt_str.c_str ()); @@ -6377,8 +6267,8 @@ mips_print_fp_register (struct ui_file *file, frame_info_ptr frame, get_formatted_print_options (&opts, 'x'); print_scalar_formatted (raw_buffer, - builtin_type (gdbarch)->builtin_uint64, - &opts, 'g', file); + builtin_type (gdbarch)->builtin_uint64, &opts, + 'g', file); gdb_printf (file, " flt: %s", flt_str.c_str ()); gdb_printf (file, " dbl: %s", dbl_str.c_str ()); @@ -6386,8 +6276,7 @@ mips_print_fp_register (struct ui_file *file, frame_info_ptr frame, } static void -mips_print_register (struct ui_file *file, frame_info_ptr frame, - int regnum) +mips_print_register (struct ui_file *file, frame_info_ptr frame, int regnum) { struct gdbarch *gdbarch = get_frame_arch (frame); struct value_print_options opts; @@ -6441,7 +6330,7 @@ print_fpu_flags (struct ui_file *file, int flags) static void mips_print_float_info (struct gdbarch *gdbarch, struct ui_file *file, - frame_info_ptr frame, const char *args) + frame_info_ptr frame, const char *args) { int fcsr = mips_regnum (gdbarch)->fp_control_status; enum mips_fpu_type type = mips_get_fpu_type (gdbarch); @@ -6452,9 +6341,9 @@ mips_print_float_info (struct gdbarch *gdbarch, struct ui_file *file, type = MIPS_FPU_NONE; gdb_printf (file, "fpu type: %s\n", - type == MIPS_FPU_DOUBLE ? "double-precision" + type == MIPS_FPU_DOUBLE ? "double-precision" : type == MIPS_FPU_SINGLE ? "single-precision" - : "none / unused"); + : "none / unused"); if (type == MIPS_FPU_NONE) return; @@ -6480,10 +6369,18 @@ mips_print_float_info (struct gdbarch *gdbarch, struct ui_file *file, gdb_puts ("rounding: ", file); switch (fcs & 3) { - case 0: gdb_puts ("nearest\n", file); break; - case 1: gdb_puts ("zero\n", file); break; - case 2: gdb_puts ("+inf\n", file); break; - case 3: gdb_puts ("-inf\n", file); break; + case 0: + gdb_puts ("nearest\n", file); + break; + case 1: + gdb_puts ("zero\n", file); + break; + case 2: + gdb_puts ("+inf\n", file); + break; + case 3: + gdb_puts ("-inf\n", file); + break; } gdb_puts ("flush :", file); @@ -6508,8 +6405,7 @@ mips_print_float_info (struct gdbarch *gdbarch, struct ui_file *file, Print regs in pretty columns. */ static int -print_fp_register_row (struct ui_file *file, frame_info_ptr frame, - int regnum) +print_fp_register_row (struct ui_file *file, frame_info_ptr frame, int regnum) { gdb_printf (file, " "); mips_print_fp_register (file, frame, regnum); @@ -6517,7 +6413,6 @@ print_fp_register_row (struct ui_file *file, frame_info_ptr frame, return regnum + 1; } - /* Print a row's worth of GP (int) registers, with name labels above. */ static int @@ -6528,25 +6423,24 @@ print_gp_register_row (struct ui_file *file, frame_info_ptr frame, /* Do values for GP (int) regs. */ const gdb_byte *raw_buffer; struct value *value; - int ncols = (mips_abi_regsize (gdbarch) == 8 ? 4 : 8); /* display cols + int ncols = (mips_abi_regsize (gdbarch) == 8 ? 4 : 8); /* display cols per row. */ int col, byte; int regnum; /* For GP registers, we print a separate row of names above the vals. */ for (col = 0, regnum = start_regnum; - col < ncols && regnum < gdbarch_num_cooked_regs (gdbarch); - regnum++) + col < ncols && regnum < gdbarch_num_cooked_regs (gdbarch); regnum++) { if (*gdbarch_register_name (gdbarch, regnum) == '\0') - continue; /* unused register */ + continue; /* unused register */ if (mips_float_register_p (gdbarch, regnum)) - break; /* End the row: reached FP register. */ + break; /* End the row: reached FP register. */ /* Large registers are handled separately. */ if (register_size (gdbarch, regnum) > mips_abi_regsize (gdbarch)) { if (col > 0) - break; /* End the row before this register. */ + break; /* End the row before this register. */ /* Print this register on a row by itself. */ mips_print_register (file, frame, regnum); @@ -6555,8 +6449,7 @@ print_gp_register_row (struct ui_file *file, frame_info_ptr frame, } if (col == 0) gdb_printf (file, " "); - gdb_printf (file, - mips_abi_regsize (gdbarch) == 8 ? "%17s" : "%9s", + gdb_printf (file, mips_abi_regsize (gdbarch) == 8 ? "%17s" : "%9s", gdbarch_register_name (gdbarch, regnum)); col++; } @@ -6566,55 +6459,50 @@ print_gp_register_row (struct ui_file *file, frame_info_ptr frame, /* Print the R0 to R31 names. */ if ((start_regnum % gdbarch_num_regs (gdbarch)) < MIPS_NUMREGS) - gdb_printf (file, "\n R%-4d", - start_regnum % gdbarch_num_regs (gdbarch)); + gdb_printf (file, "\n R%-4d", start_regnum % gdbarch_num_regs (gdbarch)); else gdb_printf (file, "\n "); /* Now print the values in hex, 4 or 8 to the row. */ for (col = 0, regnum = start_regnum; - col < ncols && regnum < gdbarch_num_cooked_regs (gdbarch); - regnum++) + col < ncols && regnum < gdbarch_num_cooked_regs (gdbarch); regnum++) { if (*gdbarch_register_name (gdbarch, regnum) == '\0') - continue; /* unused register */ + continue; /* unused register */ if (mips_float_register_p (gdbarch, regnum)) - break; /* End row: reached FP register. */ + break; /* End row: reached FP register. */ if (register_size (gdbarch, regnum) > mips_abi_regsize (gdbarch)) - break; /* End row: large register. */ + break; /* End row: large register. */ /* OK: get the data in raw format. */ value = get_frame_register_value (frame, regnum); - if (value_optimized_out (value) - || !value_entirely_available (value)) + if (value_optimized_out (value) || !value_entirely_available (value)) { - gdb_printf (file, "%*s ", - (int) mips_abi_regsize (gdbarch) * 2, + gdb_printf (file, "%*s ", (int) mips_abi_regsize (gdbarch) * 2, (mips_abi_regsize (gdbarch) == 4 ? "<unavl>" - : "<unavailable>")); + : "<unavailable>")); col++; continue; } raw_buffer = value_contents_all (value).data (); /* pad small registers */ - for (byte = 0; - byte < (mips_abi_regsize (gdbarch) - - register_size (gdbarch, regnum)); byte++) + for (byte = 0; byte < (mips_abi_regsize (gdbarch) + - register_size (gdbarch, regnum)); + byte++) gdb_printf (file, " "); /* Now print the register value in hex, endian order. */ if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) - for (byte = - register_size (gdbarch, regnum) - register_size (gdbarch, regnum); + for (byte = register_size (gdbarch, regnum) + - register_size (gdbarch, regnum); byte < register_size (gdbarch, regnum); byte++) gdb_printf (file, "%02x", raw_buffer[byte]); else - for (byte = register_size (gdbarch, regnum) - 1; - byte >= 0; byte--) + for (byte = register_size (gdbarch, regnum) - 1; byte >= 0; byte--) gdb_printf (file, "%02x", raw_buffer[byte]); gdb_printf (file, " "); col++; } - if (col > 0) /* ie. if we actually printed anything... */ + if (col > 0) /* ie. if we actually printed anything... */ gdb_printf (file, "\n"); return regnum; @@ -6626,11 +6514,11 @@ static void mips_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file, frame_info_ptr frame, int regnum, int all) { - if (regnum != -1) /* Do one specified register. */ + if (regnum != -1) /* Do one specified register. */ { gdb_assert (regnum >= gdbarch_num_regs (gdbarch)); if (*(gdbarch_register_name (gdbarch, regnum)) == '\0') - error (_("Not a valid register for the current processor type")); + error (_ ("Not a valid register for the current processor type")); mips_print_register (file, frame, regnum); gdb_printf (file, "\n"); @@ -6643,10 +6531,10 @@ mips_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file, { if (mips_float_register_p (gdbarch, regnum)) { - if (all) /* True for "INFO ALL-REGISTERS" command. */ + if (all) /* True for "INFO ALL-REGISTERS" command. */ regnum = print_fp_register_row (file, frame, regnum); else - regnum += MIPS_NUMREGS; /* Skip floating point regs. */ + regnum += MIPS_NUMREGS; /* Skip floating point regs. */ } else regnum = print_gp_register_row (file, frame, regnum); @@ -6655,16 +6543,14 @@ mips_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file, } static int -mips_single_step_through_delay (struct gdbarch *gdbarch, - frame_info_ptr frame) +mips_single_step_through_delay (struct gdbarch *gdbarch, frame_info_ptr frame) { CORE_ADDR pc = get_frame_pc (frame); enum mips_isa isa; ULONGEST insn; int size; - if ((mips_pc_is_mips (pc) - && !mips32_insn_at_pc_has_delay_slot (gdbarch, pc)) + if ((mips_pc_is_mips (pc) && !mips32_insn_at_pc_has_delay_slot (gdbarch, pc)) || (mips_pc_is_micromips (gdbarch, pc) && !micromips_insn_at_pc_has_delay_slot (gdbarch, pc, 0)) || (mips_pc_is_mips16 (gdbarch, pc) @@ -6715,7 +6601,7 @@ mips_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc) that bound, then use an arbitrary large number as the upper bound. */ limit_pc = skip_prologue_using_sal (gdbarch, pc); if (limit_pc == 0) - limit_pc = pc + 100; /* Magic. */ + limit_pc = pc + 100; /* Magic. */ if (mips_pc_is_mips16 (gdbarch, pc)) return mips16_scan_prologue (gdbarch, pc, limit_pc, NULL, NULL); @@ -6751,10 +6637,10 @@ mips32_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc) inst = mips_fetch_instruction (gdbarch, ISA_MIPS, pc, NULL); high_word = (inst >> 16) & 0xffff; - if (high_word != 0x27bd /* addiu $sp,$sp,offset */ - && high_word != 0x67bd /* daddiu $sp,$sp,offset */ - && inst != 0x03e00008 /* jr $ra */ - && inst != 0x00000000) /* nop */ + if (high_word != 0x27bd /* addiu $sp,$sp,offset */ + && high_word != 0x67bd /* daddiu $sp,$sp,offset */ + && inst != 0x03e00008 /* jr $ra */ + && inst != 0x00000000) /* nop */ return 0; } @@ -6800,18 +6686,19 @@ micromips_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc) /* 32-bit instructions. */ case 2 * MIPS_INSN16_SIZE: insn <<= 16; - insn |= mips_fetch_instruction (gdbarch, - ISA_MICROMIPS, pc + loc, NULL); + insn + |= mips_fetch_instruction (gdbarch, ISA_MICROMIPS, pc + loc, NULL); loc += MIPS_INSN16_SIZE; switch (micromips_op (insn >> 16)) { - case 0xc: /* ADDIU: bits 001100 */ + case 0xc: /* ADDIU: bits 001100 */ case 0x17: /* DADDIU: bits 010111 */ sreg = b0s5_reg (insn >> 16); dreg = b5s5_reg (insn >> 16); offset = (b0s16_imm (insn) ^ 0x8000) - 0x8000; - if (sreg == MIPS_SP_REGNUM && dreg == MIPS_SP_REGNUM - /* (D)ADDIU $sp, imm */ + if (sreg == MIPS_SP_REGNUM + && dreg == MIPS_SP_REGNUM + /* (D)ADDIU $sp, imm */ && offset >= 0) break; return 0; @@ -6829,24 +6716,24 @@ micromips_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc) sreg = b0s5_reg (insn); dreg = b5s5_reg (insn); if (sreg == 0 && dreg == 0) - /* MOVE $zero, $zero aka NOP */ + /* MOVE $zero, $zero aka NOP */ break; return 0; case 0x11: /* POOL16C: bits 010001 */ if (b5s5_op (insn) == 0x18 - /* JRADDIUSP: bits 010011 11000 */ + /* JRADDIUSP: bits 010011 11000 */ || (b5s5_op (insn) == 0xd - /* JRC: bits 010011 01101 */ + /* JRC: bits 010011 01101 */ && b0s5_reg (insn) == MIPS_RA_REGNUM)) - /* JRC $ra */ + /* JRC $ra */ break; return 0; case 0x13: /* POOL16D: bits 010011 */ offset = micromips_decode_imm9 (b1s9_imm (insn)); if ((insn & 0x1) == 0x1 - /* ADDIUSP: bits 010011 1 */ + /* ADDIUSP: bits 010011 1 */ && offset > 0) break; return 0; @@ -6884,14 +6771,14 @@ mips16_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc) inst = mips_fetch_instruction (gdbarch, ISA_MIPS16, pc, NULL); - if ((inst & 0xf800) == 0xf000) /* extend */ + if ((inst & 0xf800) == 0xf000) /* extend */ continue; - if (inst != 0x6300 /* addiu $sp,offset */ - && inst != 0xfb00 /* daddiu $sp,$sp,offset */ - && inst != 0xe820 /* jr $ra */ - && inst != 0xe8a0 /* jrc $ra */ - && inst != 0x6500) /* nop */ + if (inst != 0x6300 /* addiu $sp,offset */ + && inst != 0xfb00 /* daddiu $sp,$sp,offset */ + && inst != 0xe820 /* jr $ra */ + && inst != 0xe8a0 /* jrc $ra */ + && inst != 0x6500) /* nop */ return 0; } @@ -6926,9 +6813,8 @@ show_mipsfpu_command (const char *args, int from_tty) if (gdbarch_bfd_arch_info (target_gdbarch ())->arch != bfd_arch_mips) { - gdb_printf - ("The MIPS floating-point coprocessor is unknown " - "because the current architecture is not MIPS.\n"); + gdb_printf ("The MIPS floating-point coprocessor is unknown " + "because the current architecture is not MIPS.\n"); return; } @@ -6944,18 +6830,17 @@ show_mipsfpu_command (const char *args, int from_tty) fpu = "absent (none)"; break; default: - internal_error (_("bad switch")); + internal_error (_ ("bad switch")); } if (mips_fpu_type_auto) gdb_printf ("The MIPS floating-point coprocessor " "is set automatically (currently %s)\n", fpu); else - gdb_printf - ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu); + gdb_printf ("The MIPS floating-point coprocessor is assumed to be %s\n", + fpu); } - static void set_mipsfpu_single_command (const char *args, int from_tty) { @@ -6966,7 +6851,7 @@ set_mipsfpu_single_command (const char *args, int from_tty) instead of relying on globals. Doing that would let generic code handle the search for this specific architecture. */ if (!gdbarch_update_p (info)) - internal_error (_("set mipsfpu failed")); + internal_error (_ ("set mipsfpu failed")); } static void @@ -6979,7 +6864,7 @@ set_mipsfpu_double_command (const char *args, int from_tty) instead of relying on globals. Doing that would let generic code handle the search for this specific architecture. */ if (!gdbarch_update_p (info)) - internal_error (_("set mipsfpu failed")); + internal_error (_ ("set mipsfpu failed")); } static void @@ -6992,7 +6877,7 @@ set_mipsfpu_none_command (const char *args, int from_tty) instead of relying on globals. Doing that would let generic code handle the search for this specific architecture. */ if (!gdbarch_update_p (info)) - internal_error (_("set mipsfpu failed")); + internal_error (_ ("set mipsfpu failed")); } static void @@ -7028,8 +6913,10 @@ gdb_print_insn_mips (bfd_vma memaddr, struct disassemble_info *info) info->mach = bfd_mach_mips_micromips; /* Round down the instruction address to the appropriate boundary. */ - memaddr &= (info->mach == bfd_mach_mips16 - || info->mach == bfd_mach_mips_micromips) ? ~1 : ~3; + memaddr + &= (info->mach == bfd_mach_mips16 || info->mach == bfd_mach_mips_micromips) + ? ~1 + : ~3; return default_print_insn (memaddr, info); } @@ -7137,35 +7024,35 @@ mips32_instruction_has_delay_slot (struct gdbarch *gdbarch, ULONGEST inst) { rs = itype_rs (inst); rt = itype_rt (inst); - return (is_octeon_bbit_op (op, gdbarch) - || op >> 2 == 5 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */ - || op == 29 /* JALX: bits 011101 */ + return (is_octeon_bbit_op (op, gdbarch) + || op >> 2 == 5 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */ + || op == 29 /* JALX: bits 011101 */ || (op == 17 && (rs == 8 - /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */ + /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */ || (rs == 9 && (rt & 0x2) == 0) - /* BC1ANY2F, BC1ANY2T: bits 010001 01001 */ + /* BC1ANY2F, BC1ANY2T: bits 010001 01001 */ || (rs == 10 && (rt & 0x2) == 0)))); - /* BC1ANY4F, BC1ANY4T: bits 010001 01010 */ + /* BC1ANY4F, BC1ANY4T: bits 010001 01010 */ } else - switch (op & 0x07) /* extract bits 28,27,26 */ + switch (op & 0x07) /* extract bits 28,27,26 */ { - case 0: /* SPECIAL */ + case 0: /* SPECIAL */ op = rtype_funct (inst); - return (op == 8 /* JR */ - || op == 9); /* JALR */ - break; /* end SPECIAL */ - case 1: /* REGIMM */ + return (op == 8 /* JR */ + || op == 9); /* JALR */ + break; /* end SPECIAL */ + case 1: /* REGIMM */ rs = itype_rs (inst); - rt = itype_rt (inst); /* branch condition */ + rt = itype_rt (inst); /* branch condition */ return ((rt & 0xc) == 0 - /* BLTZ, BLTZL, BGEZ, BGEZL: bits 000xx */ - /* BLTZAL, BLTZALL, BGEZAL, BGEZALL: 100xx */ + /* BLTZ, BLTZL, BGEZ, BGEZL: bits 000xx */ + /* BLTZAL, BLTZALL, BGEZAL, BGEZALL: 100xx */ || ((rt & 0x1e) == 0x1c && rs == 0)); - /* BPOSGE32, BPOSGE64: bits 1110x */ - break; /* end REGIMM */ - default: /* J, JAL, BEQ, BNE, BLEZ, BGTZ */ + /* BPOSGE32, BPOSGE64: bits 1110x */ + break; /* end REGIMM */ + default: /* J, JAL, BEQ, BNE, BLEZ, BGTZ */ return 1; break; } @@ -7201,48 +7088,45 @@ micromips_instruction_has_delay_slot (ULONGEST insn, int mustbe32) switch (micromips_op (major)) { /* 16-bit instructions. */ - case 0x33: /* B16: bits 110011 */ - case 0x2b: /* BNEZ16: bits 101011 */ - case 0x23: /* BEQZ16: bits 100011 */ + case 0x33: /* B16: bits 110011 */ + case 0x2b: /* BNEZ16: bits 101011 */ + case 0x23: /* BEQZ16: bits 100011 */ return !mustbe32; - case 0x11: /* POOL16C: bits 010001 */ + case 0x11: /* POOL16C: bits 010001 */ return (!mustbe32 && ((b5s5_op (major) == 0xc - /* JR16: bits 010001 01100 */ - || (b5s5_op (major) & 0x1e) == 0xe))); - /* JALR16, JALRS16: bits 010001 0111x */ + /* JR16: bits 010001 01100 */ + || (b5s5_op (major) & 0x1e) == 0xe))); + /* JALR16, JALRS16: bits 010001 0111x */ /* 32-bit instructions. */ - case 0x3d: /* JAL: bits 111101 */ - case 0x3c: /* JALX: bits 111100 */ - case 0x35: /* J: bits 110101 */ - case 0x2d: /* BNE: bits 101101 */ - case 0x25: /* BEQ: bits 100101 */ - case 0x1d: /* JALS: bits 011101 */ + case 0x3d: /* JAL: bits 111101 */ + case 0x3c: /* JALX: bits 111100 */ + case 0x35: /* J: bits 110101 */ + case 0x2d: /* BNE: bits 101101 */ + case 0x25: /* BEQ: bits 100101 */ + case 0x1d: /* JALS: bits 011101 */ return 1; - case 0x10: /* POOL32I: bits 010000 */ + case 0x10: /* POOL32I: bits 010000 */ return ((b5s5_op (major) & 0x1c) == 0x0 - /* BLTZ, BLTZAL, BGEZ, BGEZAL: 010000 000xx */ + /* BLTZ, BLTZAL, BGEZ, BGEZAL: 010000 000xx */ || (b5s5_op (major) & 0x1d) == 0x4 - /* BLEZ, BGTZ: bits 010000 001x0 */ + /* BLEZ, BGTZ: bits 010000 001x0 */ || (b5s5_op (major) & 0x1d) == 0x11 - /* BLTZALS, BGEZALS: bits 010000 100x1 */ - || ((b5s5_op (major) & 0x1e) == 0x14 - && (major & 0x3) == 0x0) - /* BC2F, BC2T: bits 010000 1010x xxx00 */ + /* BLTZALS, BGEZALS: bits 010000 100x1 */ + || ((b5s5_op (major) & 0x1e) == 0x14 && (major & 0x3) == 0x0) + /* BC2F, BC2T: bits 010000 1010x xxx00 */ || (b5s5_op (major) & 0x1e) == 0x1a - /* BPOSGE64, BPOSGE32: bits 010000 1101x */ - || ((b5s5_op (major) & 0x1e) == 0x1c - && (major & 0x3) == 0x0) - /* BC1F, BC1T: bits 010000 1110x xxx00 */ - || ((b5s5_op (major) & 0x1c) == 0x1c - && (major & 0x3) == 0x1)); - /* BC1ANY*: bits 010000 111xx xxx01 */ - case 0x0: /* POOL32A: bits 000000 */ + /* BPOSGE64, BPOSGE32: bits 010000 1101x */ + || ((b5s5_op (major) & 0x1e) == 0x1c && (major & 0x3) == 0x0) + /* BC1F, BC1T: bits 010000 1110x xxx00 */ + || ((b5s5_op (major) & 0x1c) == 0x1c && (major & 0x3) == 0x1)); + /* BC1ANY*: bits 010000 111xx xxx01 */ + case 0x0: /* POOL32A: bits 000000 */ return (b0s6_op (insn) == 0x3c - /* POOL32Axf: bits 000000 ... 111100 */ + /* POOL32Axf: bits 000000 ... 111100 */ && (b6s10_ext (insn) & 0x2bf) == 0x3c); - /* JALR, JALR.HB: 000000 000x111100 111100 */ - /* JALRS, JALRS.HB: 000000 010x111100 111100 */ + /* JALR, JALR.HB: 000000 000x111100 111100 */ + /* JALRS, JALRS.HB: 000000 010x111100 111100 */ default: return 0; } @@ -7253,8 +7137,8 @@ micromips_instruction_has_delay_slot (ULONGEST insn, int mustbe32) must be 32-bit if MUSTBE32 is set or can be any instruction otherwise. */ static int -micromips_insn_at_pc_has_delay_slot (struct gdbarch *gdbarch, - CORE_ADDR addr, int mustbe32) +micromips_insn_at_pc_has_delay_slot (struct gdbarch *gdbarch, CORE_ADDR addr, + int mustbe32) { ULONGEST insn; int status; @@ -7283,9 +7167,9 @@ micromips_insn_at_pc_has_delay_slot (struct gdbarch *gdbarch, static int mips16_instruction_has_delay_slot (unsigned short inst, int mustbe32) { - if ((inst & 0xf89f) == 0xe800) /* JR/JALR (16-bit instruction) */ + if ((inst & 0xf89f) == 0xe800) /* JR/JALR (16-bit instruction) */ return !mustbe32; - return (inst & 0xf800) == 0x1800; /* JAL/JALX (32-bit instruction) */ + return (inst & 0xf800) == 0x1800; /* JAL/JALX (32-bit instruction) */ } /* Return non-zero if a MIPS16 instruction at ADDR has a branch delay @@ -7293,8 +7177,8 @@ mips16_instruction_has_delay_slot (unsigned short inst, int mustbe32) must be 32-bit if MUSTBE32 is set or can be any instruction otherwise. */ static int -mips16_insn_at_pc_has_delay_slot (struct gdbarch *gdbarch, - CORE_ADDR addr, int mustbe32) +mips16_insn_at_pc_has_delay_slot (struct gdbarch *gdbarch, CORE_ADDR addr, + int mustbe32) { unsigned short insn; int status; @@ -7323,21 +7207,21 @@ mips_segment_boundary (CORE_ADDR bpaddr) { case 3: if (bpaddr == (bfd_signed_vma) (int32_t) bpaddr) - segsize = 29; /* 32-bit compatibility segment */ + segsize = 29; /* 32-bit compatibility segment */ else - segsize = 62; /* xkseg */ + segsize = 62; /* xkseg */ break; - case 2: /* xkphys */ + case 2: /* xkphys */ segsize = 59; break; - default: /* xksseg (1), xkuseg/kuseg (0) */ + default: /* xksseg (1), xkuseg/kuseg (0) */ segsize = 62; break; } - else if (bpaddr & 0x80000000) /* kernel segment */ + else if (bpaddr & 0x80000000) /* kernel segment */ segsize = 29; else - segsize = 31; /* user segment */ + segsize = 31; /* user segment */ mask <<= segsize; return bpaddr & mask; } @@ -7417,8 +7301,8 @@ mips_adjust_breakpoint_address (struct gdbarch *gdbarch, CORE_ADDR bpaddr) FIXME: We have to assume that bpaddr is not the second half of an extended instruction. */ insn_at_pc_has_delay_slot = (mips_pc_is_micromips (gdbarch, bpaddr) - ? micromips_insn_at_pc_has_delay_slot - : mips16_insn_at_pc_has_delay_slot); + ? micromips_insn_at_pc_has_delay_slot + : mips16_insn_at_pc_has_delay_slot); jmpaddr = 0; addr = bpaddr; @@ -7483,19 +7367,19 @@ static int mips_is_stub_suffix (const char *suffix, int zero) { switch (suffix[0]) - { - case '0': - return zero && suffix[1] == '\0'; - case '1': - return suffix[1] == '\0' || (suffix[1] == '0' && suffix[2] == '\0'); - case '2': - case '5': - case '6': - case '9': - return suffix[1] == '\0'; - default: - return 0; - } + { + case '0': + return zero && suffix[1] == '\0'; + case '1': + return suffix[1] == '\0' || (suffix[1] == '0' && suffix[2] == '\0'); + case '2': + case '5': + case '6': + case '9': + return suffix[1] == '\0'; + default: + return 0; + } } /* Return non-zero if MODE is one of the mode infixes used for MIPS16 @@ -7573,8 +7457,7 @@ mips_get_mips16_fn_stub_pc (frame_info_ptr frame, CORE_ADDR pc) int status = 0; int i; - for (i = 0; - status == 0 && target_pc == 0 && i < 20; + for (i = 0; status == 0 && target_pc == 0 && i < 20; i++, pc += MIPS_INSN32_SIZE) { ULONGEST inst = mips_fetch_instruction (gdbarch, ISA_MIPS, pc, NULL); @@ -7585,19 +7468,19 @@ mips_get_mips16_fn_stub_pc (frame_info_ptr frame, CORE_ADDR pc) switch (itype_op (inst)) { - case 0: /* SPECIAL */ + case 0: /* SPECIAL */ switch (rtype_funct (inst)) { - case 8: /* JR */ - case 9: /* JALR */ + case 8: /* JR */ + case 9: /* JALR */ rs = rtype_rs (inst); if (rs == MIPS_GP_REGNUM) - target_pc = gp; /* Hmm... */ + target_pc = gp; /* Hmm... */ else if (rs == addrreg) target_pc = addr; break; - case 0x21: /* ADDU */ + case 0x21: /* ADDU */ rt = rtype_rt (inst); rs = rtype_rs (inst); rd = rtype_rd (inst); @@ -7609,13 +7492,13 @@ mips_get_mips16_fn_stub_pc (frame_info_ptr frame, CORE_ADDR pc) } break; - case 2: /* J */ - case 3: /* JAL */ + case 2: /* J */ + case 3: /* JAL */ target_pc = jtype_target (inst) << 2; target_pc += ((pc + 4) & ~(CORE_ADDR) 0x0fffffff); break; - case 9: /* ADDIU */ + case 9: /* ADDIU */ rt = itype_rt (inst); rs = itype_rs (inst); if (rt == rs) @@ -7628,7 +7511,7 @@ mips_get_mips16_fn_stub_pc (frame_info_ptr frame, CORE_ADDR pc) } break; - case 0xf: /* LUI */ + case 0xf: /* LUI */ rt = itype_rt (inst); imm = ((itype_immediate (inst) ^ 0x8000) - 0x8000) << 16; if (rt == MIPS_GP_REGNUM) @@ -7640,7 +7523,7 @@ mips_get_mips16_fn_stub_pc (frame_info_ptr frame, CORE_ADDR pc) } break; - case 0x23: /* LW */ + case 0x23: /* LW */ rt = itype_rt (inst); rs = itype_rs (inst); imm = (itype_immediate (inst) ^ 0x8000) - 0x8000; @@ -7699,10 +7582,9 @@ mips_skip_mips16_trampoline_code (frame_info_ptr frame, CORE_ADDR pc) and the target PC is in $31 ($ra). */ prefixlen = strlen (mips_str_mips16_ret_stub); if (strncmp (name, mips_str_mips16_ret_stub, prefixlen) == 0 - && mips_is_stub_mode (name + prefixlen) - && name[prefixlen + 2] == '\0') - return get_frame_register_signed - (frame, gdbarch_num_regs (gdbarch) + MIPS_RA_REGNUM); + && mips_is_stub_mode (name + prefixlen) && name[prefixlen + 2] == '\0') + return get_frame_register_signed (frame, gdbarch_num_regs (gdbarch) + + MIPS_RA_REGNUM); /* If the PC is in __mips16_call_stub_*, this is one of the call call/return stubs. */ @@ -7712,8 +7594,8 @@ mips_skip_mips16_trampoline_code (frame_info_ptr frame, CORE_ADDR pc) /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub and the target PC is in $2. */ if (mips_is_stub_suffix (name + prefixlen, 0)) - return get_frame_register_signed - (frame, gdbarch_num_regs (gdbarch) + MIPS_V0_REGNUM); + return get_frame_register_signed (frame, gdbarch_num_regs (gdbarch) + + MIPS_V0_REGNUM); /* If the PC at the start of __mips16_call_stub_{s,d}{f,c}_{0..10}, i.e. before the JALR instruction, this is effectively a call stub @@ -7726,16 +7608,16 @@ mips_skip_mips16_trampoline_code (frame_info_ptr frame, CORE_ADDR pc) if (pc == start_addr) /* This is the 'call' part of a call stub. The return address is in $2. */ - return get_frame_register_signed - (frame, gdbarch_num_regs (gdbarch) + MIPS_V0_REGNUM); + return get_frame_register_signed (frame, gdbarch_num_regs (gdbarch) + + MIPS_V0_REGNUM); else /* This is the 'return' part of a call stub. The return address is in $18. */ - return get_frame_register_signed - (frame, gdbarch_num_regs (gdbarch) + MIPS_S2_REGNUM); + return get_frame_register_signed (frame, gdbarch_num_regs (gdbarch) + + MIPS_S2_REGNUM); } else - return 0; /* Not a stub. */ + return 0; /* Not a stub. */ } /* If the PC is in __call_stub_* or __fn_stub*, this is one of the @@ -7751,11 +7633,11 @@ mips_skip_mips16_trampoline_code (frame_info_ptr frame, CORE_ADDR pc) else /* This is the 'return' part of a call stub. The return address is in $18. */ - return get_frame_register_signed - (frame, gdbarch_num_regs (gdbarch) + MIPS_S2_REGNUM); + return get_frame_register_signed (frame, gdbarch_num_regs (gdbarch) + + MIPS_S2_REGNUM); } - return 0; /* Not a stub. */ + return 0; /* Not a stub. */ } /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline). @@ -7777,8 +7659,7 @@ mips_in_return_stub (struct gdbarch *gdbarch, CORE_ADDR pc, const char *name) prefixlen = strlen (mips_str_mips16_call_stub); if (pc != start_addr && strncmp (name, mips_str_mips16_call_stub, prefixlen) == 0 - && mips_is_stub_mode (name + prefixlen) - && name[prefixlen + 2] == '_' + && mips_is_stub_mode (name + prefixlen) && name[prefixlen + 2] == '_' && mips_is_stub_suffix (name + prefixlen + 3, 1)) return 1; @@ -7800,11 +7681,10 @@ mips_in_return_stub (struct gdbarch *gdbarch, CORE_ADDR pc, const char *name) /* If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub. */ prefixlen = strlen (mips_str_mips16_ret_stub); if (strncmp (name, mips_str_mips16_ret_stub, prefixlen) == 0 - && mips_is_stub_mode (name + prefixlen) - && name[prefixlen + 2] == '\0') + && mips_is_stub_mode (name + prefixlen) && name[prefixlen + 2] == '\0') return 1; - return 0; /* Not a stub. */ + return 0; /* Not a stub. */ } /* If the current PC is the start of a non-PIC-to-PIC stub, return the @@ -7825,8 +7705,7 @@ mips_skip_pic_trampoline_code (frame_info_ptr frame, CORE_ADDR pc) instructions inserted before foo or a three instruction sequence which jumps to foo. */ msym = lookup_minimal_symbol_by_pc (pc); - if (msym.minsym == NULL - || msym.value_address () != pc + if (msym.minsym == NULL || msym.value_address () != pc || msym.minsym->linkage_name () == NULL || !startswith (msym.minsym->linkage_name (), ".pic.")) return 0; @@ -7841,8 +7720,8 @@ mips_skip_pic_trampoline_code (frame_info_ptr frame, CORE_ADDR pc) if (target_read_memory (pc, stub_code, 16) != 0) return 0; for (i = 0; i < 4; i++) - stub_words[i] = extract_unsigned_integer (stub_code + i * 4, - 4, byte_order); + stub_words[i] + = extract_unsigned_integer (stub_code + i * 4, 4, byte_order); /* A stub contains these instructions: lui t9, %hi(target) @@ -7857,7 +7736,9 @@ mips_skip_pic_trampoline_code (frame_info_ptr frame, CORE_ADDR pc) && (stub_words[2] & 0xffff0000U) == 0x27390000 && stub_words[3] == 0x00000000) return ((((stub_words[0] & 0x0000ffff) << 16) - + (stub_words[2] & 0x0000ffff)) ^ 0x8000) - 0x8000; + + (stub_words[2] & 0x0000ffff)) + ^ 0x8000) + - 0x8000; } /* Not a recognized stub. */ @@ -7914,7 +7795,6 @@ mips_stab_reg_to_regnum (struct gdbarch *gdbarch, int num) return gdbarch_num_regs (gdbarch) + regnum; } - /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 * gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */ @@ -7945,20 +7825,19 @@ mips_register_sim_regno (struct gdbarch *gdbarch, int regnum) /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to decide if it is valid. Should instead define a standard sim/gdb register numbering scheme. */ - if (gdbarch_register_name (gdbarch, - gdbarch_num_regs (gdbarch) + regnum)[0] != '\0') + if (gdbarch_register_name (gdbarch, gdbarch_num_regs (gdbarch) + regnum)[0] + != '\0') return regnum; else return LEGACY_SIM_REGNO_IGNORE; } - /* Convert an integer into an address. Extracting the value signed guarantees a correctly sign extended address. */ static CORE_ADDR -mips_integer_to_address (struct gdbarch *gdbarch, - struct type *type, const gdb_byte *buf) +mips_integer_to_address (struct gdbarch *gdbarch, struct type *type, + const gdb_byte *buf) { enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); return extract_signed_integer (buf, type->length (), byte_order); @@ -7970,8 +7849,8 @@ mips_integer_to_address (struct gdbarch *gdbarch, an assertion failure. */ static void -mips_virtual_frame_pointer (struct gdbarch *gdbarch, - CORE_ADDR pc, int *reg, LONGEST *offset) +mips_virtual_frame_pointer (struct gdbarch *gdbarch, CORE_ADDR pc, int *reg, + LONGEST *offset) { *reg = MIPS_SP_REGNUM; *offset = 0; @@ -8002,7 +7881,7 @@ mips_find_abi_section (bfd *abfd, asection *sect, void *obj) else if (strcmp (name, ".mdebug.eabi64") == 0) *abip = MIPS_ABI_EABI64; else - warning (_("unsupported ABI %s."), name + 8); + warning (_ ("unsupported ABI %s."), name + 8); } static void @@ -8016,7 +7895,7 @@ mips_find_long_section (bfd *abfd, asection *sect, void *obj) else if (startswith (name, ".gcc_compiled_long64")) *lbp = 64; else if (startswith (name, ".gcc_compiled_long")) - warning (_("unrecognized .gcc_compiled_longXX")); + warning (_ ("unrecognized .gcc_compiled_longXX")); } static enum mips_abi @@ -8028,7 +7907,7 @@ global_mips_abi (void) if (mips_abi_strings[i] == mips_abi_string) return (enum mips_abi) i; - internal_error (_("unknown ABI string")); + internal_error (_ ("unknown ABI string")); } /* Return the default compressed instruction set, either of MIPS16 @@ -8045,7 +7924,7 @@ global_mips_compression (void) if (mips_compression_strings[i] == mips_compression_string) return (enum mips_isa) i; - internal_error (_("unknown compressed ISA string")); + internal_error (_ ("unknown compressed ISA string")); } static void @@ -8081,7 +7960,7 @@ mips_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) enum mips_fpu_type fpu_type; tdesc_arch_data_up tdesc_data; int elf_fpu_type = Val_GNU_MIPS_ABI_FP_ANY; - const char * const *reg_names; + const char *const *reg_names; struct mips_regnum mips_regnum, *regnum; enum mips_isa mips_isa; int dspacc; @@ -8099,8 +7978,8 @@ mips_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) else elf_flags = 0; if (gdbarch_debug) - gdb_printf (gdb_stdlog, - "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags); + gdb_printf (gdb_stdlog, "mips_gdbarch_init: elf_flags = 0x%08x\n", + elf_flags); /* Check ELF_FLAGS to see if it specifies the ABI being used. */ switch ((elf_flags & EF_MIPS_ABI)) @@ -8139,8 +8018,7 @@ mips_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) } /* Try the architecture for any hint of the correct ABI. */ - if (found_abi == MIPS_ABI_UNKNOWN - && info.bfd_arch_info != NULL + if (found_abi == MIPS_ABI_UNKNOWN && info.bfd_arch_info != NULL && info.bfd_arch_info->arch == bfd_arch_mips) { switch (info.bfd_arch_info->mach) @@ -8168,15 +8046,13 @@ mips_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) } /* Default 64-bit objects to N64 instead of O32. */ - if (found_abi == MIPS_ABI_UNKNOWN - && info.abfd != NULL + if (found_abi == MIPS_ABI_UNKNOWN && info.abfd != NULL && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour && elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) found_abi = MIPS_ABI_N64; if (gdbarch_debug) - gdb_printf (gdb_stdlog, "mips_gdbarch_init: found_abi = %d\n", - found_abi); + gdb_printf (gdb_stdlog, "mips_gdbarch_init: found_abi = %d\n", found_abi); /* What has the user specified from the command line? */ wanted_abi = global_mips_abi (); @@ -8193,12 +8069,10 @@ mips_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) else mips_abi = MIPS_ABI_O32; if (gdbarch_debug) - gdb_printf (gdb_stdlog, "mips_gdbarch_init: mips_abi = %d\n", - mips_abi); + gdb_printf (gdb_stdlog, "mips_gdbarch_init: mips_abi = %d\n", mips_abi); /* Make sure we don't use a 32-bit architecture with a 64-bit ABI. */ - if (mips_abi != MIPS_ABI_EABI32 - && mips_abi != MIPS_ABI_O32 + if (mips_abi != MIPS_ABI_EABI32 && mips_abi != MIPS_ABI_O32 && info.bfd_arch_info != NULL && info.bfd_arch_info->arch == bfd_arch_mips && info.bfd_arch_info->bits_per_word < 64) @@ -8222,10 +8096,9 @@ mips_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) "mips64_transfers_32bit_regs_p = %d\n", mips64_transfers_32bit_regs_p); - /* Determine the MIPS FPU type. */ + /* Determine the MIPS FPU type. */ #ifdef HAVE_ELF - if (info.abfd - && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) + if (info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour) elf_fpu_type = bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_GNU, Tag_GNU_MIPS_ABI_FP); #endif /* HAVE_ELF */ @@ -8271,8 +8144,7 @@ mips_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) else fpu_type = MIPS_FPU_DOUBLE; if (gdbarch_debug) - gdb_printf (gdb_stdlog, - "mips_gdbarch_init: fpu_type = %d\n", fpu_type); + gdb_printf (gdb_stdlog, "mips_gdbarch_init: fpu_type = %d\n", fpu_type); /* Check for blatant incompatibilities. */ @@ -8280,8 +8152,7 @@ mips_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) ABI. */ if (info.target_desc && tdesc_property (info.target_desc, PROPERTY_GP32) != NULL - && mips_abi != MIPS_ABI_EABI32 - && mips_abi != MIPS_ABI_O32) + && mips_abi != MIPS_ABI_EABI32 && mips_abi != MIPS_ABI_O32) return NULL; /* Fill in the OS dependent register numbers and names. */ @@ -8325,15 +8196,14 @@ mips_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) /* Check any target description for validity. */ if (tdesc_has_registers (info.target_desc)) { - static const char *const mips_gprs[] = { - "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", - "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", - "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", - "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" - }; + static const char *const mips_gprs[] + = { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", + "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", + "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", + "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" }; static const char *const mips_fprs[] = { - "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", - "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", + "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", + "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", }; @@ -8341,8 +8211,7 @@ mips_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) const struct tdesc_feature *feature; int valid_p; - feature = tdesc_find_feature (info.target_desc, - "org.gnu.gdb.mips.cpu"); + feature = tdesc_find_feature (info.target_desc, "org.gnu.gdb.mips.cpu"); if (feature == NULL) return NULL; @@ -8353,7 +8222,6 @@ mips_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), i, mips_gprs[i]); - valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), mips_regnum.lo, "lo"); valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), @@ -8364,8 +8232,7 @@ mips_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) if (!valid_p) return NULL; - feature = tdesc_find_feature (info.target_desc, - "org.gnu.gdb.mips.cp0"); + feature = tdesc_find_feature (info.target_desc, "org.gnu.gdb.mips.cp0"); if (feature == NULL) return NULL; @@ -8382,8 +8249,7 @@ mips_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) /* FIXME drow/2007-05-17: The FPU should be optional. The MIPS backend is not prepared for that, though. */ - feature = tdesc_find_feature (info.target_desc, - "org.gnu.gdb.mips.fpu"); + feature = tdesc_find_feature (info.target_desc, "org.gnu.gdb.mips.fpu"); if (feature == NULL) return NULL; @@ -8392,9 +8258,9 @@ mips_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), i + mips_regnum.fp0, mips_fprs[i]); - valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), - mips_regnum.fp_control_status, - "fcsr"); + valid_p + &= tdesc_numbered_register (feature, tdesc_data.get (), + mips_regnum.fp_control_status, "fcsr"); valid_p &= tdesc_numbered_register (feature, tdesc_data.get (), mips_regnum.fp_implementation_revision, @@ -8407,8 +8273,8 @@ mips_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) if (dspacc >= 0) { - feature = tdesc_find_feature (info.target_desc, - "org.gnu.gdb.mips.dsp"); + feature + = tdesc_find_feature (info.target_desc, "org.gnu.gdb.mips.dsp"); /* The DSP registers are optional; it's OK if they are absent. */ if (feature != NULL) { @@ -8446,8 +8312,7 @@ mips_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) } /* Try to find a pre-existing architecture. */ - for (arches = gdbarch_list_lookup_by_info (arches, &info); - arches != NULL; + for (arches = gdbarch_list_lookup_by_info (arches, &info); arches != NULL; arches = gdbarch_list_lookup_by_info (arches->next, &info)) { mips_gdbarch_tdep *tdep @@ -8463,8 +8328,7 @@ mips_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) continue; /* Need to be pedantic about which register virtual size is used. */ - if (tdep->mips64_transfers_32bit_regs_p - != mips64_transfers_32bit_regs_p) + if (tdep->mips64_transfers_32bit_regs_p != mips64_transfers_32bit_regs_p) continue; /* Be pedantic about which FPU is selected. */ if (mips_get_fpu_type (arches->gdbarch) != fpu_type) @@ -8514,8 +8378,8 @@ mips_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) set_gdbarch_ax_pseudo_register_collect (gdbarch, mips_ax_pseudo_register_collect); - set_gdbarch_ax_pseudo_register_push_stack - (gdbarch, mips_ax_pseudo_register_push_stack); + set_gdbarch_ax_pseudo_register_push_stack ( + gdbarch, mips_ax_pseudo_register_push_stack); set_gdbarch_elf_make_msymbol_special (gdbarch, mips_elf_make_msymbol_special); @@ -8600,7 +8464,7 @@ mips_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) set_gdbarch_long_double_format (gdbarch, floatformats_ibm_long_double); break; default: - internal_error (_("unknown ABI in switch")); + internal_error (_ ("unknown ABI in switch")); } /* GCC creates a pseudo-section whose name specifies the size of @@ -8649,7 +8513,7 @@ mips_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) set_gdbarch_ptr_bit (gdbarch, long_bit); break; default: - internal_error (_("unknown ABI in switch")); + internal_error (_ ("unknown ABI in switch")); } } } @@ -8727,14 +8591,14 @@ mips_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) set_gdbarch_print_insn (gdbarch, gdb_print_insn_mips); if (mips_abi == MIPS_ABI_N64) - set_gdbarch_disassembler_options_implicit - (gdbarch, (const char *) mips_disassembler_options_n64); + set_gdbarch_disassembler_options_implicit ( + gdbarch, (const char *) mips_disassembler_options_n64); else if (mips_abi == MIPS_ABI_N32) - set_gdbarch_disassembler_options_implicit - (gdbarch, (const char *) mips_disassembler_options_n32); + set_gdbarch_disassembler_options_implicit ( + gdbarch, (const char *) mips_disassembler_options_n32); else - set_gdbarch_disassembler_options_implicit - (gdbarch, (const char *) mips_disassembler_options_o32); + set_gdbarch_disassembler_options_implicit ( + gdbarch, (const char *) mips_disassembler_options_o32); set_gdbarch_disassembler_options (gdbarch, &mips_disassembler_options); set_gdbarch_valid_disassembler_options (gdbarch, disassembler_options_mips ()); @@ -8813,8 +8677,8 @@ mips_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) value_of_mips_user_reg, &mips_n32_n64_aliases[i].regnum); else for (i = 0; i < ARRAY_SIZE (mips_o32_aliases); i++) - user_reg_add (gdbarch, mips_o32_aliases[i].name, - value_of_mips_user_reg, &mips_o32_aliases[i].regnum); + user_reg_add (gdbarch, mips_o32_aliases[i].name, value_of_mips_user_reg, + &mips_o32_aliases[i].regnum); /* Add some other standard aliases. */ for (i = 0; i < ARRAY_SIZE (mips_register_aliases); i++) @@ -8823,15 +8687,15 @@ mips_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) for (i = 0; i < ARRAY_SIZE (mips_numeric_register_aliases); i++) user_reg_add (gdbarch, mips_numeric_register_aliases[i].name, - value_of_mips_user_reg, + value_of_mips_user_reg, &mips_numeric_register_aliases[i].regnum); return gdbarch; } static void -mips_abi_update (const char *ignore_args, - int from_tty, struct cmd_list_element *c) +mips_abi_update (const char *ignore_args, int from_tty, + struct cmd_list_element *c) { struct gdbarch_info info; @@ -8843,16 +8707,13 @@ mips_abi_update (const char *ignore_args, /* Print out which MIPS ABI is in use. */ static void -show_mips_abi (struct ui_file *file, - int from_tty, - struct cmd_list_element *ignored_cmd, - const char *ignored_value) +show_mips_abi (struct ui_file *file, int from_tty, + struct cmd_list_element *ignored_cmd, const char *ignored_value) { if (gdbarch_bfd_arch_info (target_gdbarch ())->arch != bfd_arch_mips) - gdb_printf - (file, - "The MIPS ABI is unknown because the current architecture " - "is not MIPS.\n"); + gdb_printf (file, + "The MIPS ABI is unknown because the current architecture " + "is not MIPS.\n"); else { enum mips_abi global_abi = global_mips_abi (); @@ -8860,15 +8721,14 @@ show_mips_abi (struct ui_file *file, const char *actual_abi_str = mips_abi_strings[actual_abi]; if (global_abi == MIPS_ABI_UNKNOWN) - gdb_printf - (file, - "The MIPS ABI is set automatically (currently \"%s\").\n", - actual_abi_str); + gdb_printf (file, + "The MIPS ABI is set automatically (currently \"%s\").\n", + actual_abi_str); else if (global_abi == actual_abi) - gdb_printf - (file, - "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n", - actual_abi_str); + gdb_printf ( + file, + "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n", + actual_abi_str); else { /* Probably shouldn't happen... */ @@ -8886,8 +8746,7 @@ static void show_mips_compression (struct ui_file *file, int from_tty, struct cmd_list_element *c, const char *value) { - gdb_printf (file, _("The compressed ISA encoding used is %s.\n"), - value); + gdb_printf (file, _ ("The compressed ISA encoding used is %s.\n"), value); } /* Return a textual name for MIPS FPU type FPU_TYPE. */ @@ -8937,37 +8796,29 @@ mips_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file) } /* Determine the size of a pointer. */ ef_mips_32bitmode = (tdep->elf_flags & EF_MIPS_32BITMODE); - gdb_printf (file, - "mips_dump_tdep: tdep->elf_flags = 0x%x\n", + gdb_printf (file, "mips_dump_tdep: tdep->elf_flags = 0x%x\n", tdep->elf_flags); - gdb_printf (file, - "mips_dump_tdep: ef_mips_32bitmode = %d\n", + gdb_printf (file, "mips_dump_tdep: ef_mips_32bitmode = %d\n", ef_mips_32bitmode); - gdb_printf (file, - "mips_dump_tdep: ef_mips_arch = %d\n", - ef_mips_arch); - gdb_printf (file, - "mips_dump_tdep: tdep->mips_abi = %d (%s)\n", + gdb_printf (file, "mips_dump_tdep: ef_mips_arch = %d\n", ef_mips_arch); + gdb_printf (file, "mips_dump_tdep: tdep->mips_abi = %d (%s)\n", tdep->mips_abi, mips_abi_strings[tdep->mips_abi]); gdb_printf (file, "mips_dump_tdep: " "mips_mask_address_p() %d (default %d)\n", - mips_mask_address_p (tdep), - tdep->default_mask_address_p); + mips_mask_address_p (tdep), tdep->default_mask_address_p); } - gdb_printf (file, - "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n", + gdb_printf (file, "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n", MIPS_DEFAULT_FPU_TYPE, mips_fpu_type_str (MIPS_DEFAULT_FPU_TYPE)); - gdb_printf (file, "mips_dump_tdep: MIPS_EABI = %d\n", - mips_eabi (gdbarch)); - gdb_printf (file, - "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n", + gdb_printf (file, "mips_dump_tdep: MIPS_EABI = %d\n", mips_eabi (gdbarch)); + gdb_printf (file, "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n", mips_get_fpu_type (gdbarch), mips_fpu_type_str (mips_get_fpu_type (gdbarch))); } void _initialize_mips_tdep (); + void _initialize_mips_tdep () { @@ -8976,7 +8827,7 @@ _initialize_mips_tdep () mips_abi_string = mips_abi_strings[MIPS_ABI_UNKNOWN]; if (MIPS_ABI_LAST + 1 != sizeof (mips_abi_strings) / sizeof (mips_abi_strings[0])) - internal_error (_("mips_abi_strings out of sync")); + internal_error (_ ("mips_abi_strings out of sync")); gdbarch_register (bfd_arch_mips, mips_gdbarch_init, mips_dump_tdep); @@ -8990,16 +8841,18 @@ _initialize_mips_tdep () /* Add root prefix command for all "set mips"/"show mips" commands. */ add_setshow_prefix_cmd ("mips", no_class, - _("Various MIPS specific commands."), - _("Various MIPS specific commands."), - &setmipscmdlist, &showmipscmdlist, - &setlist, &showlist); + _ ("Various MIPS specific commands."), + _ ("Various MIPS specific commands."), + &setmipscmdlist, &showmipscmdlist, &setlist, + &showlist); /* Allow the user to override the ABI. */ add_setshow_enum_cmd ("abi", class_obscure, mips_abi_strings, - &mips_abi_string, _("\ -Set the MIPS ABI used by this program."), _("\ -Show the MIPS ABI used by this program."), _("\ + &mips_abi_string, _ ("\ +Set the MIPS ABI used by this program."), + _ ("\ +Show the MIPS ABI used by this program."), + _ ("\ This option can be set to one of:\n\ auto - the default ABI associated with the current binary\n\ o32\n\ @@ -9008,64 +8861,67 @@ This option can be set to one of:\n\ n64\n\ eabi32\n\ eabi64"), - mips_abi_update, - show_mips_abi, - &setmipscmdlist, &showmipscmdlist); + mips_abi_update, show_mips_abi, &setmipscmdlist, + &showmipscmdlist); /* Allow the user to set the ISA to assume for compressed code if ELF file flags don't tell or there is no program file selected. This setting is updated whenever unambiguous ELF file flags are interpreted, and carried over to subsequent sessions. */ add_setshow_enum_cmd ("compression", class_obscure, mips_compression_strings, - &mips_compression_string, _("\ -Set the compressed ISA encoding used by MIPS code."), _("\ -Show the compressed ISA encoding used by MIPS code."), _("\ + &mips_compression_string, _ ("\ +Set the compressed ISA encoding used by MIPS code."), + _ ("\ +Show the compressed ISA encoding used by MIPS code."), + _ ("\ Select the compressed ISA encoding used in functions that have no symbol\n\ information available. The encoding can be set to either of:\n\ mips16\n\ micromips\n\ and is updated automatically from ELF file flags if available."), - mips_abi_update, - show_mips_compression, + mips_abi_update, show_mips_compression, &setmipscmdlist, &showmipscmdlist); /* Let the user turn off floating point and set the fence post for heuristic_proc_start. */ add_basic_prefix_cmd ("mipsfpu", class_support, - _("Set use of MIPS floating-point coprocessor."), + _ ("Set use of MIPS floating-point coprocessor."), &mipsfpulist, 0, &setlist); add_cmd ("single", class_support, set_mipsfpu_single_command, - _("Select single-precision MIPS floating-point coprocessor."), + _ ("Select single-precision MIPS floating-point coprocessor."), &mipsfpulist); cmd_list_element *set_mipsfpu_double_cmd = add_cmd ("double", class_support, set_mipsfpu_double_command, - _("Select double-precision MIPS floating-point coprocessor."), + _ ("Select double-precision MIPS floating-point coprocessor."), &mipsfpulist); add_alias_cmd ("on", set_mipsfpu_double_cmd, class_support, 1, &mipsfpulist); - add_alias_cmd ("yes", set_mipsfpu_double_cmd, class_support, 1, &mipsfpulist); + add_alias_cmd ("yes", set_mipsfpu_double_cmd, class_support, 1, + &mipsfpulist); add_alias_cmd ("1", set_mipsfpu_double_cmd, class_support, 1, &mipsfpulist); cmd_list_element *set_mipsfpu_none_cmd = add_cmd ("none", class_support, set_mipsfpu_none_command, - _("Select no MIPS floating-point coprocessor."), &mipsfpulist); + _ ("Select no MIPS floating-point coprocessor."), &mipsfpulist); add_alias_cmd ("off", set_mipsfpu_none_cmd, class_support, 1, &mipsfpulist); add_alias_cmd ("no", set_mipsfpu_none_cmd, class_support, 1, &mipsfpulist); add_alias_cmd ("0", set_mipsfpu_none_cmd, class_support, 1, &mipsfpulist); add_cmd ("auto", class_support, set_mipsfpu_auto_command, - _("Select MIPS floating-point coprocessor automatically."), + _ ("Select MIPS floating-point coprocessor automatically."), &mipsfpulist); add_cmd ("mipsfpu", class_support, show_mipsfpu_command, - _("Show current use of MIPS floating-point coprocessor target."), + _ ("Show current use of MIPS floating-point coprocessor target."), &showlist); /* We really would like to have both "0" and "unlimited" work, but command.c doesn't deal with that. So make it a var_zinteger because the user can always use "999999" or some such for unlimited. */ add_setshow_zinteger_cmd ("heuristic-fence-post", class_support, - &heuristic_fence_post, _("\ -Set the distance searched for the start of a function."), _("\ -Show the distance searched for the start of a function."), _("\ + &heuristic_fence_post, _ ("\ +Set the distance searched for the start of a function."), + _ ("\ +Show the distance searched for the start of a function."), + _ ("\ If you are debugging a stripped executable, GDB needs to search through the\n\ program for the start of a function. This command sets the distance of the\n\ search. The only need to set it is when debugging a stripped executable."), @@ -9076,23 +8932,25 @@ search. The only need to set it is when debugging a stripped executable."), /* Allow the user to control whether the upper bits of 64-bit addresses should be zeroed. */ - add_setshow_auto_boolean_cmd ("mask-address", no_class, - &mask_address_var, _("\ -Set zeroing of upper 32 bits of 64-bit addresses."), _("\ -Show zeroing of upper 32 bits of 64-bit addresses."), _("\ + add_setshow_auto_boolean_cmd ("mask-address", no_class, &mask_address_var, + _ ("\ +Set zeroing of upper 32 bits of 64-bit addresses."), + _ ("\ +Show zeroing of upper 32 bits of 64-bit addresses."), + _ ("\ Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to\n\ allow GDB to determine the correct value."), - NULL, show_mask_address, - &setmipscmdlist, &showmipscmdlist); + NULL, show_mask_address, &setmipscmdlist, + &showmipscmdlist); /* Allow the user to control the size of 32 bit registers within the raw remote packet. */ add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure, - &mips64_transfers_32bit_regs_p, _("\ + &mips64_transfers_32bit_regs_p, _ ("\ Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."), - _("\ + _ ("\ Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."), - _("\ + _ ("\ Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\ that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\ 64 bits for others. Use \"off\" to disable compatibility mode"), @@ -9103,13 +8961,13 @@ that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\ &setlist, &showlist); /* Debug this files internals. */ - add_setshow_zuinteger_cmd ("mips", class_maintenance, - &mips_debug, _("\ -Set mips debugging."), _("\ -Show mips debugging."), _("\ + add_setshow_zuinteger_cmd ("mips", class_maintenance, &mips_debug, _ ("\ +Set mips debugging."), + _ ("\ +Show mips debugging."), + _ ("\ When non-zero, mips specific debugging is enabled."), - NULL, - NULL, /* FIXME: i18n: Mips debugging is + NULL, NULL, /* FIXME: i18n: Mips debugging is currently %s. */ &setdebuglist, &showdebuglist); } |