diff options
Diffstat (limited to 'gdb/amd64-tdep.c')
| -rw-r--r-- | gdb/amd64-tdep.c | 825 |
1 files changed, 392 insertions, 433 deletions
diff --git a/gdb/amd64-tdep.c b/gdb/amd64-tdep.c index 328e001..73b76ee 100644 --- a/gdb/amd64-tdep.c +++ b/gdb/amd64-tdep.c @@ -60,110 +60,121 @@ /* Register information. */ -static const char * const amd64_register_names[] = -{ - "rax", "rbx", "rcx", "rdx", "rsi", "rdi", "rbp", "rsp", +static const char *const amd64_register_names[] = { + "rax", + "rbx", + "rcx", + "rdx", + "rsi", + "rdi", + "rbp", + "rsp", /* %r8 is indeed register number 8. */ - "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", - "rip", "eflags", "cs", "ss", "ds", "es", "fs", "gs", + "r8", + "r9", + "r10", + "r11", + "r12", + "r13", + "r14", + "r15", + "rip", + "eflags", + "cs", + "ss", + "ds", + "es", + "fs", + "gs", /* %st0 is register number 24. */ - "st0", "st1", "st2", "st3", "st4", "st5", "st6", "st7", - "fctrl", "fstat", "ftag", "fiseg", "fioff", "foseg", "fooff", "fop", + "st0", + "st1", + "st2", + "st3", + "st4", + "st5", + "st6", + "st7", + "fctrl", + "fstat", + "ftag", + "fiseg", + "fioff", + "foseg", + "fooff", + "fop", /* %xmm0 is register number 40. */ - "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", - "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", + "xmm0", + "xmm1", + "xmm2", + "xmm3", + "xmm4", + "xmm5", + "xmm6", + "xmm7", + "xmm8", + "xmm9", + "xmm10", + "xmm11", + "xmm12", + "xmm13", + "xmm14", + "xmm15", "mxcsr", }; -static const char * const amd64_ymm_names[] = -{ - "ymm0", "ymm1", "ymm2", "ymm3", - "ymm4", "ymm5", "ymm6", "ymm7", - "ymm8", "ymm9", "ymm10", "ymm11", - "ymm12", "ymm13", "ymm14", "ymm15" -}; +static const char *const amd64_ymm_names[] + = { "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", + "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15" }; -static const char * const amd64_ymm_avx512_names[] = -{ - "ymm16", "ymm17", "ymm18", "ymm19", - "ymm20", "ymm21", "ymm22", "ymm23", - "ymm24", "ymm25", "ymm26", "ymm27", - "ymm28", "ymm29", "ymm30", "ymm31" -}; +static const char *const amd64_ymm_avx512_names[] + = { "ymm16", "ymm17", "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", + "ymm24", "ymm25", "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31" }; -static const char * const amd64_ymmh_names[] = -{ - "ymm0h", "ymm1h", "ymm2h", "ymm3h", - "ymm4h", "ymm5h", "ymm6h", "ymm7h", - "ymm8h", "ymm9h", "ymm10h", "ymm11h", - "ymm12h", "ymm13h", "ymm14h", "ymm15h" -}; +static const char *const amd64_ymmh_names[] + = { "ymm0h", "ymm1h", "ymm2h", "ymm3h", "ymm4h", "ymm5h", + "ymm6h", "ymm7h", "ymm8h", "ymm9h", "ymm10h", "ymm11h", + "ymm12h", "ymm13h", "ymm14h", "ymm15h" }; -static const char * const amd64_ymmh_avx512_names[] = -{ - "ymm16h", "ymm17h", "ymm18h", "ymm19h", - "ymm20h", "ymm21h", "ymm22h", "ymm23h", - "ymm24h", "ymm25h", "ymm26h", "ymm27h", - "ymm28h", "ymm29h", "ymm30h", "ymm31h" -}; +static const char *const amd64_ymmh_avx512_names[] + = { "ymm16h", "ymm17h", "ymm18h", "ymm19h", "ymm20h", "ymm21h", + "ymm22h", "ymm23h", "ymm24h", "ymm25h", "ymm26h", "ymm27h", + "ymm28h", "ymm29h", "ymm30h", "ymm31h" }; -static const char * const amd64_mpx_names[] = -{ - "bnd0raw", "bnd1raw", "bnd2raw", "bnd3raw", "bndcfgu", "bndstatus" -}; +static const char *const amd64_mpx_names[] + = { "bnd0raw", "bnd1raw", "bnd2raw", "bnd3raw", "bndcfgu", "bndstatus" }; -static const char * const amd64_k_names[] = -{ - "k0", "k1", "k2", "k3", - "k4", "k5", "k6", "k7" -}; +static const char *const amd64_k_names[] + = { "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7" }; -static const char * const amd64_zmmh_names[] = -{ - "zmm0h", "zmm1h", "zmm2h", "zmm3h", - "zmm4h", "zmm5h", "zmm6h", "zmm7h", - "zmm8h", "zmm9h", "zmm10h", "zmm11h", - "zmm12h", "zmm13h", "zmm14h", "zmm15h", - "zmm16h", "zmm17h", "zmm18h", "zmm19h", - "zmm20h", "zmm21h", "zmm22h", "zmm23h", - "zmm24h", "zmm25h", "zmm26h", "zmm27h", - "zmm28h", "zmm29h", "zmm30h", "zmm31h" -}; +static const char *const amd64_zmmh_names[] + = { "zmm0h", "zmm1h", "zmm2h", "zmm3h", "zmm4h", "zmm5h", "zmm6h", + "zmm7h", "zmm8h", "zmm9h", "zmm10h", "zmm11h", "zmm12h", "zmm13h", + "zmm14h", "zmm15h", "zmm16h", "zmm17h", "zmm18h", "zmm19h", "zmm20h", + "zmm21h", "zmm22h", "zmm23h", "zmm24h", "zmm25h", "zmm26h", "zmm27h", + "zmm28h", "zmm29h", "zmm30h", "zmm31h" }; -static const char * const amd64_zmm_names[] = -{ - "zmm0", "zmm1", "zmm2", "zmm3", - "zmm4", "zmm5", "zmm6", "zmm7", - "zmm8", "zmm9", "zmm10", "zmm11", - "zmm12", "zmm13", "zmm14", "zmm15", - "zmm16", "zmm17", "zmm18", "zmm19", - "zmm20", "zmm21", "zmm22", "zmm23", - "zmm24", "zmm25", "zmm26", "zmm27", - "zmm28", "zmm29", "zmm30", "zmm31" -}; +static const char *const amd64_zmm_names[] + = { "zmm0", "zmm1", "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", + "zmm8", "zmm9", "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", + "zmm16", "zmm17", "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", + "zmm24", "zmm25", "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31" }; -static const char * const amd64_xmm_avx512_names[] = { - "xmm16", "xmm17", "xmm18", "xmm19", - "xmm20", "xmm21", "xmm22", "xmm23", - "xmm24", "xmm25", "xmm26", "xmm27", - "xmm28", "xmm29", "xmm30", "xmm31" -}; +static const char *const amd64_xmm_avx512_names[] + = { "xmm16", "xmm17", "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", + "xmm24", "xmm25", "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31" }; -static const char * const amd64_pkeys_names[] = { - "pkru" -}; +static const char *const amd64_pkeys_names[] = { "pkru" }; /* DWARF Register Number Mapping as defined in the System V psABI, section 3.6. */ -static int amd64_dwarf_regmap[] = -{ +static int amd64_dwarf_regmap[] = { /* General Purpose Registers RAX, RDX, RCX, RBX, RSI, RDI. */ - AMD64_RAX_REGNUM, AMD64_RDX_REGNUM, - AMD64_RCX_REGNUM, AMD64_RBX_REGNUM, + AMD64_RAX_REGNUM, AMD64_RDX_REGNUM, AMD64_RCX_REGNUM, AMD64_RBX_REGNUM, AMD64_RSI_REGNUM, AMD64_RDI_REGNUM, /* Frame Pointer Register RBP. */ @@ -173,34 +184,31 @@ static int amd64_dwarf_regmap[] = AMD64_RSP_REGNUM, /* Extended Integer Registers 8 - 15. */ - AMD64_R8_REGNUM, /* %r8 */ - AMD64_R9_REGNUM, /* %r9 */ - AMD64_R10_REGNUM, /* %r10 */ - AMD64_R11_REGNUM, /* %r11 */ - AMD64_R12_REGNUM, /* %r12 */ - AMD64_R13_REGNUM, /* %r13 */ - AMD64_R14_REGNUM, /* %r14 */ - AMD64_R15_REGNUM, /* %r15 */ + AMD64_R8_REGNUM, /* %r8 */ + AMD64_R9_REGNUM, /* %r9 */ + AMD64_R10_REGNUM, /* %r10 */ + AMD64_R11_REGNUM, /* %r11 */ + AMD64_R12_REGNUM, /* %r12 */ + AMD64_R13_REGNUM, /* %r13 */ + AMD64_R14_REGNUM, /* %r14 */ + AMD64_R15_REGNUM, /* %r15 */ /* Return Address RA. Mapped to RIP. */ AMD64_RIP_REGNUM, /* SSE Registers 0 - 7. */ - AMD64_XMM0_REGNUM + 0, AMD64_XMM1_REGNUM, - AMD64_XMM0_REGNUM + 2, AMD64_XMM0_REGNUM + 3, - AMD64_XMM0_REGNUM + 4, AMD64_XMM0_REGNUM + 5, + AMD64_XMM0_REGNUM + 0, AMD64_XMM1_REGNUM, AMD64_XMM0_REGNUM + 2, + AMD64_XMM0_REGNUM + 3, AMD64_XMM0_REGNUM + 4, AMD64_XMM0_REGNUM + 5, AMD64_XMM0_REGNUM + 6, AMD64_XMM0_REGNUM + 7, /* Extended SSE Registers 8 - 15. */ - AMD64_XMM0_REGNUM + 8, AMD64_XMM0_REGNUM + 9, - AMD64_XMM0_REGNUM + 10, AMD64_XMM0_REGNUM + 11, - AMD64_XMM0_REGNUM + 12, AMD64_XMM0_REGNUM + 13, + AMD64_XMM0_REGNUM + 8, AMD64_XMM0_REGNUM + 9, AMD64_XMM0_REGNUM + 10, + AMD64_XMM0_REGNUM + 11, AMD64_XMM0_REGNUM + 12, AMD64_XMM0_REGNUM + 13, AMD64_XMM0_REGNUM + 14, AMD64_XMM0_REGNUM + 15, /* Floating Point Registers 0-7. */ - AMD64_ST0_REGNUM + 0, AMD64_ST0_REGNUM + 1, - AMD64_ST0_REGNUM + 2, AMD64_ST0_REGNUM + 3, - AMD64_ST0_REGNUM + 4, AMD64_ST0_REGNUM + 5, + AMD64_ST0_REGNUM + 0, AMD64_ST0_REGNUM + 1, AMD64_ST0_REGNUM + 2, + AMD64_ST0_REGNUM + 3, AMD64_ST0_REGNUM + 4, AMD64_ST0_REGNUM + 5, AMD64_ST0_REGNUM + 6, AMD64_ST0_REGNUM + 7, /* MMX Registers 0 - 7. @@ -213,33 +221,21 @@ static int amd64_dwarf_regmap[] = AMD64_EFLAGS_REGNUM, /* Selector Registers. */ - AMD64_ES_REGNUM, - AMD64_CS_REGNUM, - AMD64_SS_REGNUM, - AMD64_DS_REGNUM, - AMD64_FS_REGNUM, - AMD64_GS_REGNUM, - -1, - -1, + AMD64_ES_REGNUM, AMD64_CS_REGNUM, AMD64_SS_REGNUM, AMD64_DS_REGNUM, + AMD64_FS_REGNUM, AMD64_GS_REGNUM, -1, -1, /* Segment Base Address Registers. */ - -1, - -1, - -1, - -1, + -1, -1, -1, -1, /* Special Selector Registers. */ - -1, - -1, + -1, -1, /* Floating Point Control Registers. */ - AMD64_MXCSR_REGNUM, - AMD64_FCTRL_REGNUM, - AMD64_FSTAT_REGNUM + AMD64_MXCSR_REGNUM, AMD64_FCTRL_REGNUM, AMD64_FSTAT_REGNUM }; -static const int amd64_dwarf_regmap_len = - (sizeof (amd64_dwarf_regmap) / sizeof (amd64_dwarf_regmap[0])); +static const int amd64_dwarf_regmap_len + = (sizeof (amd64_dwarf_regmap) / sizeof (amd64_dwarf_regmap[0])); /* Convert DWARF register number REG to the appropriate register number used by GDB. */ @@ -254,8 +250,7 @@ amd64_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg) if (reg >= 0 && reg < amd64_dwarf_regmap_len) regnum = amd64_dwarf_regmap[reg]; - if (ymm0_regnum >= 0 - && i386_xmm_regnum_p (gdbarch, regnum)) + if (ymm0_regnum >= 0 && i386_xmm_regnum_p (gdbarch, regnum)) regnum += ymm0_regnum - I387_XMM0_REGNUM (tdep); return regnum; @@ -263,28 +258,27 @@ amd64_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg) /* Map architectural register numbers to gdb register numbers. */ -static const int amd64_arch_regmap[16] = -{ - AMD64_RAX_REGNUM, /* %rax */ - AMD64_RCX_REGNUM, /* %rcx */ - AMD64_RDX_REGNUM, /* %rdx */ - AMD64_RBX_REGNUM, /* %rbx */ - AMD64_RSP_REGNUM, /* %rsp */ - AMD64_RBP_REGNUM, /* %rbp */ - AMD64_RSI_REGNUM, /* %rsi */ - AMD64_RDI_REGNUM, /* %rdi */ - AMD64_R8_REGNUM, /* %r8 */ - AMD64_R9_REGNUM, /* %r9 */ - AMD64_R10_REGNUM, /* %r10 */ - AMD64_R11_REGNUM, /* %r11 */ - AMD64_R12_REGNUM, /* %r12 */ - AMD64_R13_REGNUM, /* %r13 */ - AMD64_R14_REGNUM, /* %r14 */ - AMD64_R15_REGNUM /* %r15 */ +static const int amd64_arch_regmap[16] = { + AMD64_RAX_REGNUM, /* %rax */ + AMD64_RCX_REGNUM, /* %rcx */ + AMD64_RDX_REGNUM, /* %rdx */ + AMD64_RBX_REGNUM, /* %rbx */ + AMD64_RSP_REGNUM, /* %rsp */ + AMD64_RBP_REGNUM, /* %rbp */ + AMD64_RSI_REGNUM, /* %rsi */ + AMD64_RDI_REGNUM, /* %rdi */ + AMD64_R8_REGNUM, /* %r8 */ + AMD64_R9_REGNUM, /* %r9 */ + AMD64_R10_REGNUM, /* %r10 */ + AMD64_R11_REGNUM, /* %r11 */ + AMD64_R12_REGNUM, /* %r12 */ + AMD64_R13_REGNUM, /* %r13 */ + AMD64_R14_REGNUM, /* %r14 */ + AMD64_R15_REGNUM /* %r15 */ }; -static const int amd64_arch_regmap_len = - (sizeof (amd64_arch_regmap) / sizeof (amd64_arch_regmap[0])); +static const int amd64_arch_regmap_len + = (sizeof (amd64_arch_regmap) / sizeof (amd64_arch_regmap[0])); /* Convert architectural register number REG to the appropriate register number used by GDB. */ @@ -299,32 +293,25 @@ amd64_arch_reg_to_regnum (int reg) /* Register names for byte pseudo-registers. */ -static const char * const amd64_byte_names[] = -{ - "al", "bl", "cl", "dl", "sil", "dil", "bpl", "spl", - "r8l", "r9l", "r10l", "r11l", "r12l", "r13l", "r14l", "r15l", - "ah", "bh", "ch", "dh" -}; +static const char *const amd64_byte_names[] + = { "al", "bl", "cl", "dl", "sil", "dil", "bpl", + "spl", "r8l", "r9l", "r10l", "r11l", "r12l", "r13l", + "r14l", "r15l", "ah", "bh", "ch", "dh" }; /* Number of lower byte registers. */ #define AMD64_NUM_LOWER_BYTE_REGS 16 /* Register names for word pseudo-registers. */ -static const char * const amd64_word_names[] = -{ - "ax", "bx", "cx", "dx", "si", "di", "bp", "", - "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w" -}; +static const char *const amd64_word_names[] + = { "ax", "bx", "cx", "dx", "si", "di", "bp", "", + "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w" }; /* Register names for dword pseudo-registers. */ -static const char * const amd64_dword_names[] = -{ - "eax", "ebx", "ecx", "edx", "esi", "edi", "ebp", "esp", - "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d", - "eip" -}; +static const char *const amd64_dword_names[] + = { "eax", "ebx", "ecx", "edx", "esi", "edi", "ebp", "esp", "r8d", + "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d", "eip" }; /* Return the name of register REGNUM. */ @@ -350,8 +337,7 @@ amd64_pseudo_register_name (struct gdbarch *gdbarch, int regnum) static struct value * amd64_pseudo_register_read_value (struct gdbarch *gdbarch, - readable_regcache *regcache, - int regnum) + readable_regcache *regcache, int regnum) { i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch); @@ -375,8 +361,8 @@ amd64_pseudo_register_read_value (struct gdbarch *gdbarch, if (status == REG_VALID) memcpy (buf, raw_buf + 1, 1); else - mark_value_bytes_unavailable (result_value, 0, - value_type (result_value)->length ()); + mark_value_bytes_unavailable ( + result_value, 0, value_type (result_value)->length ()); } else { @@ -385,8 +371,8 @@ amd64_pseudo_register_read_value (struct gdbarch *gdbarch, if (status == REG_VALID) memcpy (buf, raw_buf, 1); else - mark_value_bytes_unavailable (result_value, 0, - value_type (result_value)->length ()); + mark_value_bytes_unavailable ( + result_value, 0, value_type (result_value)->length ()); } } else if (i386_dword_regnum_p (gdbarch, regnum)) @@ -410,8 +396,8 @@ amd64_pseudo_register_read_value (struct gdbarch *gdbarch, static void amd64_pseudo_register_write (struct gdbarch *gdbarch, - struct regcache *regcache, - int regnum, const gdb_byte *buf) + struct regcache *regcache, int regnum, + const gdb_byte *buf) { i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch); @@ -488,8 +474,6 @@ amd64_ax_pseudo_register_collect (struct gdbarch *gdbarch, return i386_ax_pseudo_register_collect (gdbarch, ax, regnum); } - - /* Register classes as defined in the psABI. */ enum amd64_reg_class @@ -540,15 +524,15 @@ amd64_merge_classes (enum amd64_reg_class class1, enum amd64_reg_class class2) return AMD64_SSE; } -static void amd64_classify (struct type *type, enum amd64_reg_class theclass[2]); +static void amd64_classify (struct type *type, + enum amd64_reg_class theclass[2]); /* Return true if TYPE is a structure or union with unaligned fields. */ static bool amd64_has_unaligned_fields (struct type *type) { - if (type->code () == TYPE_CODE_STRUCT - || type->code () == TYPE_CODE_UNION) + if (type->code () == TYPE_CODE_STRUCT || type->code () == TYPE_CODE_UNION) { for (int i = 0; i < type->num_fields (); i++) { @@ -558,8 +542,7 @@ amd64_has_unaligned_fields (struct type *type) empty structures), and bitfields (these are handled by the caller). */ if (field_is_static (&type->field (i)) - || (TYPE_FIELD_BITSIZE (type, i) == 0 - && subtype->length () == 0) + || (TYPE_FIELD_BITSIZE (type, i) == 0 && subtype->length () == 0) || TYPE_FIELD_PACKED (type, i)) continue; @@ -570,7 +553,7 @@ amd64_has_unaligned_fields (struct type *type) int align = type_align (subtype); if (align == 0) - error (_("could not determine alignment of type")); + error (_ ("could not determine alignment of type")); int bytepos = bitpos / 8; if (bytepos % align != 0) @@ -666,8 +649,7 @@ amd64_classify_aggregate (struct type *type, enum amd64_reg_class theclass[2]) loc_bitpos attributes, which will cause an assert to trigger within the unaligned field check. As classes with virtual bases are not trivially copyable, checking that first avoids this problem. */ - if (TYPE_HAS_DYNAMIC_LENGTH (type) - || type->length () > 16 + if (TYPE_HAS_DYNAMIC_LENGTH (type) || type->length () > 16 || !language_pass_by_reference (type).trivially_copyable || amd64_has_unaligned_fields (type)) { @@ -735,8 +717,8 @@ amd64_classify (struct type *type, enum amd64_reg_class theclass[2]) class. */ if ((code == TYPE_CODE_INT || code == TYPE_CODE_ENUM || code == TYPE_CODE_BOOL || code == TYPE_CODE_RANGE - || code == TYPE_CODE_CHAR - || code == TYPE_CODE_PTR || TYPE_IS_REFERENCE (type)) + || code == TYPE_CODE_CHAR || code == TYPE_CODE_PTR + || TYPE_IS_REFERENCE (type)) && (len == 1 || len == 2 || len == 4 || len == 8)) theclass[0] = AMD64_INTEGER; @@ -925,27 +907,24 @@ amd64_return_value (struct gdbarch *gdbarch, struct value *function, return RETURN_VALUE_REGISTER_CONVENTION; } - static CORE_ADDR -amd64_push_arguments (struct regcache *regcache, int nargs, struct value **args, - CORE_ADDR sp, function_call_return_method return_method) -{ - static int integer_regnum[] = - { - AMD64_RDI_REGNUM, /* %rdi */ - AMD64_RSI_REGNUM, /* %rsi */ - AMD64_RDX_REGNUM, /* %rdx */ - AMD64_RCX_REGNUM, /* %rcx */ - AMD64_R8_REGNUM, /* %r8 */ - AMD64_R9_REGNUM /* %r9 */ +amd64_push_arguments (struct regcache *regcache, int nargs, + struct value **args, CORE_ADDR sp, + function_call_return_method return_method) +{ + static int integer_regnum[] = { + AMD64_RDI_REGNUM, /* %rdi */ + AMD64_RSI_REGNUM, /* %rsi */ + AMD64_RDX_REGNUM, /* %rdx */ + AMD64_RCX_REGNUM, /* %rcx */ + AMD64_R8_REGNUM, /* %r8 */ + AMD64_R9_REGNUM /* %r9 */ }; - static int sse_regnum[] = - { + static int sse_regnum[] = { /* %xmm0 ... %xmm7 */ - AMD64_XMM0_REGNUM + 0, AMD64_XMM1_REGNUM, - AMD64_XMM0_REGNUM + 2, AMD64_XMM0_REGNUM + 3, - AMD64_XMM0_REGNUM + 4, AMD64_XMM0_REGNUM + 5, + AMD64_XMM0_REGNUM + 0, AMD64_XMM1_REGNUM, AMD64_XMM0_REGNUM + 2, + AMD64_XMM0_REGNUM + 3, AMD64_XMM0_REGNUM + 4, AMD64_XMM0_REGNUM + 5, AMD64_XMM0_REGNUM + 6, AMD64_XMM0_REGNUM + 7, }; struct value **stack_args = XALLOCAVEC (struct value *, nargs); @@ -957,7 +936,7 @@ amd64_push_arguments (struct regcache *regcache, int nargs, struct value **args, int i; /* Reserve a register for the "hidden" argument. */ -if (return_method == return_method_struct) + if (return_method == return_method_struct) integer_reg++; for (i = 0; i < nargs; i++) @@ -1059,13 +1038,13 @@ if (return_method == return_method_struct) containing ellipsis (...) in the declaration) %al is used as hidden argument to specify the number of SSE registers used. */ regcache_raw_write_unsigned (regcache, AMD64_RAX_REGNUM, sse_reg); - return sp; + return sp; } static CORE_ADDR amd64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, - struct regcache *regcache, CORE_ADDR bp_addr, - int nargs, struct value **args, CORE_ADDR sp, + struct regcache *regcache, CORE_ADDR bp_addr, int nargs, + struct value **args, CORE_ADDR sp, function_call_return_method return_method, CORE_ADDR struct_addr) { @@ -1103,7 +1082,7 @@ amd64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, return sp + 16; } - + /* Displaced instruction handling. */ /* A partially decoded instruction. @@ -1129,8 +1108,9 @@ struct amd64_displaced_step_copy_insn_closure : public displaced_step_copy_insn_closure { amd64_displaced_step_copy_insn_closure (int insn_buf_len) - : insn_buf (insn_buf_len, 0) - {} + : insn_buf (insn_buf_len, 0) + { + } /* For rip-relative insns, saved copy of the reg we use instead of %rip. */ int tmp_used = 0; @@ -1151,22 +1131,38 @@ struct amd64_displaced_step_copy_insn_closure static const unsigned char onebyte_has_modrm[256] = { /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ /* ------------------------------- */ - /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */ - /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */ - /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */ - /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */ - /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */ - /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */ - /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */ - /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */ - /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */ - /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */ - /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */ - /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */ - /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */ - /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */ - /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */ - /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */ + /* 00 */ 1, 1, 1, 1, 0, 0, 0, 0, 1, + 1, 1, 1, 0, 0, 0, 0, /* 00 */ + /* 10 */ 1, 1, 1, 1, 0, 0, 0, 0, 1, + 1, 1, 1, 0, 0, 0, 0, /* 10 */ + /* 20 */ 1, 1, 1, 1, 0, 0, 0, 0, 1, + 1, 1, 1, 0, 0, 0, 0, /* 20 */ + /* 30 */ 1, 1, 1, 1, 0, 0, 0, 0, 1, + 1, 1, 1, 0, 0, 0, 0, /* 30 */ + /* 40 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, /* 40 */ + /* 50 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, /* 50 */ + /* 60 */ 0, 0, 1, 1, 0, 0, 0, 0, 0, + 1, 0, 1, 0, 0, 0, 0, /* 60 */ + /* 70 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, /* 70 */ + /* 80 */ 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, /* 80 */ + /* 90 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, /* 90 */ + /* a0 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, /* a0 */ + /* b0 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, /* b0 */ + /* c0 */ 1, 1, 0, 0, 1, 1, 1, 1, 0, + 0, 0, 0, 0, 0, 0, 0, /* c0 */ + /* d0 */ 1, 1, 1, 1, 0, 0, 0, 0, 1, + 1, 1, 1, 1, 1, 1, 1, /* d0 */ + /* e0 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, /* e0 */ + /* f0 */ 0, 0, 0, 0, 0, 0, 1, 1, 0, + 0, 0, 0, 0, 0, 1, 1 /* f0 */ /* ------------------------------- */ /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ }; @@ -1174,22 +1170,38 @@ static const unsigned char onebyte_has_modrm[256] = { static const unsigned char twobyte_has_modrm[256] = { /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ /* ------------------------------- */ - /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */ - /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */ - /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */ - /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */ - /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */ - /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */ - /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */ - /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */ - /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */ - /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */ - /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */ - /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */ - /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */ - /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */ - /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */ - /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */ + /* 00 */ 1, 1, 1, 1, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 1, 0, 1, /* 0f */ + /* 10 */ 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, /* 1f */ + /* 20 */ 1, 1, 1, 1, 1, 1, 1, 0, 1, + 1, 1, 1, 1, 1, 1, 1, /* 2f */ + /* 30 */ 0, 0, 0, 0, 0, 0, 0, 0, 1, + 0, 1, 0, 0, 0, 0, 0, /* 3f */ + /* 40 */ 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, /* 4f */ + /* 50 */ 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, /* 5f */ + /* 60 */ 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, /* 6f */ + /* 70 */ 1, 1, 1, 1, 1, 1, 1, 0, 1, + 1, 1, 1, 1, 1, 1, 1, /* 7f */ + /* 80 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, /* 8f */ + /* 90 */ 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, /* 9f */ + /* a0 */ 0, 0, 0, 1, 1, 1, 1, 1, 0, + 0, 0, 1, 1, 1, 1, 1, /* af */ + /* b0 */ 1, 1, 1, 1, 1, 1, 1, 1, 1, + 0, 1, 1, 1, 1, 1, 1, /* bf */ + /* c0 */ 1, 1, 1, 1, 1, 1, 1, 1, 0, + 0, 0, 0, 0, 0, 0, 0, /* cf */ + /* d0 */ 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, /* df */ + /* e0 */ 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, /* ef */ + /* f0 */ 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 0 /* ff */ /* ------------------------------- */ /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ }; @@ -1296,8 +1308,10 @@ amd64_get_unused_input_int_reg (const struct amd64_insn *details) if (have_sib) { - int base = SIB_BASE_FIELD (details->raw_insn[details->modrm_offset + 1]); - int idx = SIB_INDEX_FIELD (details->raw_insn[details->modrm_offset + 1]); + int base + = SIB_BASE_FIELD (details->raw_insn[details->modrm_offset + 1]); + int idx + = SIB_INDEX_FIELD (details->raw_insn[details->modrm_offset + 1]); used_regs_mask |= 1 << base; used_regs_mask |= 1 << idx; } @@ -1316,12 +1330,12 @@ amd64_get_unused_input_int_reg (const struct amd64_insn *details) for (i = 0; i < 8; ++i) { - if (! (used_regs_mask & (1 << i))) + if (!(used_regs_mask & (1 << i))) return i; } /* We shouldn't get here. */ - internal_error (_("unable to find free reg")); + internal_error (_ ("unable to find free reg")); } } @@ -1410,8 +1424,8 @@ amd64_get_insn_details (gdb_byte *insn, struct amd64_insn *details) static void fixup_riprel (struct gdbarch *gdbarch, - amd64_displaced_step_copy_insn_closure *dsc, - CORE_ADDR from, CORE_ADDR to, struct regcache *regs) + amd64_displaced_step_copy_insn_closure *dsc, CORE_ADDR from, + CORE_ADDR to, struct regcache *regs) { const struct amd64_insn *insn_details = &dsc->insn_details; int modrm_offset = insn_details->modrm_offset; @@ -1486,16 +1500,15 @@ fixup_displaced_copy (struct gdbarch *gdbarch, } displaced_step_copy_insn_closure_up -amd64_displaced_step_copy_insn (struct gdbarch *gdbarch, - CORE_ADDR from, CORE_ADDR to, - struct regcache *regs) +amd64_displaced_step_copy_insn (struct gdbarch *gdbarch, CORE_ADDR from, + CORE_ADDR to, struct regcache *regs) { int len = gdbarch_max_insn_length (gdbarch); /* Extra space for sentinels so fixup_{riprel,displaced_copy} don't have to continually watch for running off the end of the buffer. */ int fixup_sentinel_space = len; - std::unique_ptr<amd64_displaced_step_copy_insn_closure> dsc - (new amd64_displaced_step_copy_insn_closure (len + fixup_sentinel_space)); + std::unique_ptr<amd64_displaced_step_copy_insn_closure> dsc ( + new amd64_displaced_step_copy_insn_closure (len + fixup_sentinel_space)); gdb_byte *buf = &dsc->insn_buf[0]; struct amd64_insn *details = &dsc->insn_details; @@ -1524,8 +1537,8 @@ amd64_displaced_step_copy_insn (struct gdbarch *gdbarch, write_memory (to, buf, len); - displaced_debug_printf ("copy %s->%s: %s", - paddress (gdbarch, from), paddress (gdbarch, to), + displaced_debug_printf ("copy %s->%s: %s", paddress (gdbarch, from), + paddress (gdbarch, to), displaced_step_dump_bytes (buf, len).c_str ()); /* This is a work around for a problem with g++ 4.8. */ @@ -1711,8 +1724,8 @@ amd64_displaced_step_fixup (struct gdbarch *gdbarch, if (dsc->tmp_used) { - displaced_debug_printf ("restoring reg %d to %s", - dsc->tmp_regno, paddress (gdbarch, dsc->tmp_save)); + displaced_debug_printf ("restoring reg %d to %s", dsc->tmp_regno, + paddress (gdbarch, dsc->tmp_save)); regcache_cooked_write_unsigned (regs, dsc->tmp_regno, dsc->tmp_save); } @@ -1728,9 +1741,8 @@ amd64_displaced_step_fixup (struct gdbarch *gdbarch, the displaced instruction; make it relative to the original insn. Well, signal handler returns don't need relocation either, but we use the value of %rip to recognize those; see below. */ - if (! amd64_absolute_jmp_p (insn_details) - && ! amd64_absolute_call_p (insn_details) - && ! amd64_ret_p (insn_details)) + if (!amd64_absolute_jmp_p (insn_details) + && !amd64_absolute_call_p (insn_details) && !amd64_ret_p (insn_details)) { ULONGEST orig_rip; int insn_len; @@ -1829,8 +1841,8 @@ append_insns (CORE_ADDR *to, ULONGEST len, const gdb_byte *buf) } static void -amd64_relocate_instruction (struct gdbarch *gdbarch, - CORE_ADDR *to, CORE_ADDR oldloc) +amd64_relocate_instruction (struct gdbarch *gdbarch, CORE_ADDR *to, + CORE_ADDR oldloc) { enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); int len = gdbarch_max_insn_length (gdbarch); @@ -1897,8 +1909,7 @@ amd64_relocate_instruction (struct gdbarch *gdbarch, push_buf[i++] = 0x44; push_buf[i++] = 0x24; push_buf[i++] = 0x04; - store_unsigned_integer (&push_buf[i], 4, byte_order, - ret_addr >> 32); + store_unsigned_integer (&push_buf[i], 4, byte_order, ret_addr >> 32); i += 4; } gdb_assert (i <= sizeof (push_buf)); @@ -1948,9 +1959,8 @@ amd64_relocate_instruction (struct gdbarch *gdbarch, append_insns (to, insn_length, buf); } - /* The maximum number of saved registers. This should include %rip. */ -#define AMD64_NUM_SAVED_REGS AMD64_NUM_GREGS +#define AMD64_NUM_SAVED_REGS AMD64_NUM_GREGS struct amd64_frame_cache { @@ -2049,9 +2059,7 @@ amd64_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc, /* Check caller-saved saved register. The first instruction has to be "leaq 8(%rsp), %reg". */ - if ((buf[0] & 0xfb) == 0x48 - && buf[1] == 0x8d - && buf[3] == 0x24 + if ((buf[0] & 0xfb) == 0x48 && buf[1] == 0x8d && buf[3] == 0x24 && buf[4] == 0x8) { /* MOD must be binary 10 and R/M must be binary 100. */ @@ -2074,8 +2082,7 @@ amd64_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc, reg = 0; if ((buf[0] & 0xf8) == 0x50) offset = 0; - else if ((buf[0] & 0xf6) == 0x40 - && (buf[1] & 0xf8) == 0x50) + else if ((buf[0] & 0xf6) == 0x40 && (buf[1] & 0xf8) == 0x50) { /* Check the REX.B bit. */ if ((buf[0] & 1) != 0) @@ -2092,16 +2099,14 @@ amd64_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc, offset++; /* The next instruction has to be "leaq 16(%rsp), %reg". */ - if ((buf[offset] & 0xfb) != 0x48 - || buf[offset + 1] != 0x8d - || buf[offset + 3] != 0x24 - || buf[offset + 4] != 0x10) + if ((buf[offset] & 0xfb) != 0x48 || buf[offset + 1] != 0x8d + || buf[offset + 3] != 0x24 || buf[offset + 4] != 0x10) return pc; /* MOD must be binary 10 and R/M must be binary 100. */ if ((buf[offset + 2] & 0xc7) != 0x44) return pc; - + /* REG has register number. */ r = (buf[offset + 2] >> 3) & 7; @@ -2121,8 +2126,7 @@ amd64_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc, return pc; /* The next instruction has to be "andq $-XXX, %rsp". */ - if (buf[offset] != 0x48 - || buf[offset + 2] != 0xe4 + if (buf[offset] != 0x48 || buf[offset + 2] != 0xe4 || (buf[offset + 1] != 0x81 && buf[offset + 1] != 0x83)) return pc; @@ -2133,8 +2137,7 @@ amd64_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc, r = 0; if (buf[offset] == 0xff) offset++; - else if ((buf[offset] & 0xf6) == 0x40 - && buf[offset + 1] == 0xff) + else if ((buf[offset] & 0xf6) == 0x40 && buf[offset + 1] == 0xff) { /* Check the REX.B bit. */ if ((buf[offset] & 0x1) != 0) @@ -2146,8 +2149,7 @@ amd64_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc, /* 8bit -8 is 0xf8. REG must be binary 110 and MOD must be binary 01. */ - if (buf[offset + 1] != 0xf8 - || (buf[offset] & 0xf8) != 0x70) + if (buf[offset + 1] != 0xf8 || (buf[offset] & 0xf8) != 0x70) return pc; /* R/M has register. */ @@ -2167,7 +2169,7 @@ amd64_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc, static CORE_ADDR amd64_x32_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc, - struct amd64_frame_cache *cache) + struct amd64_frame_cache *cache) { /* There are 2 code sequences to re-align stack before the frame gets set up: @@ -2222,8 +2224,7 @@ amd64_x32_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc, /* Check caller-saved saved register. The first instruction has to be "leaq 8(%rsp), %reg" or "leal 8(%rsp), %reg". */ if (((buf[offset] & 0xfb) == 0x48 || (buf[offset] & 0xfb) == 0x40) - && buf[offset + 1] == 0x8d - && buf[offset + 3] == 0x24 + && buf[offset + 1] == 0x8d && buf[offset + 3] == 0x24 && buf[offset + 4] == 0x8) { /* MOD must be binary 10 and R/M must be binary 100. */ @@ -2244,8 +2245,7 @@ amd64_x32_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc, /* Check callee-saved saved register. The first instruction has to be "pushq %reg". */ reg = 0; - if ((buf[offset] & 0xf6) == 0x40 - && (buf[offset + 1] & 0xf8) == 0x50) + if ((buf[offset] & 0xf6) == 0x40 && (buf[offset + 1] & 0xf8) == 0x50) { /* Check the REX.B bit. */ if ((buf[offset] & 1) != 0) @@ -2268,15 +2268,14 @@ amd64_x32_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc, /* The next instruction has to be "leaq 16(%rsp), %reg" or "leal 16(%rsp), %reg". */ if (((buf[offset] & 0xfb) != 0x48 && (buf[offset] & 0xfb) != 0x40) - || buf[offset + 1] != 0x8d - || buf[offset + 3] != 0x24 + || buf[offset + 1] != 0x8d || buf[offset + 3] != 0x24 || buf[offset + 4] != 0x10) return pc; /* MOD must be binary 10 and R/M must be binary 100. */ if ((buf[offset + 2] & 0xc7) != 0x44) return pc; - + /* REG has register number. */ r = (buf[offset + 2] >> 3) & 7; @@ -2315,8 +2314,7 @@ amd64_x32_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc, r = 0; if (buf[offset] == 0xff) offset++; - else if ((buf[offset] & 0xf6) == 0x40 - && buf[offset + 1] == 0xff) + else if ((buf[offset] & 0xf6) == 0x40 && buf[offset + 1] == 0xff) { /* Check the REX.B bit. */ if ((buf[offset] & 0x1) != 0) @@ -2328,8 +2326,7 @@ amd64_x32_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc, /* 8bit -8 is 0xf8. REG must be binary 110 and MOD must be binary 01. */ - if (buf[offset + 1] != 0xf8 - || (buf[offset] & 0xf8) != 0x70) + if (buf[offset + 1] != 0xf8 || (buf[offset] & 0xf8) != 0x70) return pc; /* R/M has register. */ @@ -2367,9 +2364,8 @@ amd64_x32_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc, %rbp. */ static CORE_ADDR -amd64_analyze_prologue (struct gdbarch *gdbarch, - CORE_ADDR pc, CORE_ADDR current_pc, - struct amd64_frame_cache *cache) +amd64_analyze_prologue (struct gdbarch *gdbarch, CORE_ADDR pc, + CORE_ADDR current_pc, struct amd64_frame_cache *cache) { enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); /* The `endbr64` instruction. */ @@ -2408,7 +2404,7 @@ amd64_analyze_prologue (struct gdbarch *gdbarch, if (current_pc <= pc) return current_pc; - if (op == 0x55) /* pushq %rbp */ + if (op == 0x55) /* pushq %rbp */ { /* Take into account that we've executed the `pushq %rbp' that starts this instruction sequence. */ @@ -2478,8 +2474,8 @@ amd64_skip_xmm_prologue (CORE_ADDR pc, CORE_ADDR start_pc) start_pc_sal = find_pc_sect_line (start_pc, NULL, 0); if (start_pc_sal.symtab == NULL - || producer_is_gcc_ge_4 (start_pc_sal.symtab->compunit () - ->producer ()) < 6 + || producer_is_gcc_ge_4 (start_pc_sal.symtab->compunit ()->producer ()) + < 6 || start_pc_sal.pc != start_pc || pc >= start_pc_sal.end) return pc; @@ -2548,22 +2544,20 @@ amd64_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc) prologue and another one after. We trust clang and newer Intel compilers to emit usable line notes. */ if (post_prologue_pc - && (cust != NULL - && cust->producer () != nullptr + && (cust != NULL && cust->producer () != nullptr && (producer_is_llvm (cust->producer ()) - || producer_is_icc_ge_19 (cust->producer ())))) - return std::max (start_pc, post_prologue_pc); + || producer_is_icc_ge_19 (cust->producer ())))) + return std::max (start_pc, post_prologue_pc); } amd64_init_frame_cache (&cache); - pc = amd64_analyze_prologue (gdbarch, start_pc, 0xffffffffffffffffLL, - &cache); + pc + = amd64_analyze_prologue (gdbarch, start_pc, 0xffffffffffffffffLL, &cache); if (cache.frameless_p) return start_pc; return amd64_skip_xmm_prologue (pc, start_pc); } - /* Normal frames. */ @@ -2606,8 +2600,8 @@ amd64_frame_cache_1 (frame_info_ptr this_frame, else { get_frame_register (this_frame, AMD64_RSP_REGNUM, buf); - cache->base = extract_unsigned_integer (buf, 8, byte_order) - + cache->sp_offset; + cache->base + = extract_unsigned_integer (buf, 8, byte_order) + cache->sp_offset; } } else @@ -2661,11 +2655,9 @@ amd64_frame_cache (frame_info_ptr this_frame, void **this_cache) } static enum unwind_stop_reason -amd64_frame_unwind_stop_reason (frame_info_ptr this_frame, - void **this_cache) +amd64_frame_unwind_stop_reason (frame_info_ptr this_frame, void **this_cache) { - struct amd64_frame_cache *cache = - amd64_frame_cache (this_frame, this_cache); + struct amd64_frame_cache *cache = amd64_frame_cache (this_frame, this_cache); if (!cache->base_p) return UNWIND_UNAVAILABLE; @@ -2681,8 +2673,7 @@ static void amd64_frame_this_id (frame_info_ptr this_frame, void **this_cache, struct frame_id *this_id) { - struct amd64_frame_cache *cache = - amd64_frame_cache (this_frame, this_cache); + struct amd64_frame_cache *cache = amd64_frame_cache (this_frame, this_cache); if (!cache->base_p) (*this_id) = frame_id_build_unavailable_stack (cache->pc); @@ -2700,8 +2691,7 @@ amd64_frame_prev_register (frame_info_ptr this_frame, void **this_cache, int regnum) { struct gdbarch *gdbarch = get_frame_arch (this_frame); - struct amd64_frame_cache *cache = - amd64_frame_cache (this_frame, this_cache); + struct amd64_frame_cache *cache = amd64_frame_cache (this_frame, this_cache); gdb_assert (regnum >= 0); @@ -2715,23 +2705,20 @@ amd64_frame_prev_register (frame_info_ptr this_frame, void **this_cache, return frame_unwind_got_register (this_frame, regnum, regnum); } -static const struct frame_unwind amd64_frame_unwind = -{ - "amd64 prologue", - NORMAL_FRAME, - amd64_frame_unwind_stop_reason, - amd64_frame_this_id, - amd64_frame_prev_register, - NULL, - default_frame_sniffer -}; - +static const struct frame_unwind amd64_frame_unwind + = { "amd64 prologue", + NORMAL_FRAME, + amd64_frame_unwind_stop_reason, + amd64_frame_this_id, + amd64_frame_prev_register, + NULL, + default_frame_sniffer }; + /* Generate a bytecode expression to get the value of the saved PC. */ static void -amd64_gen_return_address (struct gdbarch *gdbarch, - struct agent_expr *ax, struct axs_value *value, - CORE_ADDR scope) +amd64_gen_return_address (struct gdbarch *gdbarch, struct agent_expr *ax, + struct axs_value *value, CORE_ADDR scope) { /* The following sequence assumes the traditional use of the base register. */ @@ -2741,7 +2728,6 @@ amd64_gen_return_address (struct gdbarch *gdbarch, value->type = register_type (gdbarch, AMD64_RIP_REGNUM); value->kind = axs_lvalue_memory; } - /* Signal trampolines. */ @@ -2793,8 +2779,8 @@ static enum unwind_stop_reason amd64_sigtramp_frame_unwind_stop_reason (frame_info_ptr this_frame, void **this_cache) { - struct amd64_frame_cache *cache = - amd64_sigtramp_frame_cache (this_frame, this_cache); + struct amd64_frame_cache *cache + = amd64_sigtramp_frame_cache (this_frame, this_cache); if (!cache->base_p) return UNWIND_UNAVAILABLE; @@ -2803,11 +2789,11 @@ amd64_sigtramp_frame_unwind_stop_reason (frame_info_ptr this_frame, } static void -amd64_sigtramp_frame_this_id (frame_info_ptr this_frame, - void **this_cache, struct frame_id *this_id) +amd64_sigtramp_frame_this_id (frame_info_ptr this_frame, void **this_cache, + struct frame_id *this_id) { - struct amd64_frame_cache *cache = - amd64_sigtramp_frame_cache (this_frame, this_cache); + struct amd64_frame_cache *cache + = amd64_sigtramp_frame_cache (this_frame, this_cache); if (!cache->base_p) (*this_id) = frame_id_build_unavailable_stack (get_frame_pc (this_frame)); @@ -2832,8 +2818,7 @@ amd64_sigtramp_frame_prev_register (frame_info_ptr this_frame, static int amd64_sigtramp_frame_sniffer (const struct frame_unwind *self, - frame_info_ptr this_frame, - void **this_cache) + frame_info_ptr this_frame, void **this_cache) { gdbarch *arch = get_frame_arch (this_frame); i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (arch); @@ -2861,34 +2846,26 @@ amd64_sigtramp_frame_sniffer (const struct frame_unwind *self, return 0; } -static const struct frame_unwind amd64_sigtramp_frame_unwind = -{ - "amd64 sigtramp", - SIGTRAMP_FRAME, - amd64_sigtramp_frame_unwind_stop_reason, - amd64_sigtramp_frame_this_id, - amd64_sigtramp_frame_prev_register, - NULL, - amd64_sigtramp_frame_sniffer -}; - +static const struct frame_unwind amd64_sigtramp_frame_unwind + = { "amd64 sigtramp", + SIGTRAMP_FRAME, + amd64_sigtramp_frame_unwind_stop_reason, + amd64_sigtramp_frame_this_id, + amd64_sigtramp_frame_prev_register, + NULL, + amd64_sigtramp_frame_sniffer }; static CORE_ADDR amd64_frame_base_address (frame_info_ptr this_frame, void **this_cache) { - struct amd64_frame_cache *cache = - amd64_frame_cache (this_frame, this_cache); + struct amd64_frame_cache *cache = amd64_frame_cache (this_frame, this_cache); return cache->base; } -static const struct frame_base amd64_frame_base = -{ - &amd64_frame_unwind, - amd64_frame_base_address, - amd64_frame_base_address, - amd64_frame_base_address -}; +static const struct frame_base amd64_frame_base + = { &amd64_frame_unwind, amd64_frame_base_address, amd64_frame_base_address, + amd64_frame_base_address }; /* Normal frames, but in a function epilogue. */ @@ -2909,9 +2886,9 @@ amd64_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc) return 0; if (target_read_memory (pc, &insn, 1)) - return 0; /* Can't read memory at pc. */ + return 0; /* Can't read memory at pc. */ - if (insn != 0xc3) /* 'ret' instruction. */ + if (insn != 0xc3) /* 'ret' instruction. */ return 0; return 1; @@ -2947,8 +2924,8 @@ amd64_epilogue_frame_cache (frame_info_ptr this_frame, void **this_cache) { /* Cache base will be %rsp plus cache->sp_offset (-8). */ get_frame_register (this_frame, AMD64_RSP_REGNUM, buf); - cache->base = extract_unsigned_integer (buf, 8, - byte_order) + cache->sp_offset; + cache->base + = extract_unsigned_integer (buf, 8, byte_order) + cache->sp_offset; /* Cache pc will be the frame func. */ cache->pc = get_frame_func (this_frame); @@ -2984,12 +2961,11 @@ amd64_epilogue_frame_unwind_stop_reason (frame_info_ptr this_frame, } static void -amd64_epilogue_frame_this_id (frame_info_ptr this_frame, - void **this_cache, +amd64_epilogue_frame_this_id (frame_info_ptr this_frame, void **this_cache, struct frame_id *this_id) { - struct amd64_frame_cache *cache = amd64_epilogue_frame_cache (this_frame, - this_cache); + struct amd64_frame_cache *cache + = amd64_epilogue_frame_cache (this_frame, this_cache); if (!cache->base_p) (*this_id) = frame_id_build_unavailable_stack (cache->pc); @@ -2997,16 +2973,14 @@ amd64_epilogue_frame_this_id (frame_info_ptr this_frame, (*this_id) = frame_id_build (cache->base + 16, cache->pc); } -static const struct frame_unwind amd64_epilogue_frame_unwind = -{ - "amd64 epilogue", - NORMAL_FRAME, - amd64_epilogue_frame_unwind_stop_reason, - amd64_epilogue_frame_this_id, - amd64_frame_prev_register, - NULL, - amd64_epilogue_frame_sniffer -}; +static const struct frame_unwind amd64_epilogue_frame_unwind + = { "amd64 epilogue", + NORMAL_FRAME, + amd64_epilogue_frame_unwind_stop_reason, + amd64_epilogue_frame_this_id, + amd64_frame_prev_register, + NULL, + amd64_epilogue_frame_sniffer }; static struct frame_id amd64_dummy_id (struct gdbarch *gdbarch, frame_info_ptr this_frame) @@ -3023,9 +2997,8 @@ amd64_dummy_id (struct gdbarch *gdbarch, frame_info_ptr this_frame) static CORE_ADDR amd64_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) { - return sp & -(CORE_ADDR)16; + return sp & -(CORE_ADDR) 16; } - /* Supply register REGNUM from the buffer specified by FPREGS and LEN in the floating-point register set REGSET to register cache @@ -3049,8 +3022,8 @@ amd64_supply_fpregset (const struct regset *regset, struct regcache *regcache, static void amd64_collect_fpregset (const struct regset *regset, - const struct regcache *regcache, - int regnum, void *fpregs, size_t len) + const struct regcache *regcache, int regnum, + void *fpregs, size_t len) { struct gdbarch *gdbarch = regcache->arch (); const i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch); @@ -3059,11 +3032,8 @@ amd64_collect_fpregset (const struct regset *regset, amd64_collect_fxsave (regcache, regnum, fpregs); } -const struct regset amd64_fpregset = - { - NULL, amd64_supply_fpregset, amd64_collect_fpregset - }; - +const struct regset amd64_fpregset + = { NULL, amd64_supply_fpregset, amd64_collect_fpregset }; /* Figure out where the longjmp will land. Slurp the jmp_buf out of %rdi. We expect its value to be a pointer to the jmp_buf structure @@ -3087,8 +3057,8 @@ amd64_get_longjmp_target (frame_info_ptr frame, CORE_ADDR *pc) return 0; get_frame_register (frame, AMD64_RDI_REGNUM, buf); - jb_addr= extract_typed_address - (buf, builtin_type (gdbarch)->builtin_data_ptr); + jb_addr + = extract_typed_address (buf, builtin_type (gdbarch)->builtin_data_ptr); if (target_read_memory (jb_addr + jb_pc_offset, buf, len)) return 0; @@ -3097,14 +3067,13 @@ amd64_get_longjmp_target (frame_info_ptr frame, CORE_ADDR *pc) return 1; } -static const int amd64_record_regmap[] = -{ - AMD64_RAX_REGNUM, AMD64_RCX_REGNUM, AMD64_RDX_REGNUM, AMD64_RBX_REGNUM, - AMD64_RSP_REGNUM, AMD64_RBP_REGNUM, AMD64_RSI_REGNUM, AMD64_RDI_REGNUM, - AMD64_R8_REGNUM, AMD64_R9_REGNUM, AMD64_R10_REGNUM, AMD64_R11_REGNUM, - AMD64_R12_REGNUM, AMD64_R13_REGNUM, AMD64_R14_REGNUM, AMD64_R15_REGNUM, - AMD64_RIP_REGNUM, AMD64_EFLAGS_REGNUM, AMD64_CS_REGNUM, AMD64_SS_REGNUM, - AMD64_DS_REGNUM, AMD64_ES_REGNUM, AMD64_FS_REGNUM, AMD64_GS_REGNUM +static const int amd64_record_regmap[] = { + AMD64_RAX_REGNUM, AMD64_RCX_REGNUM, AMD64_RDX_REGNUM, AMD64_RBX_REGNUM, + AMD64_RSP_REGNUM, AMD64_RBP_REGNUM, AMD64_RSI_REGNUM, AMD64_RDI_REGNUM, + AMD64_R8_REGNUM, AMD64_R9_REGNUM, AMD64_R10_REGNUM, AMD64_R11_REGNUM, + AMD64_R12_REGNUM, AMD64_R13_REGNUM, AMD64_R14_REGNUM, AMD64_R15_REGNUM, + AMD64_RIP_REGNUM, AMD64_EFLAGS_REGNUM, AMD64_CS_REGNUM, AMD64_SS_REGNUM, + AMD64_DS_REGNUM, AMD64_ES_REGNUM, AMD64_FS_REGNUM, AMD64_GS_REGNUM }; /* Implement the "in_indirect_branch_thunk" gdbarch function. */ @@ -3113,8 +3082,7 @@ static bool amd64_in_indirect_branch_thunk (struct gdbarch *gdbarch, CORE_ADDR pc) { return x86_in_indirect_branch_thunk (pc, amd64_register_names, - AMD64_RAX_REGNUM, - AMD64_RIP_REGNUM); + AMD64_RAX_REGNUM, AMD64_RIP_REGNUM); } void @@ -3125,17 +3093,17 @@ amd64_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch, const struct target_desc *tdesc = info.target_desc; static const char *const stap_integer_prefixes[] = { "$", NULL }; static const char *const stap_register_prefixes[] = { "%", NULL }; - static const char *const stap_register_indirection_prefixes[] = { "(", - NULL }; - static const char *const stap_register_indirection_suffixes[] = { ")", - NULL }; + static const char *const stap_register_indirection_prefixes[] + = { "(", NULL }; + static const char *const stap_register_indirection_suffixes[] + = { ")", NULL }; /* AMD64 generally uses `fxsave' instead of `fsave' for saving its floating-point registers. */ tdep->sizeof_fpregset = I387_SIZEOF_FXSAVE; tdep->fpregset = &amd64_fpregset; - if (! tdesc_has_registers (tdesc)) + if (!tdesc_has_registers (tdesc)) tdesc = default_tdesc; tdep->tdesc = tdesc; @@ -3193,8 +3161,7 @@ amd64_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch, set_gdbarch_pseudo_register_read_value (gdbarch, amd64_pseudo_register_read_value); - set_gdbarch_pseudo_register_write (gdbarch, - amd64_pseudo_register_write); + set_gdbarch_pseudo_register_write (gdbarch, amd64_pseudo_register_write); set_gdbarch_ax_pseudo_register_collect (gdbarch, amd64_ax_pseudo_register_collect); @@ -3217,10 +3184,10 @@ amd64_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch, set_gdbarch_num_regs (gdbarch, AMD64_NUM_REGS); /* Register numbers of various important registers. */ - set_gdbarch_sp_regnum (gdbarch, AMD64_RSP_REGNUM); /* %rsp */ - set_gdbarch_pc_regnum (gdbarch, AMD64_RIP_REGNUM); /* %rip */ + set_gdbarch_sp_regnum (gdbarch, AMD64_RSP_REGNUM); /* %rsp */ + set_gdbarch_pc_regnum (gdbarch, AMD64_RIP_REGNUM); /* %rip */ set_gdbarch_ps_regnum (gdbarch, AMD64_EFLAGS_REGNUM); /* %eflags */ - set_gdbarch_fp0_regnum (gdbarch, AMD64_ST0_REGNUM); /* %st(0) */ + set_gdbarch_fp0_regnum (gdbarch, AMD64_ST0_REGNUM); /* %st(0) */ /* The "default" register numbering scheme for AMD64 is referred to as the "DWARF Register Number Mapping" in the System V psABI. @@ -3270,12 +3237,11 @@ amd64_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch, /* SystemTap variables and functions. */ set_gdbarch_stap_integer_prefixes (gdbarch, stap_integer_prefixes); set_gdbarch_stap_register_prefixes (gdbarch, stap_register_prefixes); - set_gdbarch_stap_register_indirection_prefixes (gdbarch, - stap_register_indirection_prefixes); - set_gdbarch_stap_register_indirection_suffixes (gdbarch, - stap_register_indirection_suffixes); - set_gdbarch_stap_is_single_operand (gdbarch, - i386_stap_is_single_operand); + set_gdbarch_stap_register_indirection_prefixes ( + gdbarch, stap_register_indirection_prefixes); + set_gdbarch_stap_register_indirection_suffixes ( + gdbarch, stap_register_indirection_suffixes); + set_gdbarch_stap_is_single_operand (gdbarch, i386_stap_is_single_operand); set_gdbarch_stap_parse_special_token (gdbarch, i386_stap_parse_special_token); set_gdbarch_insn_is_call (gdbarch, amd64_insn_is_call); @@ -3293,8 +3259,8 @@ amd64_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch, static void amd64_none_init_abi (gdbarch_info info, gdbarch *arch) { - amd64_init_abi (info, arch, amd64_target_description (X86_XSTATE_SSE_MASK, - true)); + amd64_init_abi (info, arch, + amd64_target_description (X86_XSTATE_SSE_MASK, true)); } static struct type * @@ -3304,10 +3270,10 @@ amd64_x32_pseudo_register_type (struct gdbarch *gdbarch, int regnum) switch (regnum - tdep->eax_regnum) { - case AMD64_RBP_REGNUM: /* %ebp */ - case AMD64_RSP_REGNUM: /* %esp */ + case AMD64_RBP_REGNUM: /* %ebp */ + case AMD64_RSP_REGNUM: /* %esp */ return builtin_type (gdbarch)->builtin_data_ptr; - case AMD64_RIP_REGNUM: /* %eip */ + case AMD64_RIP_REGNUM: /* %eip */ return builtin_type (gdbarch)->builtin_func_ptr; } @@ -3343,24 +3309,24 @@ amd64_x32_none_init_abi (gdbarch_info info, gdbarch *arch) const struct target_desc * amd64_target_description (uint64_t xcr0, bool segments) { - static target_desc *amd64_tdescs \ - [2/*AVX*/][2/*MPX*/][2/*AVX512*/][2/*PKRU*/][2/*segments*/] = {}; + static target_desc *amd64_tdescs[2 /*AVX*/][2 /*MPX*/][2 /*AVX512*/] + [2 /*PKRU*/][2 /*segments*/] + = {}; target_desc **tdesc; tdesc = &amd64_tdescs[(xcr0 & X86_XSTATE_AVX) ? 1 : 0] - [(xcr0 & X86_XSTATE_MPX) ? 1 : 0] - [(xcr0 & X86_XSTATE_AVX512) ? 1 : 0] - [(xcr0 & X86_XSTATE_PKRU) ? 1 : 0] - [segments ? 1 : 0]; + [(xcr0 & X86_XSTATE_MPX) ? 1 : 0] + [(xcr0 & X86_XSTATE_AVX512) ? 1 : 0] + [(xcr0 & X86_XSTATE_PKRU) ? 1 : 0][segments ? 1 : 0]; if (*tdesc == NULL) - *tdesc = amd64_create_target_description (xcr0, false, false, - segments); + *tdesc = amd64_create_target_description (xcr0, false, false, segments); return *tdesc; } void _initialize_amd64_tdep (); + void _initialize_amd64_tdep () { @@ -3369,7 +3335,6 @@ _initialize_amd64_tdep () gdbarch_register_osabi (bfd_arch_i386, bfd_mach_x64_32, GDB_OSABI_NONE, amd64_x32_none_init_abi); } - /* The 64-bit FXSAVE format differs from the 32-bit format in the sense that the instruction pointer and data pointer are simply @@ -3384,16 +3349,14 @@ _initialize_amd64_tdep () reserved bits in *FXSAVE. */ void -amd64_supply_fxsave (struct regcache *regcache, int regnum, - const void *fxsave) +amd64_supply_fxsave (struct regcache *regcache, int regnum, const void *fxsave) { struct gdbarch *gdbarch = regcache->arch (); i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch); i387_supply_fxsave (regcache, regnum, fxsave); - if (fxsave - && gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 64) + if (fxsave && gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 64) { const gdb_byte *regs = (const gdb_byte *) fxsave; @@ -3407,16 +3370,14 @@ amd64_supply_fxsave (struct regcache *regcache, int regnum, /* Similar to amd64_supply_fxsave, but use XSAVE extended state. */ void -amd64_supply_xsave (struct regcache *regcache, int regnum, - const void *xsave) +amd64_supply_xsave (struct regcache *regcache, int regnum, const void *xsave) { struct gdbarch *gdbarch = regcache->arch (); i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch); i387_supply_xsave (regcache, regnum, xsave); - if (xsave - && gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 64) + if (xsave && gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 64) { const gdb_byte *regs = (const gdb_byte *) xsave; ULONGEST clear_bv; @@ -3463,8 +3424,8 @@ amd64_collect_fxsave (const struct regcache *regcache, int regnum, /* Similar to amd64_collect_fxsave, but use XSAVE extended state. */ void -amd64_collect_xsave (const struct regcache *regcache, int regnum, - void *xsave, int gcore) +amd64_collect_xsave (const struct regcache *regcache, int regnum, void *xsave, + int gcore) { struct gdbarch *gdbarch = regcache->arch (); i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch); @@ -3475,10 +3436,8 @@ amd64_collect_xsave (const struct regcache *regcache, int regnum, if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 64) { if (regnum == -1 || regnum == I387_FISEG_REGNUM (tdep)) - regcache->raw_collect (I387_FISEG_REGNUM (tdep), - regs + 12); + regcache->raw_collect (I387_FISEG_REGNUM (tdep), regs + 12); if (regnum == -1 || regnum == I387_FOSEG_REGNUM (tdep)) - regcache->raw_collect (I387_FOSEG_REGNUM (tdep), - regs + 20); + regcache->raw_collect (I387_FOSEG_REGNUM (tdep), regs + 20); } } |