diff options
Diffstat (limited to 'gas')
| -rw-r--r-- | gas/doc/c-arm.texi | 239 |
1 files changed, 129 insertions, 110 deletions
diff --git a/gas/doc/c-arm.texi b/gas/doc/c-arm.texi index 3a57c12..f07b933 100644 --- a/gas/doc/c-arm.texi +++ b/gas/doc/c-arm.texi @@ -288,182 +288,201 @@ See their availability and meaning below: For @code{armv5te}, @code{armv5texp}, @code{armv5tej}, @code{armv6}, @code{armv6j}, @code{armv6k}, @code{armv6z}, @code{armv6kz}, @code{armv6zk}, @code{armv6t2}, @code{armv6kt2} and @code{armv6zt2}: -@code{+fp}: Enables VFPv2 instructions. -@code{+nofp}: Disables all FPU instrunctions. +@itemize @w{} +@item@code{+fp}: Enables VFPv2 instructions. +@item@code{+nofp}: Disables all FPU instrunctions. +@end itemize For @code{armv7}: -@code{+fp}: Enables VFPv3 instructions with 16 double-word registers. -@code{+nofp}: Disables all FPU instructions. +@itemize @w{} +@item@code{+fp}: Enables VFPv3 instructions with 16 double-word registers. +@item@code{+nofp}: Disables all FPU instructions. +@end itemize For @code{armv7-a}: -@code{+fp}: Enables VFPv3 instructions with 16 double-word registers. -@code{+vfpv3-d16}: Alias for @code{+fp}. -@code{+vfpv3}: Enables VFPv3 instructions with 32 double-word registers. -@code{+vfpv3-d16-fp16}: Enables VFPv3 with half precision floating-point +@itemize @w{} +@item@code{+fp}: Enables VFPv3 instructions with 16 double-word registers. +@item@code{+vfpv3-d16}: Alias for @code{+fp}. +@item@code{+vfpv3}: Enables VFPv3 instructions with 32 double-word registers. +@item@code{+vfpv3-d16-fp16}: Enables VFPv3 with half precision floating-point conversion instructions and 16 double-word registers. -@code{+vfpv3-fp16}: Enables VFPv3 with half precision floating-point conversion +@item@code{+vfpv3-fp16}: Enables VFPv3 with half precision floating-point conversion instructions and 32 double-word registers. -@code{+vfpv4-d16}: Enables VFPv4 instructions with 16 double-word registers. -@code{+vfpv4}: Enables VFPv4 instructions with 32 double-word registers. -@code{+simd}: Enables VFPv3 and NEONv1 instructions with 32 double-word +@item@code{+vfpv4-d16}: Enables VFPv4 instructions with 16 double-word registers. +@item@code{+vfpv4}: Enables VFPv4 instructions with 32 double-word registers. +@item@code{+simd}: Enables VFPv3 and NEONv1 instructions with 32 double-word registers. -@code{+neon}: Alias for @code{+simd}. -@code{+neon-vfpv3}: Alias for @code{+simd}. -@code{+neon-fp16}: Enables VFPv3, half precision floating-point conversion and +@item@code{+neon}: Alias for @code{+simd}. +@item@code{+neon-vfpv3}: Alias for @code{+simd}. +@item@code{+neon-fp16}: Enables VFPv3, half precision floating-point conversion and NEONv1 instructions with 32 double-word registers. -@code{+neon-vfpv4}: Enables VFPv4 and NEONv1 with Fused-MAC instructions and 32 +@item@code{+neon-vfpv4}: Enables VFPv4 and NEONv1 with Fused-MAC instructions and 32 double-word registers. -@code{+mp}: Enables Multiprocessing Extensions. -@code{+sec}: Enables Security Extensions. -@code{+nofp}: Disables all FPU and NEON instructions. -@code{+nosimd}: Disables all NEON instructions. +@item@code{+mp}: Enables Multiprocessing Extensions. +@item@code{+sec}: Enables Security Extensions. +@item@code{+nofp}: Disables all FPU and NEON instructions. +@item@code{+nosimd}: Disables all NEON instructions. +@end itemize For @code{armv7ve}: -@code{+fp}: Enables VFPv4 instructions with 16 double-word registers. -@code{+vfpv4-d16}: Alias for @code{+fp}. -@code{+vfpv3-d16}: Enables VFPv3 instructions with 16 double-word registers. -@code{+vfpv3}: Enables VFPv3 instructions with 32 double-word registers. -@code{+vfpv3-d16-fp16}: Enables VFPv3 with half precision floating-point +@itemize @w{} +@item@code{+fp}: Enables VFPv4 instructions with 16 double-word registers. +@item@code{+vfpv4-d16}: Alias for @code{+fp}. +@item@code{+vfpv3-d16}: Enables VFPv3 instructions with 16 double-word registers. +@item@code{+vfpv3}: Enables VFPv3 instructions with 32 double-word registers. +@item@code{+vfpv3-d16-fp16}: Enables VFPv3 with half precision floating-point conversion instructions and 16 double-word registers. -@code{+vfpv3-fp16}: Enables VFPv3 with half precision floating-point conversion +@item@code{+vfpv3-fp16}: Enables VFPv3 with half precision floating-point conversion instructions and 32 double-word registers. -@code{+vfpv4}: Enables VFPv4 instructions with 32 double-word registers. -@code{+simd}: Enables VFPv4 and NEONv1 with Fused-MAC instructions and 32 +@item@code{+vfpv4}: Enables VFPv4 instructions with 32 double-word registers. +@item@code{+simd}: Enables VFPv4 and NEONv1 with Fused-MAC instructions and 32 double-word registers. -@code{+neon-vfpv4}: Alias for @code{+simd}. -@code{+neon}: Enables VFPv3 and NEONv1 instructions with 32 double-word +@item@code{+neon-vfpv4}: Alias for @code{+simd}. +@item@code{+neon}: Enables VFPv3 and NEONv1 instructions with 32 double-word registers. -@code{+neon-vfpv3}: Alias for @code{+neon}. -@code{+neon-fp16}: Enables VFPv3, half precision floating-point conversion and +@item@code{+neon-vfpv3}: Alias for @code{+neon}. +@item@code{+neon-fp16}: Enables VFPv3, half precision floating-point conversion and NEONv1 instructions with 32 double-word registers. double-word registers. -@code{+nofp}: Disables all FPU and NEON instructions. -@code{+nosimd}: Disables all NEON instructions. +@item@code{+nofp}: Disables all FPU and NEON instructions. +@item@code{+nosimd}: Disables all NEON instructions. +@end itemize For @code{armv7-r}: -@code{+fp.sp}: Enables single-precision only VFPv3 instructions with 16 +@itemize @w{} +@item@code{+fp.sp}: Enables single-precision only VFPv3 instructions with 16 double-word registers. -@code{+vfpv3xd}: Alias for @code{+fp.sp}. -@code{+fp}: Enables VFPv3 instructions with 16 double-word registers. -@code{+vfpv3-d16}: Alias for @code{+fp}. -@code{+vfpv3xd-fp16}: Enables single-precision only VFPv3 and half +@item@code{+vfpv3xd}: Alias for @code{+fp.sp}. +@item@code{+fp}: Enables VFPv3 instructions with 16 double-word registers. +@item@code{+vfpv3-d16}: Alias for @code{+fp}. +@item@code{+vfpv3xd-fp16}: Enables single-precision only VFPv3 and half floating-point conversion instructions with 16 double-word registers. -@code{+vfpv3-d16-fp16}: Enables VFPv3 and half precision floating-point +@item@code{+vfpv3-d16-fp16}: Enables VFPv3 and half precision floating-point conversion instructions with 16 double-word registers. -@code{+idiv}: Enables integer division instructions in ARM mode. -@code{+nofp}: Disables all FPU instructions. +@item@code{+idiv}: Enables integer division instructions in ARM mode. +@item@code{+nofp}: Disables all FPU instructions. +@end itemize For @code{armv7e-m}: -@code{+fp}: Enables single-precision only VFPv4 instructions with 16 +@itemize @w{} +@item@code{+fp}: Enables single-precision only VFPv4 instructions with 16 double-word registers. -@code{+vfpvf4-sp-d16}: Alias for @code{+fp}. -@code{+fpv5}: Enables single-precision only VFPv5 instructions with 16 +@item@code{+vfpvf4-sp-d16}: Alias for @code{+fp}. +@item@code{+fpv5}: Enables single-precision only VFPv5 instructions with 16 double-word registers. -@code{+fp.dp}: Enables VFPv5 instructions with 16 double-word registers. -@code{+fpv5-d16"}: Alias for @code{+fp.dp}. -@code{+nofp}: Disables all FPU instructions. +@item@code{+fp.dp}: Enables VFPv5 instructions with 16 double-word registers. +@item@code{+fpv5-d16"}: Alias for @code{+fp.dp}. +@item@code{+nofp}: Disables all FPU instructions. +@end itemize For @code{armv8-m.main}: -@code{+dsp}: Enables DSP Extension. -@code{+fp}: Enables single-precision only VFPv5 instructions with 16 +@itemize @w{} +@item@code{+dsp}: Enables DSP Extension. +@item@code{+fp}: Enables single-precision only VFPv5 instructions with 16 double-word registers. -@code{+fp.dp}: Enables VFPv5 instructions with 16 double-word registers. -@code{+cdecp0} (CDE extensions for v8-m architecture with coprocessor 0), -@code{+cdecp1} (CDE extensions for v8-m architecture with coprocessor 1), -@code{+cdecp2} (CDE extensions for v8-m architecture with coprocessor 2), -@code{+cdecp3} (CDE extensions for v8-m architecture with coprocessor 3), -@code{+cdecp4} (CDE extensions for v8-m architecture with coprocessor 4), -@code{+cdecp5} (CDE extensions for v8-m architecture with coprocessor 5), -@code{+cdecp6} (CDE extensions for v8-m architecture with coprocessor 6), -@code{+cdecp7} (CDE extensions for v8-m architecture with coprocessor 7), -@code{+nofp}: Disables all FPU instructions. -@code{+nodsp}: Disables DSP Extension. +@item@code{+fp.dp}: Enables VFPv5 instructions with 16 double-word registers. +@item@code{+cdecp0} (CDE extensions for v8-m architecture with coprocessor 0), +@item@code{+cdecp1} (CDE extensions for v8-m architecture with coprocessor 1), +@item@code{+cdecp2} (CDE extensions for v8-m architecture with coprocessor 2), +@item@code{+cdecp3} (CDE extensions for v8-m architecture with coprocessor 3), +@item@code{+cdecp4} (CDE extensions for v8-m architecture with coprocessor 4), +@item@code{+cdecp5} (CDE extensions for v8-m architecture with coprocessor 5), +@item@code{+cdecp6} (CDE extensions for v8-m architecture with coprocessor 6), +@item@code{+cdecp7} (CDE extensions for v8-m architecture with coprocessor 7), +@item@code{+nofp}: Disables all FPU instructions. +@item@code{+nodsp}: Disables DSP Extension. +@end itemize For @code{armv8.1-m.main}: -@code{+dsp}: Enables DSP Extension. -@code{+fp}: Enables single and half precision scalar Floating Point Extensions +@itemize @w{} +@item@code{+dsp}: Enables DSP Extension. +@item@code{+fp}: Enables single and half precision scalar Floating Point Extensions for Armv8.1-M Mainline with 16 double-word registers. -@code{+fp.dp}: Enables double precision scalar Floating Point Extensions for +@item@code{+fp.dp}: Enables double precision scalar Floating Point Extensions for Armv8.1-M Mainline, implies @code{+fp}. -@code{+mve}: Enables integer only M-profile Vector Extension for +@item@code{+mve}: Enables integer only M-profile Vector Extension for Armv8.1-M Mainline, implies @code{+dsp}. -@code{+mve.fp}: Enables Floating Point M-profile Vector Extension for +@item@code{+mve.fp}: Enables Floating Point M-profile Vector Extension for Armv8.1-M Mainline, implies @code{+mve} and @code{+fp}. -@code{+nofp}: Disables all FPU instructions. -@code{+nodsp}: Disables DSP Extension. -@code{+nomve}: Disables all M-profile Vector Extensions. +@item@code{+nofp}: Disables all FPU instructions. +@item@code{+nodsp}: Disables DSP Extension. +@item@code{+nomve}: Disables all M-profile Vector Extensions. +@end itemize For @code{armv8-a}: -@code{+crc}: Enables CRC32 Extension. -@code{+simd}: Enables VFP and NEON for Armv8-A. -@code{+crypto}: Enables Cryptography Extensions for Armv8-A, implies -@code{+simd}. -@code{+sb}: Enables Speculation Barrier Instruction for Armv8-A. -@code{+predres}: Enables Execution and Data Prediction Restriction Instruction +@itemize @w{} +@item@code{+crc}: Enables CRC32 Extension. +@item@code{+simd}: Enables VFP and NEON for Armv8-A. +@item@code{+crypto}: Enables Cryptography Extensions for Armv8-A, implies @code{+simd}. +@item@code{+sb}: Enables Speculation Barrier Instruction for Armv8-A. +@item@code{+predres}: Enables Execution and Data Prediction Restriction Instruction for Armv8-A. -@code{+nofp}: Disables all FPU, NEON and Cryptography Extensions. -@code{+nocrypto}: Disables Cryptography Extensions. +@item@code{+nofp}: Disables all FPU, NEON and Cryptography Extensions. +@item@code{+nocrypto}: Disables Cryptography Extensions. +@end itemize For @code{armv8.1-a}: -@code{+simd}: Enables VFP and NEON for Armv8.1-A. -@code{+crypto}: Enables Cryptography Extensions for Armv8-A, implies -@code{+simd}. -@code{+sb}: Enables Speculation Barrier Instruction for Armv8-A. -@code{+predres}: Enables Execution and Data Prediction Restriction Instruction +@itemize @w{} +@item@code{+simd}: Enables VFP and NEON for Armv8.1-A. +@item@code{+crypto}: Enables Cryptography Extensions for Armv8-A, implies @code{+simd}. +@item@code{+sb}: Enables Speculation Barrier Instruction for Armv8-A. +@item@code{+predres}: Enables Execution and Data Prediction Restriction Instruction for Armv8-A. -@code{+nofp}: Disables all FPU, NEON and Cryptography Extensions. -@code{+nocrypto}: Disables Cryptography Extensions. +@item@code{+nofp}: Disables all FPU, NEON and Cryptography Extensions. +@item@code{+nocrypto}: Disables Cryptography Extensions. +@end itemize For @code{armv8.2-a} and @code{armv8.3-a}: -@code{+simd}: Enables VFP and NEON for Armv8.1-A. -@code{+fp16}: Enables FP16 Extension for Armv8.2-A, implies @code{+simd}. -@code{+fp16fml}: Enables FP16 Floating Point Multiplication Variant Extensions +@itemize @w{} +@item@code{+simd}: Enables VFP and NEON for Armv8.1-A. +@item@code{+fp16}: Enables FP16 Extension for Armv8.2-A, implies @code{+simd}. +@item@code{+fp16fml}: Enables FP16 Floating Point Multiplication Variant Extensions for Armv8.2-A, implies @code{+fp16}. -@code{+crypto}: Enables Cryptography Extensions for Armv8-A, implies -@code{+simd}. -@code{+dotprod}: Enables Dot Product Extensions for Armv8.2-A, implies -@code{+simd}. -@code{+sb}: Enables Speculation Barrier Instruction for Armv8-A. -@code{+predres}: Enables Execution and Data Prediction Restriction Instruction +@item@code{+crypto}: Enables Cryptography Extensions for Armv8-A, implies @code{+simd}. +@item@code{+dotprod}: Enables Dot Product Extensions for Armv8.2-A, implies @code{+simd}. +@item@code{+sb}: Enables Speculation Barrier Instruction for Armv8-A. +@item@code{+predres}: Enables Execution and Data Prediction Restriction Instruction for Armv8-A. -@code{+nofp}: Disables all FPU, NEON, Cryptography and Dot Product Extensions. -@code{+nocrypto}: Disables Cryptography Extensions. +@item@code{+nofp}: Disables all FPU, NEON, Cryptography and Dot Product Extensions. +@item@code{+nocrypto}: Disables Cryptography Extensions. +@end itemize For @code{armv8.4-a}: -@code{+simd}: Enables VFP and NEON for Armv8.1-A and Dot Product Extensions for +@itemize @w{} +@item@code{+simd}: Enables VFP and NEON for Armv8.1-A and Dot Product Extensions for Armv8.2-A. -@code{+fp16}: Enables FP16 Floating Point and Floating Point Multiplication +@item@code{+fp16}: Enables FP16 Floating Point and Floating Point Multiplication Variant Extensions for Armv8.2-A, implies @code{+simd}. -@code{+crypto}: Enables Cryptography Extensions for Armv8-A, implies -@code{+simd}. -@code{+sb}: Enables Speculation Barrier Instruction for Armv8-A. -@code{+predres}: Enables Execution and Data Prediction Restriction Instruction +@item@code{+crypto}: Enables Cryptography Extensions for Armv8-A, implies @code{+simd}. +@item@code{+sb}: Enables Speculation Barrier Instruction for Armv8-A. +@item@code{+predres}: Enables Execution and Data Prediction Restriction Instruction for Armv8-A. -@code{+nofp}: Disables all FPU, NEON, Cryptography and Dot Product Extensions. -@code{+nocryptp}: Disables Cryptography Extensions. +@item@code{+nofp}: Disables all FPU, NEON, Cryptography and Dot Product Extensions. +@item@code{+nocryptp}: Disables Cryptography Extensions. +@end itemize For @code{armv8.5-a}: -@code{+simd}: Enables VFP and NEON for Armv8.1-A and Dot Product Extensions for +@itemize @w{} +@item@code{+simd}: Enables VFP and NEON for Armv8.1-A and Dot Product Extensions for Armv8.2-A. -@code{+fp16}: Enables FP16 Floating Point and Floating Point Multiplication +@item@code{+fp16}: Enables FP16 Floating Point and Floating Point Multiplication Variant Extensions for Armv8.2-A, implies @code{+simd}. -@code{+crypto}: Enables Cryptography Extensions for Armv8-A, implies -@code{+simd}. -@code{+nofp}: Disables all FPU, NEON, Cryptography and Dot Product Extensions. -@code{+nocryptp}: Disables Cryptography Extensions. - +@item@code{+crypto}: Enables Cryptography Extensions for Armv8-A, implies @code{+simd}. +@item@code{+nofp}: Disables all FPU, NEON, Cryptography and Dot Product Extensions. +@item@code{+nocryptp}: Disables Cryptography Extensions. +@end itemize @cindex @code{-mfpu=} command-line option, ARM @item -mfpu=@var{floating-point-format} |