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+2015-12-24 Thomas Preud'homme <thomas.preudhomme@arm.com>
+
+ * config/tc-arm.c (arm_ext_v6t2_v8m): New feature for instructions
+ shared between ARMv6T2 and ARMv8-M.
+ (move_or_literal_pool): Check mov.w/mvn and movw availability against
+ arm_ext_v6t2 and arm_ext_v6t2_v8m respectively instead of checking
+ arm_arch_t2.
+ (do_t_branch): Error out for wide conditional branch instructions if
+ targetting ARMv8-M Baseline.
+ (non_v6t2_wide_only_insn): Add the logic for new wide-only instructions
+ in ARMv8-M Baseline.
+ (wide_insn_ok): New function.
+ (md_assemble): Use wide_insn_ok instead of non_v6t2_wide_only_insn and
+ adapt error message for unsupported wide instruction to ARMv8-M
+ Baseline.
+ (insns): Reorganize instructions shared by ARMv8-M Baseline and
+ ARMv6t2 architecture.
+ (arm_cpus): Set feature bit ARM_EXT2_V6T2_V8M for marvell-pj4 and
+ marvell-whitney cores.
+ (arm_archs): Define armv8-m.base architecture.
+ (cpu_arch_ver): Define ARM_ARCH_V8M_BASE architecture version.
+ (aeabi_set_public_attributes): Add logic to set Tag_CPU_arch to 17 for
+ ARMv8-M Mainline. Set Tag_DIV_use for ARMv8-M Baseline as well.
+
+2015-12-24 Thomas Preud'homme <thomas.preudhomme@arm.com>
+
+ * config/tc-arm.c (arm_ext_m): Include ARMv8-M.
+ (arm_ext_v8m): New feature for ARMv8-M.
+ (arm_ext_atomics): New feature for ARMv8 atomics.
+ (do_tt): New encoding function for TT* instructions.
+ (insns): Add new entries for ARMv8-M specific instructions and
+ reorganize the ones shared by ARMv8-M Mainline and ARMv8-A.
+ (arm_archs): Define armv8-m.main architecture.
+ (cpu_arch_ver): Define ARM_ARCH_V8M_MAIN architecture version and
+ clarify the ordering rule.
+ (aeabi_set_public_attributes): Use TAG_CPU_ARCH_* macro to refer to
+ Tag_CPU_arch values for ARMv7e-M detection. Add logic to keep setting
+ Tag_CPU_arch to ARMv8-A for -march=all. Also set Tag_CPU_arch_profile
+ to 'A' if extension bit for atomic instructions is set, unless it is
+ ARMv8-M. Set Tag_THUMB_ISA_use to 3 for ARMv8-M. Set Tag_DIV_use to 0
+ for ARMv8-M Mainline.
+
+2015-12-24 Thomas Preud'homme <thomas.preudhomme@arm.com>
+
+ * config/tc-arm.c (move_or_literal_pool): Check mov.w, mvm and movw
+ availability against arm_ext_v6t2 instead of checking arm_arch_t2,
+ fixing comments along the way.
+ (handle_it_state): Check arm_ext_v6t2 instead of arm_arch_t2 to
+ generate IT instruction.
+ (t1_isa_t32_only_insn): New function.
+ (md_assemble): Use above new function to check for invalid wide
+ instruction for CPU Thumb ISA and to determine what Thumb extension
+ bit is necessary for that instruction.
+ (md_apply_fix): Use arm_ext_v6t2 instead of arm_arch_t2 to decide if
+ branch is out of range.
+
+2015-12-21 Nick Clifton <nickc@redhat.com>
+
+ PR gas/19386
+ * doc/as.texinfo (Strings): Prepend a space to index entries that
+ start with a backslash. This works around a problem in the pdf
+ generator.
+
+2015-12-18 H.J. Lu <hongjiu.lu@intel.com>
+
+ * config/tc-i386.c (optimize_imm): Store 32-bit immediate in
+ 64-bit only for 64-bit BFD.
+ (optimize_disp): Optimize 64-bit displacement to 32-bit only
+ for 64-bit BFD.
+
+2015-12-17 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
+
+ * config/tc-arm.c (aeabi_set_public_attributes): Adjust
+ TAG_ARCH_profile for armv8-a.
+
+2015-12-16 Mickael Guene <mickael.guene@st.com>
+
+ * doc/c-arm.texi: Add documentation about new directives
+ * config/tc-arm.c (group_reloc_table): Add mapping between gas
+ syntax and new relocations.
+ (do_t_add_sub): Keep new relocations for add operand.
+ (do_t_mov_cmp): Keep new relocations for mov operand.
+ (insns): Use 'shifter operand with possible group relocation'
+ operand parse code for movs operand.
+ (md_apply_fix): Implement mov and add encoding when new
+ relocations on them.
+ (tc_gen_reloc): Add new relocations.
+ (arm_fix_adjustable): Since offset has a limited range ([0:255])
+ we disable adjust_reloc_syms() for new relocations.
+
+2015-12-15 Nick Clifton <nickc@redhat.com>
+
+ * doc/c-msp430.texi (MSP430 Options): Remove references to a
+ non-existant silicon errata.
+ * config/tc-msp430.c: Likewise.
+
+2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
+
+ * config/tc-aarch64.c (parse_neon_type_for_operand): Adjust to
+ take into account new vector type 2H.
+ (vectype_to_qualifier): Likewise.
+
+2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
+
+ * config/tc-aarch64.c (vectype_to_qualifier): Calculate operand
+ qualifier from per-type base and offet.
+
+2015-12-14 Yoshinori Sato <ysato@users.sourceforge.jp>
+
+ * config/rx-defs.h(rx_cpu_type): Add RXV2 type.
+ * config/tc-rx.c(cpu_type_list): New type lookup table.
+ (md_parse_option): Use lookup table for choose cpu.
+ (md_show_usage): Add rxv2 for mcpu option.
+ * doc/c-rx.texi: Likewise.
+ * config/rx-parse.y: Add v2 instructions and ACC register.
+ (rx_check_v2): check v2 type.
+
+2015-12-14 Jan Beulich <jbeulich@suse.com>
+
+ * dw2gencfi.c (dot_cfi_label): Free "name".
+
+2015-12-11 Matthew Wahab <matthew.wahab@arm.com>
+
+ * config/tc-aarch64.c (aarch64_hint_opt_hsh): New.
+ (parse_barrier_psb): New.
+ (parse_operands): Add case for AARCH64_OPND_BARRIER_PSB.
+ (md_begin): Set up aarch64_hint_opt_hsh.
+
+2015-12-11 Matthew Wahab <matthew.wahab@arm.com>
+
+ * config/tc-aarch64.c (aarch64_features): Add "profile".
+ * doc/c-aarch64.texi (AArch64 Extensions): Add "profile".
+
+2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
+
+ * config/tc-aarch64.c (parse_sys_ins_reg): Add check of
+ architectural support for system register.
+
+2015-12-10 Jose E. Marchesi <jose.marchesi@oracle.com>
+
+ * doc/c-sparc.texi (Sparc-Regs): Document the %dN and %qN notation
+ for floating-point registers.
+
+2015-12-10 Matthew Wahab <matthew.wahab@arm.com>
+
+ * doc/c-aarch64.texi (AArch64 Extensions): Update entry for crc.
+
+2015-12-10 Andrew Burgess <andrew.burgess@embecosm.com>
+
+ * config/tc-arc.c (md_parse_option): Return 1 in order to accept
+ dummy arguments.
+
+2015-12-09 Jose E. Marchesi <jose.marchesi@oracle.com>
+
+ * config/tc-sparc.c (sparc_ip): Support %dN and %qN notation for
+ double and quad-precision floating-point registers.
+
+2015-12-09 Nick Clifton <nickc@redhat.com>
+
+ * config/tc-rx.c (rx_relax_frag): Fix compile time warning.
+
+2015-12-08 Jan Beulich <jbeulich@suse.com>
+
+ * read.c (in_bss): New.
+ (do_align): Use it to also warn for non-zero fill in .bss.
+ (do_org): Likewise.
+ (s_space): Likewise.
+ (s_fill): Error on bad use in .bss/.struct.
+ (float_cons): Likewise.
+ (emit_leb128_expr): Likewise.
+ (emit_expr_with_reloc): Defer handling use inside .struct. Also
+ error on non-zero item added to .bss.
+ (stringer_append_char): Error on non-zero character.
+
+2015-12-08 Jan Beulich <jbeulich@suse.com>
+
+ * read.c (stringer): Move absolute section check up. Return
+ right away.
+
+2015-12-08 Jan Beulich <jbeulich@suse.com>
+
+ * config/obj-elf.c (elf_file_symbol): Tighten condition for
+ moving BSF_FILE symbols.
+
+2015-12-08 DJ Delorie <dj@redhat.com>
+
+ * config/rl78-parse.y: Make all branches relaxable via
+ rl78_linkrelax_branch().
+ * config/tc-rl78.c (rl78_linkrelax_branch): Mark all relaxable
+ branches with relocs.
+ (options): Add OPTION_NORELAX.
+ (md_longopts): Add -mnorelax.
+ (md_parse_option): Support OPTION_NORELAX.
+ (op_type_T): Add bh, sk, call, and br.
+ (rl78_opcode_type): Likewise.
+ (rl78_relax_frag): Fix not-relaxing logic. Add sk.
+ (md_convert_frag): Fix relocation handling.
+ (tc_gen_reloc): Strip relax relocs when not linker relaxing.
+ (md_apply_fix): Defer overflow handling for anything that needs a
+ PLT, to the linker.
+ * config/tc-rl78.h (TC_FORCE_RELOCATION): Force all relocations to
+ the linker when linker relaxing.
+ * doc/c-rl78.texi (norelax): Add.
+
+2015-12-07 Alan Modra <amodra@gmail.com>
+
+ * config/tc-ppc.c (md_apply_fix): Localize variables. Reduce casts.
+
+2015-12-04 Nick Clifton <nickc@redhat.com>
+
+ PR gas/19276
+ * config/tc-arm.h (SUB_SEGMENT_ALIGN): Do not define for COFF/PE
+ targets.
+
+2015-12-04 Claudiu Zissulescu <claziss@synopsys.com>
+
+ * config/tc-arc.c (arc_option): Sets all internal gas options when
+ parsing .cpu directive.
+ (declare_register_set): Declare all 64 registers.
+ (md_section_align): Refactor.
+ (md_pcrel_from_section): Remove assert.
+ (pseudo_operand_match): Fix pseudo operand match.
+ (find_reloc): Use flags filed, extend matching.
+ * config/tc-arc.h (TC_VALIDATE_FIX): Don't fixup any PLT
+ relocation.
+
+2015-12-01 Alan Modra <amodra@gmail.com>
+
+ * config/aout_gnu.h: Invoke aout N_* macros with pointer to
+ struct internal_exec.
+
+2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
+
+ * config/tc-aarch64.c (aarch64_features): Add "fp16".
+ * doc/c-aarch64.texi (Architecture Extensions): Add "fp16".
+
+2015-11-24 Christophe Monat <christophe.monat@st.com>
+
+ * config/tc-arm.c (move_or_literal_pool): Do not transform ldr
+ ri,=imm into movs when ri is a high register in T1.
+
+2015-11-20 Nick Clifton <nickc@redhat.com>
+
+ * po/fr.po: Updated French translation.
+ * po/uk.po: Updated Ukraninan translation.
+ * po/zh_CN.po: New simplified Chinese translation.
+ * configure.ac (ALL_LINGUAS): Add zh_CN.
+ * configure: Regenerate.
+
+2015-11-19 Matthew Wahab <matthew.wahab@arm.com>
+
+ * config/tc-arm.c (arm_archs): Add "armv8.2-a".
+ * doc/c-arm.texi (-march): Add "armv8.2-a".
+
+2015-11-19 Matthew Wahab <matthew.wahab@arm.com>
+
+ * config/tc-aarch64.c (aarch64_archs): Add "armv8.2-a".
+ * doc/c-aarch64.texi (-march): Likewise.
+
+2015-11-19 Alan Modra <amodra@gmail.com>
+
+ * read.c (output_big_leb128): Describe "sign" parameter.
+
+2015-11-19 Alan Modra <amodra@gmail.com>
+
+ * config/tc-ppc.h (SUB_SEGMENT_ALIGN): Define only for ELF.
+
+2015-11-16 Mike Frysinger <vapier@gentoo.org>
+
+ * config/tc-microblaze.c (parse_imm): Add an offsetT cast.
+
+2015-11-13 Tristan Gingold <gingold@adacore.com>
+
+ * configure: Regenerate.
+
+2015-11-13 Tristan Gingold <gingold@adacore.com>
+
+ * NEWS: Add marker for 2.26.
+
+2015-11-12 James Greenhalgh <james.greenhalgh@arm.com>
+
+ * config/tc-aarch64.c (aarch64_cpus): Add cortex-a35.
+ * doc/c-aarch64.texi (-mcpu=): Likewise.
+
+2015-11-12 James Greenhalgh <james.greenhalgh@arm.com>
+
+ * config/tc-arm.c (arm_cpus): Likewise.
+ * doc/c-arm.texi (-mcpu=): Likewise.
+
+2015-11-12 Matthew Wahab <matthew.wahab@arm.com>
+
+ PR gas/19217
+ * config/tc-arm.c (move_or_literal_pool): Remove redundant feature
+ check. Fix some code formatting. Drop use of MOVT. Add some
+ comments.
+
+2015-11-11 Alan Modra <amodra@gmail.com>
+ Peter Bergner <bergner@vnet.ibm.com>
+
+ * doc/as.texinfo (Target PowerPC): Document -mpower9 and -mpwr9.
+ * doc/c-ppc.texi (PowerPC-Opts): Likewise.
+ * config/tc-ppc.c (md_show_usage): Likewise.
+ (md_assemble): Handle BFD_RELOC_PPC_REL16DX_HA.
+ (md_apply_fix): Likewise.
+ (ppc_handle_align): Handle power9's group ending nop.
+
+2015-11-09 Jim Wilson <jim.wilson@linaro.org>
+
+ * config/tc-aarch64.c (aarch64_cpus): Add qdf24xx.
+ * config/tc-arm.c (arm_cpus): Likewise.
+ * doc/c-arm.texi, doc/c-aarch64.texi: Likewise.
+
+2015-11-09 Dominik Vogt <vogt@linux.vnet.ibm.com>
+
+ * read.c (parse_bitfield_cons): Fix left shift of negative value.
+ * config/tc-xstormy16.c (md_section_align): Likewise.
+ * config/tc-xgate.c (md_section_align): Likewise.
+ * config/tc-visium.c (md_section_align): Likewise.
+ * config/tc-v850.c (md_section_align): Likewise.
+ * config/tc-tic6x.c (md_section_align): Likewise.
+ * config/tc-sh.c (SH64PCREL32_M, SH64PCREL48_M, SH64PCREL32_M)
+ (MOVI_32_M, MOVI_48_M, MOVI_32_M, md_section_align): Likewise.
+ * config/tc-sh64.c (shmedia_md_estimate_size_before_relax): Likewise.
+ * config/tc-score.c (s3_section_align): Likewise.
+ * config/tc-score7.c (s7_section_align): Likewise.
+ * config/tc-s390.c (md_section_align): Likewise.
+ * config/tc-rx.c (md_section_align): Likewise.
+ * config/tc-rl78.c (md_section_align): Likewise.
+ * config/tc-ppc.c (md_section_align): Likewise.
+ * config/tc-or1k.c (md_section_align): Likewise.
+ * config/tc-nds32.c (md_section_align): Likewise.
+ * config/tc-mt.c (md_section_align): Likewise.
+ * config/tc-msp430.c (md_section_align): Likewise.
+ * config/tc-mn10300.c (md_section_align): Likewise.
+ * config/tc-mn10200.c (md_section_align): Likewise.
+ * config/tc-mips.c (md_section_align): Likewise.
+ * config/tc-microblaze.c (parse_imm): Likewise.
+ * config/tc-mep.c (md_section_align): Likewise.
+ * config/tc-m68k.c (md_section_align): Likewise.
+ * config/tc-m68hc11.c (md_section_align): Likewise.
+ * config/tc-m32r.c (md_section_align): Likewise.
+ * config/tc-m32c.c (md_section_align): Likewise.
+ * config/tc-lm32.c (md_section_align): Likewise.
+ * config/tc-iq2000.c (md_section_align): Likewise.
+ * config/tc-ip2k.c (md_section_align): Likewise.
+ * config/tc-ia64.c (dot_save, dot_vframe): Likewise.
+ * config/tc-i960.c (md_number_to_field, md_section_align): Likewise.
+ * config/tc-i386.c (md_section_align): Likewise.
+ * config/tc-i370.c (md_section_align): Likewise.
+ * config/tc-frv.c (md_section_align): Likewise.
+ * config/tc-fr30.c (md_section_align): Likewise.
+ * config/tc-epiphany.c (md_section_align): Likewise.
+ * config/tc-d30v.c (md_section_align): Likewise.
+ * config/tc-d10v.c (md_section_align): Likewise.
+ * config/tc-cr16.c (l_cons): Likewise.
+ * config/tc-bfin.c (md_section_align): Likewise.
+ * config/tc-arm.c (md_section_align): Likewise.
+ * config/tc-arc.c (md_section_align): Likewise.
+ * config/bfin-parse.y (expr_1): Likewise.
+
+2015-11-02 Nick Clifton <nickc@redhat.com>
+
+ * config/rx-parse.y: Allow zero value for 5-bit displacements.
+
+2015-11-02 Nick Clifton <nickc@redhat.com>
+
+ * config/tc-rx.c (parse_rx_section): Align parameter provides a
+ multiple of n argument, not a power of n argument.
+
+2015-10-29 Nick Clifton <nickc@redhat.com>
+
+ * config/tc-aarch64.c (elf64_aarch64_target_format): Select the
+ cloudabi format if the TARGET_OS is cloudabi.
+
+2015-10-29 Thomas Preud'homme <thomas.preudhomme@arm.com>
+
+ * config/tc-arm.c (insns): Guard cps by arm_ext_v6_notm instead of
+ arm_ext_v6_dsp.
+
+2015-10-28 Claudiu Zissulescu <claziss@synopsys.com>
+
+ * config/tc-arc.c (tokenize_arguments): Avoid creating unused
+ symbols when parsing relocation types.
+ (md_apply_fix): Handle TLS relocations. Fix BFD_RELOC_ARC_32_PCREL
+ relocation.
+ (arc_check_reloc): Emit BFD_RELOC_ARC_32_PCREL relocation.
+
+2015-10-27 Jim Wilson <jim.wilson@linaro.org>
+
+ * config/tc-arm.c (selected_cpu_name): Increase length of array to
+ accomodate "Samsung Exynos M1".
+ (arm_parse_cpu): Add assertion and length check to prevent
+ overfilling selected_cpu_name.
+
+2015-10-22 Nick Clifton <nickc@redhat.com>
+
+ * config/tc-msp430.c (PUSH_1X_WORKAROUND): Delete.
+ (OPTION_SILICON_ERRATA): Define.
+ (OPTION_SILICON_WARN): Define.
+ (md_parse_opton): Handle silicon errata options.
+ (md_longopts): Add silicon errata options.
+ (ms_show_usage): Report silicon errata options.
+ (msp430_srcoperand): Handle silicon errata.
+ (msp430_operands): Likewise. Improve nop insertion.
+ (msp430_fix_adjustable): Update warning generation.
+ * doc/c-msp430.texi: Document silicon errata options.
+
+2015-10-22 H.J. Lu <hongjiu.lu@intel.com>
+
+ * configure.ac: Properly check
+ --enable-compressed-debug-sections={yes,all}.
+ * configure: Regenerated.
+
+2015-10-22 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/19109
+ * configure.ac: Handle --enable-compressed-debug-sections=*,gas,*.
+ * configure: Regenerated.
+
+2015-10-22 H.J. Lu <hongjiu.lu@intel.com>
+
+ * config/tc-i386.c (tc_i386_fix_adjustable): Handle
+ BFD_RELOC_X86_64_GOTPCRELX and BFD_RELOC_X86_64_REX_GOTPCRELX.
+ (tc_gen_reloc): Likewise.
+ (i386_validate_fix): Generate BFD_RELOC_X86_64_GOTPCRELX or
+ BFD_RELOC_X86_64_REX_GOTPCRELX if fx_tcbit2 is set.
+ * config/tc-i386.h (TC_FORCE_RELOCATION_LOCAL): Also return
+ true for BFD_RELOC_X86_64_GOTPCRELX and
+ BFD_RELOC_X86_64_REX_GOTPCRELX.
+
+2015-10-22 H.J. Lu <hongjiu.lu@intel.com>
+
+ * config/tc-i386.c (tc_i386_fix_adjustable): Handle
+ BFD_RELOC_386_GOT32X.
+ (tc_gen_reloc): Likewise.
+ (match_template): Force 0x8b encoding for "mov foo@GOT, %eax".
+ (output_disp): Check for "call/jmp *mem", "mov mem, %reg",
+ "test %reg, mem" and "binop mem, %reg" where binop is one of
+ adc, add, and, cmp, or, sbb, sub, xor instructions. Set
+ fx_tcbit if the REX prefix is generated. Set fx_tcbit2 if
+ BFD_RELOC_386_GOT32X should be generated.
+ (i386_validate_fix): Generate BFD_RELOC_386_GOT32X if fx_tcbit2
+ is set.
+
+2015-10-21 Nick Clifton <nickc@redhat.com>
+
+ PR gas/19109
+ * configure.ac: Restore --enable-compressed-debug-sections, with
+ options of all, none or gas.
+ Do not enable compressed debug sections by default for x86 Linux
+ targets.
+ * configure: Regenerate.
+
+2015-10-20 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/19109
+ * NEWS: Update --enable-compressed-debug-sections=.
+ * configure.ac: Remove --enable-compressed-debug-sections.
+ (DEFAULT_FLAG_COMPRESS_DEBUG): Check
+ --enable-compressed-debug-sections={all,gas} instead of
+ --enable-compressed-debug-sections. For x86 Linux targets,
+ default to compressing debug sections.
+ * configure: Regenerated.
+
+2015-10-19 Nick Clifton <nickc@redhat.com>
+
+ PR gas/19109
+ * configure.ac: Add option --enable-compressed-debug-sections.
+ This sets the default behaviour for compressing debug sections.
+ * as.c (flag_compress_debug): Define and initialise to
+ COMPRESS_DEBUG_GABI_ZLIB if DEFAULT_COMPRESS_DEBUG is set.
+ (show_usage): Indicate whether --no-compress-debug-sections
+ or --compress-debug-sections is the default.
+ * config/tc-i386.c (flag_compress_debug): Delete definition.
+ * doc/as.texinfo (--nocompress-debug-sectionas): Update
+ description.
+ * NEWS: Announce the new feature.
+ * config.in: Regenerate.
+ * configure: Regenerate.
+
+2015-10-12 Nick Clifton <nickc@redhat.com>
+
+ * config/tc-msp430.c (msp430_mcu_names): Rename to
+ msp430_mcu_data. Add fields for the ISA and hardware multiply
+ support. Update with information from the latest devices.csv
+ file.
+ (md_parse_option): Make use of the new array.
+
+2015-10-12 Andrew Burgess <andrew.burgess@embecosm.com>
+
+ * config/tc-avr.c (avr_output_property_record): Fix overwrite bug
+ for align and fill records.
+ (avr_handle_align): Record fill information for align frags.
+ (create_record_for_frag): Add next frag assertion, use correct
+ address for align records.
+
+2015-10-10 Alan Modra <amodra@gmail.com>
+
+ PR gas/19113
+ * read.c (next_char_of_string): Mask char after escape. Use
+ CHAR_MASK rather than 0xff.
+
+2015-10-07 Yao Qi <yao.qi@linaro.org>
+
+ * config/tc-aarch64.c (md_begin): Access field 'name' rather
+ than 'template'.
+
+2015-10-07 Claudiu Zissulescu <claziss@synopsys.com>
+
+ * config/tc-arc.c: Revamped file for ARC support.
+ * config/tc-arc.h: Likewise.
+ * doc/as.texinfo: Add new ARC options.
+ * doc/c-arc.texi: Likewise.
+
+2015-10-02 Renlin Li <renlin.li@arm.com>
+
+ * config/tc-aarch64.c (s_tlsdescadd): New.
+ (s_tlsdescldr): New.
+ (md_pseudo_table): Handle tlsdescadd and tlsdescldr pseudo ops.
+ (reloc_table): Add entries for BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC and
+ BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC.
+ (process_movw_reloc_info): Support AARCH64_TLSDESC_OFF_G1 and
+ AARCH64_TLSDESC_OFF_G0_NC.
+ (md_apply_fix): Likewise.
+ (aarch64_force_relocation): Likewise.
+
+2015-10-02 Renlin Li <renlin.li@arm.com>
+
+ * config/tc-aarch64.c (reloc_table): Add two entries for
+ gottprel_g0_nc and gottprel_g1.
+ (process_movw_reloc_info): Add support.
+ (md_apply_fix): Likewise.
+ (aarch64_force_relocation): Likewise.
+
+2015-10-02 Renlin Li <renlin.li@arm.com>
+
+ * config/tc-aarch64.c (reloc_table): New relocation modifier tlsgd_g0_nc.
+ (process_movw_reloc_info): Support BFD_RELOC_AARCH64_TLSGD_MOVW_G1.
+ (md_apply_fix): Likewise.
+ (aarch64_force_relocation): Likewise.
+
+2015-10-02 Renlin Li <renlin.li@arm.com>
+
+ * config/tc-aarch64.c (reloc_table): New relocation modifier tlsgd_g1.
+ (process_movw_reloc_info): Support BFD_RELOC_AARCH64_TLSGD_MOVW_G1.
+ (md_apply_fix): Likewise.
+ (aarch64_force_relocation): Likewise.
+
+2015-10-02 Renlin Li <renlin.li@arm.com>
+
+ * config/tc-aarch64.c (reloc_table): New relocation modifier
+ gotoff_g0_nc.
+ (process_movw_reloc_info): Support gotoff_g0_nc.
+ (md_apply_fix): Likewise.
+
+2015-10-02 Renlin Li <renlin.li@arm.com>
+
+ * config/tc-aarch64.c (reloc_table): New relocation modifier
+ gotoff_g1.
+ (process_movw_reloc_info): Support newly added modifier.
+ (md_apply_fix): Likewise.
+
+2015-09-29 Dominik Vogt <vogt@linux.vnet.ibm.com>
+
+ * doc/c-s390.texi: Add documentation.
+ Add missing code markup.
+ * config/tc-s390.c (current_flags): New static variable.
+ (s390_parse_cpu): Parse cpu flags a la "+nohtm" etc.
+ (s390_setup_opcodes): Use cpu flags to determine the set of opcodes.
+ Fix indentation.
+ (md_parse_option): Call s390_parse_cpu with the new signature.
+ (s390_machine): Likewise.
+ Keep track of current_flags.
+ Simplify code a bit.
+ undefine MAX_HISTORY at end of function.
+ (s390_machinemode): undefine MAX_HISTORY at end of function.
+ Update an error message.
+
+2015-08-11 Peter Zotov <whitequark@whitequark.org>
+
+ PR ld/18759
+ * config/tc-or1k.c (tc_gen_reloc): Correct computation of PC
+ relative relocs.
+ * config/tc-or1k.h (GAS_CGEN_PRCEL_R_TYPE): Delete.
+
+2015-09-25 Ryo ONODERA <ryo_on@yk.rim.or.jp>
+
+ PR 18994
+ * configure.ac (nds32): Don't use bash == in tests.
+ * configure: Regenerate.
+
+2015-09-23 Nick Clifton <nickc@redhat.com>
+
+ * config/tc-ppc.c (insn_validate): Cast PPC_OPSHIFT_INV to an int.
+
+2015-09-22 Nick Clifton <nickc@redhat.com>
+
+ * config/tc-rx.c (nop_7): Recode using MAX.
+
+2015-09-05 Chen Gang <gang.chen.5i5j@gmail.com>
+
+ * config/tc-avr.c (md_section_align): Append UL for -1 to avoid
+ the latest gcc's warning.
+
+2015-08-27 Alan Modra <amodra@gmail.com>
+
+ PR gas/18581
+ * config/tc-aarch64.h (TC_START_LABEL): Redefine.
+ * config/tc-arm.c (tc_start_label_without_colon): Delete params.
+ Use input_line_pointer directly.
+ * config/tc-arm.h (TC_START_LABEL): Redefine.
+ (TC_START_LABEL_WITHOUT_COLON): Redefine.
+ (tc_start_label_without_colon): Update prototype.
+ * config/tc-bfin.c (bfin_start_label): Delete ptr param. Check
+ for NUL instead.
+ * config/tc-bfin.h (bfin_start_label): Update prototype.
+ (TC_START_LABEL): Redefine.
+ * config/tc-d30v.h (TC_START_LABEL): Redefine.
+ * config/tc-fr30.c (restore_colon): Rewrite.
+ (fr30_is_colon_insn): Add nul_char param. Return int. Bump
+ i_l_p over quote. Update restore_colon calls.
+ * config/tc-fr30.h (TC_START_LABEL): Redefine.
+ (fr30_is_colon_insn): Update prototype.
+ * config/tc-m32c.c (restore_colon, m32c_is_colon_insn): As above.
+ * config/tc-m32c.h (TC_START_LABEL): Redefine.
+ (m32c_is_colon_insn): Update prototype.
+ * config/tc-m32r.h (TC_START_LABEL): Redefine.
+ * config/tc-mep.h (TC_START_LABEL): Redefine.
+ * config/tc-nds32.h (TC_START_LABEL): Redefine.
+ * config/tc-tic54x.c (tic54x_start_label): Replace params with
+ nul_char and next_char. Step over trailing quote.
+ * config/tc-tic54x.h (TC_START_LABEL_WITHOUT_COLON): Redefine.
+ (tic54x_start_label): Update prototype.
+ * read.c (TC_START_LABEL): Redefine. Update invocation.
+ (TC_START_LABEL_WITHOUT_COLON): Update invocation.
+ * config/tc-nios2.c (s_nios2_set): Save initial input_line_pointer
+ and restore if calling s_set. Don't restore delim again.
+
+2015-08-26 Alan Modra <amodra@gmail.com>
+
+ PR gas/18581
+ * config/tc-mn10200.c (md_assemble <mdr>): Move restore_line_pointer
+ call to where input line used to be restored.
+ * config/tc-mn10300.c (md_assemble <usp>): Remove redundant input
+ line restore.
+ * config/tc-tilepro.c (parse_reg_expression): Add regname var.
+
+2015-08-26 Nick Clifton <nickc@redhat.com>
+
+ PR gas/18842
+ * configure.ac (AS_CHECK_DECLS): Add asprintf.
+ * configure: Regenerate.
+ * config.in: Regenerate.
+
+2015-08-25 Jose E. Marchesi <jose.marchesi@oracle.com>
+
+ * config/tc-sparc.c (priv_reg_table): New privileged register
+ %pmcdper.
+
+2015-08-21 Nick Clifton <nickc@redhat.com>
+
+ PR gas/18581
+ * expr.c (get_symbol_end): Rename to get_symbol_name. Add a
+ return parameter pointing to the start of the symbol. Allow
+ symbol names enclosed in double quotes.
+ (restore_line_pointer): New function. Replace the NUL character
+ inserted into the input stream with the given character. If the
+ character was a double quote, advance the input pointer.
+ * expr.h (get_symbol_end): Delete.
+ (get_symbol_name): Add prototype.
+ (restore_line_pointer): Prototype.
+ * read.h (SKIP_WHITESPACE_AFTER_NAME): New macro.
+ * doc/as.texinfo (Symbol Intro): Document that symbol names can
+ now be enclosed in double quotes.
+ * cond.c (s_ifdef): Replace get_symbol_end with get_symbol_name.
+ Use restore_line_pointer to replace the NUL in the input stream.
+ Use SKIP_WHITESPACE_AFTER_NAME to skip past the end of a symbol.
+ Check for the use of double quoted symbol names.
+ * expr.c: Likewise.
+ * config/obj-aout.c: Likewise.
+ * config/obj-coff-seh.c: Likewise.
+ * config/obj-coff.c: Likewise.
+ * config/obj-elf.c: Likewise.
+ * config/obj-evax.c: Likewise.
+ * config/obj-macho.c: Likewise.
+ * config/obj-som.c: Likewise.
+ * config/tc-alpha.c: Likewise.
+ * config/tc-arc.c: Likewise.
+ * config/tc-arm.c: Likewise.
+ * config/tc-dlx.c: Likewise.
+ * config/tc-h8300.c: Likewise.
+ * config/tc-hppa.c: Likewise.
+ * config/tc-i370.c: Likewise.
+ * config/tc-i386-intel.c: Likewise.
+ * config/tc-i386.c: Likewise.
+ * config/tc-i960.c: Likewise.
+ * config/tc-ia64.c: Likewise.
+ * config/tc-iq2000.c: Likewise.
+ * config/tc-m32r.c: Likewise.
+ * config/tc-m68hc11.c: Likewise.
+ * config/tc-m68k.c: Likewise.
+ * config/tc-microblaze.c: Likewise.
+ * config/tc-mips.c: Likewise.
+ * config/tc-mmix.c: Likewise.
+ * config/tc-mn10200.c: Likewise.
+ * config/tc-mn10300.c: Likewise.
+ * config/tc-nios2.c: Likewise.
+ * config/tc-ppc.c: Likewise.
+ * config/tc-s390.c: Likewise.
+ * config/tc-score.c: Likewise.
+ * config/tc-score7.c: Likewise.
+ * config/tc-sparc.c: Likewise.
+ * config/tc-tic4x.c: Likewise.
+ * config/tc-tic54x.c: Likewise.
+ * config/tc-tic6x.c: Likewise.
+ * config/tc-tilegx.c: Likewise.
+ * config/tc-tilepro.c: Likewise.
+ * config/tc-v850.c: Likewise.
+ * config/tc-xtensa.c: Likewise.
+ * config/tc-z80.c: Likewise.
+ * dw2gencfi.c: Likewise.
+ * dwarf2dbgc.: Likewise.
+ * ecoff.c: Likewise.
+ * read.c: Likewise.
+ * stabs.c: Likewise.
+
+2015-08-19 Jiong Wang <jiong.wang@arm.com>
+
+ * config/tc-aarch64.c (reloc_table): New relocation types support for
+ dtprel_lo12.
+ (ldst_lo12_determine_real_reloc_type): Support
+ BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12,
+ BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC,
+ BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12,
+ BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC,
+ BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12,
+ BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC,
+ BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12,
+ BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC.
+ (parse_operands): Likewise.
+ (md_apply_fix): Likewise.
+ (aarch64_force_relocation): Likewise.
+ (process_movw_reloc_info): Likewise.
+
+2015-08-19 Jiong Wang <jiong.wang@arm.com>
+
+ * config/tc-aarch64.c (reloc_table): New relocation modifiers,
+ "dtprel_hi12", "dtprel_g0", "dtprel_g0_nc", "dtprel_g1",
+ "dtprel_g1_nc", "dtprel_g2".
+ (md_apply_fix): Support new relocation types.
+ (aarch64_force_relocation): Likewise.
+ (process_movw_reloc_info): Likewise.
+
+2015-08-19 Jiong Wang <jiong.wang@arm.com>
+
+ * config/tc-aarch64.c (reloc_table): New relocation modifiers.
+ (md_apply_fix): Support BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC.
+ (aarch64_force_relocation): Likewise.
+
+2015-08-17 Alan Modra <amodra@gmail.com>
+
+ * config/tc-arm.c (s_align): Delete.
+ (md_pseudo_table): Use s_align_ptwo for "align".
+ * config/tc-arm.h (TC_ALIGN_ZERO_IS_DEFAULT): Define.
+ * read.c (s_align): Modify for TC_ALIGN_ZERO_IS_DEFAULT.
+
+2015-08-13 Alan Modra <amodra@gmail.com>
+
+ * expr.c (operand): Rewrite handling of operands starting with "0f".
+ If atof_generic only parses "-" or "+", treat as expression.
+
+2015-08-13 Alan Modra <amodra@gmail.com>
+ DJ Delorie <dj@redhat.com>
+
+ * expr.c (integer_constant): Return O_absent expression if eol.
+ (operand): For targets with both LOCAL_LABELS_FB and
+ NUMBERS_WITH_SUFFIX set, treat "0b" not followed by binary
+ digits as a local label reference. Correct handling of 0b prefix.
+ If a suffix is not allowed, error on 0B.
+
+2015-08-13 Alan Modra <amodra@gmail.com>
+
+ * doc/as.texinfo (Local Labels): Allowed range of N in local
+ labels is non-negative integers, not positive integers.
+
+2015-08-12 David Weatherford <weath@cadence.com>
+
+ * config/tc-xtensa.c (struct litpool_frag, struct litpool_seg):
+ New structures.
+ (xtensa_maybe_create_literal_pool_frag): New function.
+ (litpool_seg_list, auto_litpools, auto_litpool_limit)
+ (litpool_buf, litpool_slotbuf): New static variables.
+ (option_auto_litpools, option_no_auto_litpools)
+ (option_auto_litpool_limit): New enum identifiers.
+ (md_longopts): Add entries for auto-litpools, no-auto-litpools
+ and auto-litpool-limit.
+ (md_parse_option): Handle option_auto_litpools,
+ option_no_auto_litpools and option_auto_litpool_limit.
+ (md_show_usage): Add help for --[no-]auto-litpools and
+ --auto-litpool-limit.
+ (xtensa_mark_literal_pool_location): Record a place for literal
+ pool with a call to xtensa_maybe_create_literal_pool_frag.
+ (get_literal_pool_location): Find highest priority literal pool
+ or convert candidate to literal pool when auto-litpools are used.
+ (xg_assemble_vliw_tokens): Create literal pool after jump
+ instruction.
+ (xtensa_check_frag_count): Create candidate literal pool every
+ auto_litpool_limit frags.
+ (xtensa_relax_frag): Add jump around literals to non-empty
+ literal pool.
+ (xtensa_move_literals): Estimate literal pool addresses and move
+ unreachable literals closer to their users, converting candidate
+ to literal pool if needed.
+ (xtensa_switch_to_non_abs_literal_fragment): Only emit error
+ about missing .literal_position in case auto-litpools are not
+ used.
+ * config/tc-xtensa.h (xtensa_relax_statesE): New relaxation
+ state: RELAX_LITERAL_POOL_CANDIDATE_BEGIN.
+ * doc/as.texinfo (Xtensa options): Document --auto-litpools and
+ --no-auto-litpools options.
+ * doc/c-xtensa.texi (Xtensa options): Likewise.
+
+2015-08-12 Simon Dardis <simon.dardis@imgtec.com>
+
+ * config/tc-mips.c (move_register): Change to use 'or' only.
+ (s_cpload, s_cpsetup, s_cprestore, s_cpreturn): Update to
+ use or for move.
+
+2015-08-11 Jiong Wang <jiong.wang@arm.com>
+
+ * config/tc-aarch64.c (reloc_table): New relocation modifiers
+ "dtprel_lo12".
+ (md_apply_fix): Support BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12.
+ (aarch64_force_relocation): Likewise.
+
+2015-08-11 Jiong Wang <jiong.wang@arm.com>
+
+ * config/tc-aarch64.c (reloc_table): New relocation modifiers.
+ (md_apply_fix): Support BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC.
+ (aarch64_force_relocation): Likewise.
+
+2015-08-11 Jiong Wang <jiong.wang@arm.com>
+
+ * config/tc-aarch64.c (reloc_table): New relocation modifiers.
+ (md_apply_fix): Support BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21.
+ (aarch64_force_relocation): Likewise.
+
+2015-08-11 Nick Clifton <nickc@redhat.com>
+
+ PR gas/18765
+ * config/tc-arm.c (move_or_literal_pool): Use U suffix to remove
+ compile time warnings about constant expressions being shifted
+ into bit 31.
+ (do_iwmmxt_wldstd): Likewise.
+ (do_iwmmxt_wrwrwr_or_imm5): Likewise.
+ (md_assemble): Likewise.
+
+ PR gas/18574
+ * config/tc-msp430.c (msp430_operands): Rewrite if statements to
+ remove redundant checks.
+ (md_apply_fix): Likewise.
+
+ PR gas/18677
+ * config/tc-mmix.c (md_assemble): Fix typo checking operands with
+ a numeric constant value.
+
+ PR gas/18678
+ * config/tc-tic4x.c (tic4x_insn_check): Fix typo.
+
+ PR gas/18679
+ * config/xtensa-relax.c (same_operand_name): Fix typo.
+
+2015-08-08 Hans-Peter Nilsson <hp@axis.com>
+
+ * tc-arm.c (double_to_single, is_double_a_single): Append ULL to
+ 0xFFFFFFFFFFFFF to avoid errors on 32-bit hosts.
+
+2015-08-04 Thomas Preud'homme <thomas.preudhomme@arm.com>
+
+ * doc/c-aarch64.texi (.xword): Document directive.
+
+2015-08-03 Nick Clifton <nickc@redhat.com>
+
+ * doc/as.texinfo (Overview): Add --hash-size to the synopsis and
+ fix typo in its entry: @kindex -> @item.
+
+2015-07-28 Robert Suchanek <robert.suchanek@imgtec.com>
+
+ * config/tc-mips.c (mips_cpu_info_table): Add m5100 and m5101 entries.
+ * doc/c-mips.texi: Document m5100 and m5101 for -march=.
+
+2015-07-28 Robert Suchanek <robert.suchanek@imgtec.com>
+
+ * config/tc-mips.c (mips_cpu_info_table): Add interaptiv entry.
+ * doc/c-mips.text: Document -march=interaptiv.
+
+2015-07-27 H.J. Lu <hongjiu.lu@intel.com>
+
+ * configure: Regenerated.
+
+2015-07-24 Nick Clifton <nickc@redhat.com>
+
+ * config/tc-rl78.c (rl78_abs_sym): New local variable.
+ (md_begin): Initialise the new symbol.
+ (OPIMM): Define the value to be relative to the new symbol and not
+ the absolute section symbol.
+
+2015-07-22 Alan Modra <amodra@gmail.com>
+
+ PR gas/18687
+ * input-scrub.c (input_scrub_next_buffer): Rearrange and simplify
+ loop. Don't drop lines at end of file lacking a newline, add a
+ newline instead. Ensure partial_size is zero whenever
+ partial_where is NULL. Adjust buffer size for extra char.
+ (input_scrub_push, input_scrub_begin): Adjust buffer size here too.
+
+2015-07-20 Matthew Wahab <matthew.wahab@arm.com>
+
+ * NEWS: Mention corrected spelling of armv6kz.
+ * config/tc-arm.c (arm_cpus): Replace ARM_ARCH_V6ZK with
+ ARM_ARCH_V6KZ.
+ (arm_archs): Likewise. Also add "armv6kz" and "armv6kzt2".
+ * doc/c-arm.texi: Replace "armv6zk" with "armv6kz".
+
+2015-07-16 Jiong Wang <jiong.wang@arm.com>
+
+ * config/tc-aarch64.c (reloc_table): New relocation modifiers.
+ (md_apply_fix): Support BFD_RELOC_AARCH64_TLSLD_ADR_PREL21.
+ (aarch64_force_relocation): Ditto.
+
+2015-07-16 Matthew Wahab <matthew.wahab@arm.com>
+
+ * config/tc-arm.c (arm_fpus): Add crypto-neon-fp-armv8.1.
+ * doc/c-arm.texi (-mfpu=): Likewise. Correct the entry for
+ neon-fp-armv8.1.
+
+2015-07-16 James Greenhalgh <james.greenhalgh@arm.com>
+
+ * config/tc-arm.c (md_assemble): Rephrase the "selected processor does
+ not support ARM mode" error messages.
+
+2015-07-15 H.J. Lu <hongjiu.lu@intel.com>
+
+ * config/tc-i386.c (flag_compress_debug): Replace
+ COMPRESS_DEBUG_GNU_ZLIB with COMPRESS_DEBUG_GABI_ZLIB.
+
+2015-07-14 H.J. Lu <hongjiu.lu@intel.com>
+
+ * as.c (parse_args): Make --compress-debug-sections and
+ --compress-debug-sections=zlib the same as
+ --compress-debug-sections=zlib-gabi.
+ * doc/as.texinfo: Change --compress-debug-sections and
+ --compress-debug-sections=zlib to zlib-gabi.
+
+2015-07-09 Catherine Moore <clm@codesourcery.com>
+
+ * config/tc-mips.c (check_fpabi): Handle
+ VAL_GNU_MIPS_ABI_FP_NAN2008.
+
+2015-07-08 Ciro Santilli <ciro.santilli@gmail.com>
+
+ * doc/as.texinfo: Clarify case requirements for pseudo ops.
+
+2015-07-08 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
+
+ * config/tc-avr.c (tc_gen_reloc): Change 32 bit relocation to
+ 32 bit PC relative and update offset if the fixup is pc-relative.
+ * config/tc-avr.h (DIFF_EXPR_OK): Define to enable PC relative diff
+ relocs.
+
+2015-07-03 Alan Modra <amodra@gmail.com>
+
+ * config/tc-ppc.c (md_show_usage): Add -m821, -m850, -m860.
+ * doc/c-ppc.texi (PowerPC-Opts): Likewise.
+
+2015-07-01 Sandra Loosemore <sandra@codesourcery.com>
+ Cesar Philippidis <cesar@codesourcery.com>
+
+ * config/tc-nios2.c (nios2_min_align): New.
+ (nop): Replace with....
+ (nop_r1, nop_r2, nop_r2_cdx, nop32, nop16): New.
+ (nios2_align): Handle alignment on 2-byte boundaries when CDX
+ instructions may be present.
+ (s_nios2_align): Adjust reference to nop.
+ (CDXBRANCH, IS_CDXBRANCH): New.
+ (CDX_UBRANCH_SUBTYPE, CDX_CBRANCH_SUBTYPE): New.
+ (nios2_relax_subtype_size): Handle 2-byte CDX branches.
+ (nios2_relax_frag): Likewise.
+ (md_convert_frag): Handle R2 encodings.
+ (nios2_check_overflow): Check that low-order bits are zero
+ before applying rightshift from howto.
+ (nios2_check_overflow): Correct negative overflow calculation.
+ (nios2_diagnose_overflow): Handle signed_immed12_overflow. Issue
+ generic overflow messages for miscellaneous instruction formats.
+ (md_apply_fix): Recognize new R2 relocations. For pc_relative
+ relocations, store fixup in *valP.
+ (nios2_reglist_mask, nios2_reglist_dir): New.
+ (nios2_parse_reglist): New.
+ (nios2_parse_base_register): New.
+ (nios2_assemble_expression): Handle constant expressions designated
+ by BFD_RELOC_NONE.
+ (nios2_assemble_reg3): New.
+ (nios2_assemble_arg_c): Handle R2 instruction formats.
+ (nios2_assemble_arg_d): Likewise.
+ (nios2_assemble_arg_s): Likewise.
+ (nios2_assemble_arg_t): Likewise.
+ (nios2_assemble_arg_D): New.
+ (nios2_assemble_arg_S): New.
+ (nios2_assemble_arg_T): New.
+ (nios2_assemble_arg_i): Handle R2 instruction formats.
+ (nios2_assemble_arg_I): New.
+ (nios2_assemble_arg_u): Handle R2 instruction formats.
+ (nios2_assemble_arg_U): New.
+ (nios2_assemble_arg_V): New.
+ (nios2_assemble_arg_W): New.
+ (nios2_assemble_arg_X): New.
+ (nios2_assemble_arg_Y): New.
+ (nios2_assemble_arg_o): Handle R2 instruction formats.
+ (nios2_assemble_arg_O): New.
+ (nios2_assemble_arg_P): New.
+ (nios2_assemble_arg_j): Handle R2 instruction formats.
+ (nios2_assemble_arg_k): New.
+ (nios2_assemble_arg_l): Handle R2 instruction formats.
+ (nios2_assemble_arg_m): Likewise.
+ (nios2_assemble_arg_M): New.
+ (nios2_assemble_arg_N): New.
+ (nios2_assemble_arg_e): New.
+ (nios2_assemble_arg_f): New.
+ (nios2_assemble_arg_g): New.
+ (nios2_assemble_arg_h): New.
+ (nios2_assemble_arg_R): New.
+ (nios2_assemble_arg_B): New.
+ (nios2_assemble_args): Handle new argument letters.
+ (nios2_consume_arg): Likewise.
+ (nios2_translate_pseudo_insn): Avoid dereferencing null pointer
+ in error message.
+ (nios2_ps_insn_info_structs): Add nop.n.
+ (output_ubranch): Handle CDX branches.
+ (output_cbranch): Likewise.
+ (output_call): Handle R2 encodings.
+ (output_movia): Likewise.
+ (md_begin): Initialize nios2_min_align.
+ (md_assemble): Align to nios2_min_align. Adjust nios2_min_align
+ if a 16-bit instruction is seen.
+ (nios2_cons_align): Use appropriate nop pattern.
+
+2015-07-01 Sandra Loosemore <sandra@codesourcery.com>
+ Cesar Philippidis <cesar@codesourcery.com>
+
+ * config/tc-nios2.c: Adjust includes.
+ (OPTION_MARCH): Define.
+ (md_longopts): Add -march option.
+ (nios2_architecture): New.
+ (nios2_use_arch): New.
+ (md_parse_option): Handle OPTION_MARCH.
+ (md_show_usage): Document -march.
+ (md_begin): Set arch in BFD.
+ (nios2_elf_final_processing): New.
+ * config/tc-nios2.h (elf_tc_final_processing): Define.
+ (nios2_elf_final_processing): New.
+ * doc/c-nios2.texi (-march): Add documentation.
+
+2015-06-30 Amit Pawar <Amit.Pawar@amd.com>
+
+ * config/tc-i386.c (cpu_arch): Add .mwaitx.
+ (process_immext): Check operands for monitorx/mwaitx instructions.
+ * doc/c-i386.texi: Document mwaitx.
+
+2015-06-28 H.J. Lu <hongjiu.lu@intel.com>
+
+ * as.c (parse_args): Replace COMPRESS_DEBUG_ZLIB with
+ COMPRESS_DEBUG_GNU_ZLIB.
+ * config/tc-i386.c (flag_compress_debug): Likewise.
+
+2015-06-24 H.J. Lu <hongjiu.lu@intel.com>
+
+ * doc/as.texinfo (.cfi_lsda): Remove the extra @section.
+
+2015-06-19 Peter Bergner <bergner@vnet.ibm.com>
+
+ * config/tc-ppc.c (md_assemble): Use ppc_optional_operand_value.
+ Allow for optional operands without insert functions.
+
+2015-06-18 Nick Clifton <nickc@redhat.com>
+
+ PR gas/18541
+ * config/tc-arm.c (md_apply_fix): Add support for ADR in thumb
+ mode against a nearby symbol.
+
+2015-06-18 Nick Clifton <nickc@redhat.com>
+
+ PR gas/18481
+ * config/tc-arm.c (tc_gen_reloc): Include BFD_RELOC_ARM_TLS_LE32
+ in the same case as BFD_RELOC_ARM_TLS_IS32.
+
+2015-06-17 Nick Clifton <nickc@redhat.com>
+
+ * config/tc-arm.c (is_double_a_single): Make conditional upon the
+ availablity of a 64-bit type. Use this type for the argument and
+ mantissa.
+ (double_to_single): Likewise.
+ * config/tc-arm.c (move_or_literal_pool): Use a 64-bit type for
+ the constant value, if available. Generate a 64-bit value from a
+ bignum if supported. Only perform the second optimization for
+ PR 18500 if the 64-bit type is available.
+
+2015-06-17 Alessandro Marzocchi <alessandro.marzocchi@gmail.com>
+
+ PR gas/18500
+ * config/tc-arm.c (is_double_a_single): New function.
+ (double_to_single): New function.
+ (move_or_literal_pool): Add support for converting VLDR to VMOV.
+
+ PR gas/18499
+ * config/tc-arm.c (move_or_literal_pool): Add support for LDR Rx,=
+ to MOV.w or MVN.w for Thumb2.
+
+2015-06-17 Nicolas Pitre <nico@linaro.org>
+
+ * as.c (show_usage): Document --sectname-subst.
+ (parse_args): Add --sectname-subst.
+ * as.h (flag_sectname_subst): New.
+ * config/obj-elf.c (obj_elf_section_name): Add %S substitution.
+ * doc/as.texinfo: Document it.
+
+2015-06-15 Renlin Li <renlin.li@arm.com>
+
+ * config/tc-aarch64.c (reloc_table): New relocation modifier.
+ (md_apply_fix): Support BFD_RELOC_AARCH64_LD64_GOTOFF_LO15.
+ (aarch64_force_relocation): Ditto
+
+2015-06-13 Mark Wielaard <mjw@redhat.com>
+
+ * dwarf2dbg.c (out_header): Document EXPR->X_add_number value,
+ out_debug_aranges depends on it.
+ (out_debug_aranges): Track size of header to properly pad header
+ for address alignment.
+
+2015-06-11 John David Anglin <danglin@gcc.gnu.org>
+
+ PR gas/18427
+ * config/tc-hppa.c (last_label_symbol): Declare.
+ (pa_get_label): Return last label in current space/segment or NULL.
+ (pa_define_label): Record last label and add to root.
+ (pa_undefine_label): Remove last label from root.
+
+2015-06-08 Nick Clifton <nickc@redhat.com>
+
+ * config/tc-rx.c (rx_op): Correct handling of integer bignums.
+
+2015-06-04 Matthew Wahab <matthew.wahab@arm.com>
+
+ * NEWS: Mention ARMv8.1 support in the Aarch64 port.
+ * config/tc-aarch64.c (aarch64_arch_option_table): Add "armv8.1-a".
+ * doc/c-aarch64.texi (-march): Add "armv8.1-a".
+
+2015-06-04 Renlin Li <renlin.li@arm.com>
+
+ * config/tc-arm.c (arm_init_frag): Use frag's thumb_mode information
+ when available.
+
+2015-06-04 Nick Clifton <nickc@redhat.com>
+
+ * config/tc-h8300.c (md_section_align): Fix compile time warning
+ about left shifting a negative value.
+
+2015-06-03 Matthew Wahab <matthew.wahab@arm.com>
+
+ * config/tc-arm.c (arm_archs): Add "armv8.1-a".
+ * doc/c-arm.texi (ARM Options, -march): Add "armv8.1-a".
+ * NEWS: Mention ARMv8.1 support.
+
+2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
+
+ * config/tc-arm.c (arm_ext_pan): New.
+ (do_setpan): New, encode an ARM SETPAN instruction.
+ (do_t_setpan): New, encode a Thumb SETPAN instruction.
+ (insns): Add "setpan".
+ (arm_extensions): Add "pan".
+ * doc/c-arm.texi (ARM Options): Add "pan" to list of -mcpu processor
+ extensions.
+
+2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
+
+ * config/tc-aarch64.c (aarch64_features): Add "rdma".
+ * doc/c-aarch64.texi (AArch64 Extensions): Add "rdma".
+
+2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
+
+ * config/tc-aarch64.c (aarch64_features): Add "lor".
+ * doc/c-aarch64.c (Aarch64 Extensions): Add "lor" to list of
+ architecture extensions.
+
+2015-06-01 Matthew Wahab <matthew.wahab@arm.com>
+
+ * config/tc-aarch64.c (parse_sys_reg): New parameter. Check target
+ support. Fix whitespace.
+ (parse_operands): Update for parse_sys_reg changes.
+ (aarch64_features): Add "pan".
+ * doc/c-aarch64.texi (Aarch64 Extensions): Add "pan".
+
+2015-06-01 Jiong Wang <jiong.wang@arm.com>
+
+ * config/tc-aarch64.c (reloc_table): New relocation modifiers.
+ (md_apply_fix): Support BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14.
+ (aarch64_force_relocation): Ditto.
+
+2015-06-01 Jiong Wang <jiong.wang@arm.com>
+
+ * config/tc-aarch64.c (reloc_table): New relocation modifiers.
+ (md_apply_fix): Support BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15.
+ (aarch64_force_relocation): Ditto.
+
+2015-05-28 Catherine Moore <clm@codesourcery.com>
+ Bernd Schmidt <bernds@codesourcery.com>
+ Paul Brook <paul@codesourcery.com>
+
+ * config/tc-alpha.c (all_cfi_sections): Declare.
+ (s_alpha_ent): Initialize all_cfi_sections.
+ (alpha_elf_md_end): Invoke cfi_set_sections.
+ * config/tc-mips.c (md_apply_fix): Handle BFD_RELOC_NONE.
+ (s_ehword): Use BFD_RELOC_32_PCREL.
+ (mips_fix_adjustable): Handle BFD_RELOC_32_PCREL.
+ (mips_cfi_reloc_for_encoding): New function.
+ * tc-mips.h (DWARF2_FDE_RELOC_SIZE): Redefine.
+ (DWARF2_FDE_RELOC_ENCODING): Define.
+ (tc_cfi_reloc_for_encoding): Define.
+ (mips_cfi_reloc_for_encoding): Define.
+ (tc_compact_eh_opcode_stop): Define.
+ (tc_compact_eh_opcode_pad): Define.
+ * doc/as.texinfo: Document Compact EH extensions.
+ * doc/internals.texi: Likewise.
+ * dw2gencfi.c (EH_FRAME_LINKONCE): Redefine.
+ (tc_cfi_reloc_for_encoding): Provide default.
+ (compact_eh): Declare.
+ (emit_expr_encoded): New function.
+ (get_debugseg_name): Add Compact EH support.
+ (alloc_debugseg_item): Likewise.
+ (cfi_set_sections): New function.
+ (dot_cfi_fde_data): New function.
+ (dot_cfi_personality_id): New function.
+ (dot_cfi_inline_lsda): New function.
+ (cfi_pseudo_table): Add cfi_fde_data, cfi_personality_id,
+ and cfi_inline_lsda.
+ (dot_cfi_personality): Add Compact EH support.
+ (dot_cfi_lsda): Likewise.
+ (dot_cfi_sections): Likewise.
+ (dot_cfi_startproc): Likewise.
+ (get_cfi_seg): Likewise.
+ (output_compact_unwind_data): New function.
+ (output_cfi_insn): Add Compact EH support.
+ (output_cie): Likewise.
+ (output_fde): Likewise.
+ (cfi_finish): Likewise.
+ (cfi_emit_eh_header): New function.
+ (output_eh_header): New function.
+ * dw2gencfi.h (cfi_set_sections): Declare.
+ (SUPPORT_COMPACT_EH): Define.
+ (MULTIPLE_FRAME_SECTIONS): Define.
+ New enumeration to describe the Compact EH header format.
+ (fde_entry): Add new fields personality_id, eh_header_type, eh_data_size,
+ eh_data, eh_loc and sections.
+ (CFI_EMIT_eh_frame, CFI_EMIT_debug_frame, CFI_EMIT_target,
+ CFI_EMIT_eh_frame_compact): Define.
+
+2015-05-26 Max Filippov <jcmvbkbc@gmail.com>
+
+ * config/tc-xtensa.c (xtensa_move_literals): Check that
+ search_frag is non-NULL. Report error if literal frag is not
+ found.
+
+2015-05-22 Nick Clifton <nickc@redhat.com>
+
+ PR gas/18446
+ * read.c (output_big_sleb128): Use U suffix to prevent compile
+ time warning.
+
+2015-05-19 Jiong Wang <jiong.wang@arm.com>
+
+ * config/tc-aarch64.c (process_movw_reloc_info): Sort relocation case
+ labels alphabetically.
+ (md_apply_fix): Ditto.
+ (aarch64_force_relocation): Ditto.
+
+2015-05-15 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR binutis/18386
+ * config/tc-i386.c (OPTION_MAMD64): New.
+ (OPTION_MINTEL64): Likewise.
+ (md_longopts): Add -mamd64 and -mintel64.
+ (md_parse_option): Handle OPTION_MAMD64 and OPTION_MINTEL64.
+ (md_show_usage): Add -mamd64 and -mintel64.
+ * doc/c-i386.texi: Document -mamd64 and -mintel64.
+
+2015-05-15 H.J. Lu <hongjiu.lu@intel.com>
+
+ * config/tc-i386.c (shared): New.
+ (OPTION_MSHARED): Likewise.
+ (elf_symbol_resolved_in_segment_p): Add relocation argument.
+ Check PLT relocations and shared.
+ (md_estimate_size_before_relax): Pass fragP->fr_var to
+ elf_symbol_resolved_in_segment_p.
+ (md_longopts): Add -mshared.
+ (md_show_usage): Likewise.
+ (md_parse_option): Handle OPTION_MSHARED.
+ * doc/c-i386.texi: Document -mshared.
+
+2015-05-14 H.J. Lu <hongjiu.lu@intel.com>
+
+ * write.c (compress_debug): Don't write the zlib header, which
+ is handled by bfd_update_compression_header.
+
+2015-05-13 Max Filippov <jcmvbkbc@gmail.com>
+
+ * config/tc-xtensa.c (xtensa_relax_frag): Allow trampoline to be
+ closer than J_RANGE / 2 to jump frag.
+
+2015-05-11 H.J. Lu <hongjiu.lu@intel.com>
+
+ * configure.tgt (arch): Set to iamcu for i386-*-elfiamcu target.
+ * config/tc-i386.c (i386_mach): Support iamcu.
+ (i386_target_format): Likewise.
+
+2015-05-11 H.J. Lu <hongjiu.lu@intel.com>
+
+ * config/tc-i386.c (cpu_arch): Add iamcu.
+ (i386_align_code): Handle PROCESSOR_IAMCU.
+ (i386_arch): Likewise.
+ (i386_mach): Likewise.
+ (i386_target_format): Likewise.
+ (valid_iamcu_cpu_flags): New function.
+ (check_cpu_arch_compatible): Only allow Intel MCU instructions
+ when targeting Intel MCU.
+ (set_cpu_arch): Call valid_iamcu_cpu_flags to check if CPU flags
+ are valid for Intel MCU.
+ (md_parse_option): Likewise.
+ * tc-i386.h (ELF_TARGET_IAMCU_FORMAT): New.
+ (processor_type): Add PROCESSOR_IAMCU.
+ * doc/c-i386.texi: Document iamcu.
+
+2015-05-08 Nick Clifton <nickc@redhat.com>
+
+ PR gas/18347
+ * config/tc-arm.h (TC_EQUAL_IN_INSN): Define.
+ * config/tc-arm.c (arm_tc_equal_in_insn): New function. Move
+ the symbol name checking code to here from...
+ (md_undefined_symbo): ... here.
+
+2015-05-07 H.J. Lu <hongjiu.lu@intel.com>
+
+ * config/tc-i386.c (elf_symbol_resolved_in_segment_p): New.
+ (md_estimate_size_before_relax): Use it.
+
+2015-05-06 Jose E. Marchesi <jose.marchesi@oracle.com>
+
+ * config/tc-sparc.c: Typo in comment fixed.
+
+2015-05-06 Jose E. Marchesi <jose.marchesi@oracle.com>
+
+ * config/tc-sparc.c (sparc_ip): Support the %ncc "natural"
+ condition codes
+ * doc/c-sparc.texi (Sparc-Regs): Document %ncc.
+
+2015-05-06 Nick Clifton <nickc@redhat.com>
+
+ * doc/as.texinfo (Dollar Local Labels): Note that these are only
+ supported on some targets.
+
+2015-05-06 Renlin Li <renlin.li@arm.com>
+
+ * config/tc-aarch64.c (mapping_state): Recording alignment before exit.
+
+2015-05-05 Renlin Li <renlin.li@arm.com>
+
+ * config/tc-aarch64.c (aarch64_init_frag): Always generate mapping
+ symbols.
+
+2015-05-05 Nick Clifton <nickc@redhat.com>
+
+ * config/tc-msp430.c (MAX_OP_LEN): Increase to 4096.
+ (msp430_make_init_symbols): New function.
+ (msp430_section): Call it.
+ (msp430_frob_section): Likewise.
+
+2015-05-02 Max Filippov <jcmvbkbc@gmail.com>
+
+ * config/tc-xtensa.c (cached_fixupS, fixup_cacheS): New typedefs.
+ (struct cached_fixup, struct fixup_cache): New structures.
+ (fixup_order, xtensa_make_cached_fixup),
+ (xtensa_realloc_fixup_cache, xtensa_cache_relaxable_fixups),
+ (xtensa_find_first_cached_fixup, xtensa_delete_cached_fixup),
+ (xtensa_add_cached_fixup): New functions.
+ (xtensa_relax_frag): Cache fixups pointing at potentially
+ oversized jumps at the beginning of every relaxation pass. Only
+ check subset of this cache in the reach of single jump from the
+ trampoline frag currently being relaxed.
+
+2015-05-01 Nick Clifton <nickc@redhat.com>
+
+ * config/rl78-parse.y (MULU): Remove ISA_G14.
+ (MULH, DIVHU, DIVWU, MACHI, MACH): Update error strings.
+
+2015-05-01 H.J. Lu <hongjiu.lu@intel.com>
+
+ * config/tc-i386.c (i386_elf_emit_arch_note): Removed.
+ * config/tc-i386.h (md_end): Likewise.
+ (i386_elf_emit_arch_note): Likewise.
+
+2015-05-01 H.J. Lu <hongjiu.lu@intel.com>
+
+ * configure.tgt: Support i386-*-elf*.
+
+2015-04-30 DJ Delorie <dj@redhat.com>
+
+ * config/rl78-defs.h (rl78_isa_g10): New.
+ (rl78_isa_g13): New.
+ (rl78_isa_g14): New.
+ * config/rl78-parse.y (ISA_G10): New.
+ (ISA_G13): New.
+ (ISA_G14): New.
+ (MULHU, MULH, MULU, DIVHU, DIVWU, MACHU, MACH): Use them.
+ * config/tc-rl78.c (rl78_isa_g10): New.
+ (rl78_isa_g13): New.
+ (rl78_isa_g14): New.
+
+2015-04-30 H.J. Lu <hongjiu.lu@intel.com>
+
+ * config/tc-i386.c (i386_target_format): Use "else if" on
+ cpu_arch_isa.
+
+2015-04-30 Nick Clifton <nickc@redhat.com>
+
+ PR gas/18347
+ * config/tc-arm.c (md_undefined_symbol): Issue a warning message
+ (if enabled) when the user creates a symbol with the same name as
+ an ARM instruction.
+ (flag_warn_syms): New static variable.
+ (arm_opts): Add mwarn-syms and mno-warn-syms.
+ * doc/c-arm.texi (ARM Options): Document the -m[no-]warn-syms
+ options.
+
+ PR gas/18353
+ * doc/as.texinfo (Zero): Add documentation of the .zero pseudo-op.
+
+2015-04-29 Nick Clifton <nickc@redhat.com>
+
+ PR 18256
+ * config/tc-arm.c (encode_arm_cp_address): Issue an error message
+ if the operand is neither a register nor a vector.
+
+2015-04-29 Nick Clifton <nickc@redhat.com>
+
+ * doc/as.texinfo (Set): Note that a symbol cannot be set multiple
+ times if the expression is not constant and the target uses linker
+ relaxation.
+
+2015-04-28 Renlin Li <renlin.li@arm.com>
+
+ * config/tc-arm.c (arm_init_frag): Always emit mapping symbols.
+
+2015-04-28 Nick Clifton <nickc@redhat.com>
+
+ PR 18313
+ * cond.c (s_if): Stop compile time warning about stopc being used
+ before it is set.
+ (s_ifc): Likewise.
+
+2015-04-27 Renlin Li <renlin.li@arm.com>
+
+ * config/tc-aarch64.c (s_aarch64_inst): Don't align code for non-text
+ section.
+ (md_assemble): Likewise, move the align code outside the loop.
+
+2015-04-24 Jim Wilson <jim.wilson@linaro.org>
+
+ * config/tc-aarch64.c (aarch64_cpus): Add CRC and CRYPTO features
+ for thunderx.
+
+2015-04-24 Richard Earnshaw <rearnsha@arm.com>
+
+ * config/tc-arm.h (arm_min): New function.
+ (SUB_SEGMENT_ALIGN): Define.
+
+2015-04-23 Matthew Fortune <matthew.fortune@imgtec.com>
+
+ * config/tc-mips.c (macro): State the recommended way of creating
+ 32-bit or 64-bit addresses.
+
+2015-04-23 Jan Beulich <jbeulich@suse.com>
+
+ * config/tc-i386.c (match_mem_size): Also allow no size
+ specification when broadcasting.
+
+2015-04-20 H.J. Lu <hongjiu.lu@intel.com>
+
+ * doc/as.texinfo (Bundle directives): Shorten menu entry and
+ use @subsection.
+ (CFI directives): Use @subsection.
+ (SH-Dependent, SH64-Dependent): Moved after SCORE-Dependent.
+ * doc/c-i386.texi (i386-Mnemonics): Use @subsection.
+
+2015-04-17 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
+
+ * config/tc-avr.c (create_record_for_frag): Rename link to
+ prop_rec_link.
+
+2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
+
+ * NEWS: Mention
+ --compress-debug-sections=[none|zlib|zlib-gnu|zlib-gabi].
+
+2015-04-14 H.J. Lu <hongjiu.lu@intel.com>
+
+ * as.h (compressed_debug_section_type): Removed.
+
+2015-04-14 Nick Clifton <nickc@redhat.com>
+
+ * config/tc-rl78.h (TC_LINKRELAX_FIXUP): Define.
+ (TC_FORCE_RELOCATION_SUB_SAME): Define.
+ (DWARF2_USE_FIXED_ADVANCE_PC): Define.
+
+2015-04-10 Nick Clifton <nickc@redhat.com>
+
+ PR binutils/18198
+ * doc/c-arm.texi (ARM Options): Add a note about the interaction of
+ the -EB option with the linker's --be8 option.
+
+2015-04-09 Hans-Peter Nilsson <hp@axis.com>
+
+ * doc/c-rx.texi: Fix markup typos in last change.
+
+2015-04-09 Nick Clifton <nickc@redhat.com>
+
+ * config/tc-rx.c (enum options): Add OPTION_DISALLOW_STRING_INSNS.
+ (md_longopts): Add -mno-allow-string-insns.
+ (md_parse_option): Handle -mno-allow-string-insns.
+ (md_show_usage): Mention -mno-allow-string-insns.
+ (rx_note_string_insn_use): New function. Produces an error
+ message if a string insn is used when it is not allowed.
+ * config/rx-parse.y (SCMPU): Call rx_note_string_insn_use.
+ (SMOVU, SMOVB, SMOVF, SUNTIL, SWHILE, RMPA): Likewise.
+ * config/rx-defs.h (rx_note_string_insn_use): Prototype.
+ * doc/c-rx.texi: Document -mno-allow-string-insns.
+
+2015-04-08 H.J. Lu <hongjiu.lu@intel.com>
+
+ * as.c (show_usage): Update --compress-debug-sections.
+ (std_longopts): Use optional_argument on compress-debug-sections.
+ (parse_args): Handle
+ --compress-debug-sections={none|zlib|zlib-gnu|zlib-gabi}.
+ * as.h (compressed_debug_section_type): New.
+ (flag_compress_debug): Change type to compressed_debug_section_type.
+ --compress-debug-sections={none|zlib|zlib-gnu|zlib-gabi}.
+ * write.c (compress_debug): Set BFD_COMPRESS_GABI for
+ --compress-debug-sections=zlib-gabi. Call
+ bfd_get_compression_header_size to get compression header size.
+ Don't rename section name for --compress-debug-sections=zlib-gabi.
+ * config/tc-i386.c (compressed_debug_section_type): Set to
+ COMPRESS_DEBUG_ZLIB.
+ * doc/as.texinfo: Document
+ --compress-debug-sections={none|zlib|zlib-gnu|zlib-gabi}.
+
+2015-04-07 Renlin Li <renlin.li@arm.com>
+
+ * config/tc-aarch64.c (mapping_state): Use subseg_text_p.
+ (s_aarch64_inst): Likewise.
+ (md_assemble): Likewise.
+
+2015-04-06 H.J. Lu <hongjiu.lu@intel.com>
+
+ * write.c (compress_debug): Use bfd_putb64 to write uncompressed
+ section size.
+
+2015-04-05 H.J. Lu <hongjiu.lu@intel.com>
+
+ * write.c (compress_debug): Don't write the zlib header if
+ compressed section size is the same as before compression.
+
+2015-04-02 Nick Clifton <nickc@redhat.com>
+
+ PR gas/18189
+ * config/tc-microblaze.c (parse_imm): Use offsetT as the type for
+ min and max parameters. Sign extend values before testing.
+
+2015-04-02 Renlin Li <renlin.li@arm.com>
+
+ * config/tc-aarch64.c (mapping_state): Emit MAP_DATA within text section in order.
+ (mapping_state_2): Don't emit MAP_DATA here.
+ (s_aarch64_inst): Align frag during state transition.
+ (md_assemble): Likewise.
+
+2015-04-02 Ed Maste <emaste@freebsd.org>
+
+ * config/tc-aarch64.c (set_error_kind): Delete.
+ (set_error_message): Delete.
+
+2015-04-02 H.J. Lu <hongjiu.lu@intel.com>
+
+ * configure: Regenerated.
+
+2015-04-01 Evandro Menezes <e.menezes@samsung.com>
+
+ * config/tc-aarch64.c: Add support for Samsung Exynos M1.
+ * doc/c-aarch64.texi (-mcpu=): Add "exynos-m1".
+
+2015-04-01 Evandro Menezes <e.menezes@samsung.com>
+
+ * config/tc-arm.c: Add support for Samsung Exynos M1.
+ * doc/c-arm.texi (-mcpu=): Add "exynos-m1".
+
+2015-04-01 H.J. Lu <hongjiu.lu@intel.com>
+
+ * configure: Regenerated.
+
+2015-03-31 Ed Schouten <ed@nuxi.nl>
+
+ * configure.tgt (fmt): Set to elf for *-*-cloudabi*.
+
+2015-03-31 H.J. Lu <hongjiu.lu@intel.com>
+
+ * configure.ac: Revert the AM_ZLIB change.
+ * Makefile.in: Regenerated.
+ * aclocal.m4: Likewise.
+ * configure: Likewise.
+
+2015-03-31 H.J. Lu <hongjiu.lu@intel.com>
+
+ * Makefile.am (ZLIBINC): New.
+ (AM_CFLAGS): Add $(ZLIBINC).
+ * as.c: (show_usage): Don't check HAVE_ZLIB_H.
+ (parse_args): Likewise.
+ * compress-debug.c: Don't check HAVE_ZLIB_H to include <zlib.h>.
+ (compress_init): Don't check HAVE_ZLIB_H.
+ (compress_data): Likewise.
+ (compress_finish): Likewise.
+ * configure.ac (AM_ZLIB): Removed.
+ (zlibinc): New. AC_SUBST.
+ Add --with-system-zlib.
+ * Makefile.in: Regenerated.
+ * config.in: Likewise.
+ * configure: Likewise.
+ * doc/Makefile.in: Likewise.
+
+2015-03-27 H.J. Lu <hongjiu.lu@intel.com>
+
+ * config/tc-i386.c (cpu_flags_set): Removed.
+
+2015-03-25 Renlin Li <renlin.li@arm.com>
+
+ * config/tc-aarch64.c (mapping_state): Remove first MAP_DATA emitting
+ code.
+ (mapping_state_2): Emit first MAP_DATA symbol here.
+
+2015-03-24 H.J. Lu <hongjiu.lu@intel.com>
+
+ PR gas/18087
+ * write.c (compress_debug): Don't write the zlib header if
+ compression didn't make the section smaller.
+
+2015-03-24 Terry Guo <terry.guo@arm.com>
+
+ * config/tc-arm.c (no_cpu_selected): Use new macro to compare
+ features.
+ (parse_psr): Likewise.
+ (do_t_mrs): Likewise.
+ (do_t_msr): Likewise.
+ (static const arm_feature_set arm_ext_*): Defined with new macros.
+ (static const arm_feature_set arm_cext_*): Likewise.
+ (static const arm_feature_set fpu_fpa_ext_*): Likewise.
+ (static const arm_feature_set fpu_vfp_ext_*): Likewise.
+ (deprecated_coproc_regs): Likewise.
+ (UL_BARRIER): Likewise.
+ (barrier_opt_names): Likewise.
+ (arm_cpus): Likewise.
+ (arm_extensions): Likewise.
+
+2015-03-20 H.J. Lu <hongjiu.lu@intel.com>
+
+ * config/tc-i386.c (i386_align_code): Limit multi-byte nop
+ instructions to 10 bytes.
+
+2015-03-19 Nick Clifton <nickc@redhat.com>
+
+ * config/tc-rl78.c (enum options): Add G13 and G14.
+ (md_longopts): Add -mg13 and -mg14.
+ (md_parse_option): Handle -mg13 and -mg14.
+ (md_show_usage): List -mg13 and -mg14.
+ * doc/c-rl78.texi: Add description of -mg13 and -mg14 options.
+
+2015-03-18 Jon Turney <jon.turney@dronecode.org.uk>
+ Nick Clifton <nickc@redhat.com>
+
+ PR binutils/18087
+ * doc/as.texinfo: Note that when gas compresses debug sections the
+ compression is only performed if it makes the section smaller.
+ * write.c (compress_debug): Do not compress a debug section if
+ doing so would make it larger.
+
+2015-03-17 Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>
+
+ * config/tc-i386.c (cpu_arch): Add PROCESSOR_ZNVER flags.
+ (i386_align_code): Add PROCESSOR_ZNVER cases.
+ * config/tc-i386.h (processor_type): Add PROCESSOR_ZNVER.
+ * doc/c-i386.texi: Add znver1 and clzero.
+
+2015-03-16 Nick Clifton <nickc@redhat.com>
+
+ * dwarf2dbg.c (out_header): Remove spurious #if 1.
+
+2015-03-13 Jiong Wang <jiong.wang@arm.com>
+
+ * config/tc-aarch64.c (warn_unpredictable_ldst): Don't warn on reg
+ number 31.
+
+2015-03-13 Jiong Wang <jiong.wang@arm.com>
+
+ * config/tc-aarch64.h (SUB_SEGMENT_ALIGN): Define to be zero.
+
+2015-03-12 Andrew Bennett <andrew.bennett@imgtec.com>
+
+ * config/tc-mips.c (mips_cpu_info_table): Add i6400 entry.
+ * doc/c-mips.texi: Document i6400 -march option.
+
+2015-03-12 Nick Clifton <nickc@redhat.com>
+
+ PR gas/17444
+ * config/tc-arm.h (MD_APPLY_SYM_VALUE): Pass the current segment
+ to arm_apply_sym_value. Update prototype.
+ * config/tc-arm.c (arm_apply_sym_value): Add segment argument.
+ Do not apply the value if the symbol is in a different segment to
+ the current segment.
+
+2015-03-11 Alan Modra <amodra@gmail.com>
+
+ * config/tc-ppc.c (md_assemble): Don't abort on 8 byte insn fixups.
+ (md_apply_fix): Report an error on data-only fixups used with insns.
+
+2015-03-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
+
+ * config/tc-s390.c (md_gather_operands): Check for valid
+ length field operands.
+
+2015-03-10 Michael Perkins <perkinsmg75@yahoo.co.uk>
+
+ * config/tc-arm.c (parse_operands): Fix bug setting writeback
+ values for '^' on OP_REGLSTs.
+ (do_push_pop): Add new writeback constraint.
+
+2015-03-10 Renlin Li <renlin.li@arm.com>
+
+ * config/tc-arm.c (mapping_state): Remove first MAP_DATA emitting code.
+ (mapping_state_2): Emit first MAP_DATA symbol here.
+
+2015-03-10 Matthew Wahab <matthew.wahab@arm.com>
+
+ * config/tc-aarch64.c (mapping_state): Set minimum alignment for
+ code sections.
+
+2015-03-10 Nick Clifton <nickc@redhat.com>
+
+ PR gas/17852
+ * config/tc-arm.c (md_begin): Ensure that selected_cpu is
+ initialised when CPU_DEFAULT is defined.
+
+2015-03-05 Nick Clifton <nickc@redhat.com>
+
+ * config/tc-v850.c (md_parse_option): Fix code to set or clear
+ EF_RH850_DATA_ALIGN8 bit in ELF header, based upon the use of the
+ -m8byte-align and -m4byte-align command line options.
+
+2015-03-04 Richard Sandiford <richard.sandiford@arm.com>
+
+ PR gas/17843
+ * config/tc-aarch64.c (process_movw_reloc_info): Allow
+ R_AARCH64_TLSLE_MOVW_TPREL_G0_NC and R_AARCH64_TLSLE_MOVW_TPREL_G1_NC
+ for MOVK.
+
+2015-02-28 Alan Modra <amodra@gmail.com>
+
+ * write.c (SUB_SEGMENT_ALIGN): Don't pad non-code sections at
+ end to their alignment.
+
+2015-02-19 Marcus Shawcroft <marcus.shawcroft@arm.com>
+
+ * config/tc-aarch64.c (reloc_table_entry): Generate
+ BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21.
+ (md_apply_fix, aarch64_force_relocation): Handle
+ BFD_RELOC_AARCH64_TLSGD_ADR_PREL21.
+
+2015-02-19 Marcus Shawcroft <marcus.shawcroft@arm.com>
+
+ * config/tc-aarch64.c (reloc_table_entry): Generate
+ BFD_RELOC_AARCH64_TLSGD_ADR_PREL21.
+ (md_apply_fix, aarch64_force_relocation): Handle
+ BFD_RELOC_AARCH64_TLSGD_ADR_PREL21.
+
+2015-02-19 Marcus Shawcroft <marcus.shawcroft@arm.com>
+
+ * config/tc-aarch64.c (reloc_table_entry): Generate
+ BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19.
+ (md_apply_fix, aarch64_force_relocation): Handle
+ BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19.
+
+2015-02-26 Marcus Shawcroft <marcus.shawcroft@arm.com>
+
+ * config/tc-aarch64.c (reloc_table_entry): Add ld_literal_type.
+ (reloc_table): Likewise.
+ (parse_address_main): Use ld_literal_type.
+
+2015-02-26 Marcus Shawcroft <marcus.shawcroft@arm.com>
+
+ * config/tc-aarch64.c (reloc_table_entry): Add adr_type.
+ (reloc_table): Likewise.
+ (parse_address_main): Use adr_type.
+
+2015-02-26 Marcus Shawcroft <marcus.shawcroft@arm.com>
+
+ * config/tc-aarch64.c (aarch64_arch_any, aarch64_arch_node): Remove.
+
+2015-02-25 Andrew Burgess <andrew.burgess@embecosm.com>
+
+ * config/tc-avr.c: Add elf32-avr.h include.
+ (struct avr_property_record_link): New structure.
+ (avr_output_property_section_header): New function.
+ (avr_record_size): New function.
+ (avr_output_property_record): New function.
+ (avr_create_property_section): New function.
+ (avr_handle_align): New function.
+ (exclude_section_from_property_tables): New function.
+ (create_record_for_frag): New function.
+ (append_records_for_section): New function.
+ (avr_create_and_fill_property_section): New function.
+ (avr_post_relax_hook): New function.
+ * config/tc-avr.h (md_post_relax_hook): Define.
+ (avr_post_relax_hook): Declare.
+ (HANDLE_ALIGN): Define.
+ (avr_handle_align): Declare.
+ (strut avr_frag_data): New structure.
+ (TC_FRAG_TYPE): Define.
+
+2015-02-25 Matthew Wahab <matthew.wahab@arm.com>
+
+ * doc/c-arm.texi (-mcpu=): Add cortex-a53, cortex-a57 and
+ cortex-a72.
+
+2015-02-24 Nick Clifton <nickc@redhat.com>
+
+ * config/tc-v850.c (soft_float): New variable.
+ (v850_data_8): New variable.
+ (md_show_usage): Add -msoft-float/-mhard-float.
+ (md_parse_option): Likewise.
+ (md_begin): Set the default value of soft_float.
+ (v850_md_end): New function. Creates a note section.
+ * config/tc-v850.h (md_end): Define.
+ * doc/c-v850.texi: Document -msoft-float/-mhard-float.
+
+2015-02-23 Yoshinori Sato <ysato@users.sourceforge.jp>
+
+ * config/tc-h8300.c (line_separater_chars): Add a version for
+ h8300-linux that includes a separator.
+ (default_mach): New variable.
+ (md_main): Use it.
+ (md_longopts): Add '--march' option.
+ (md_parse_option): Parse the new option.
+ * config/tc-h8300.h (TARGET_FORMAT): Add elf32-h8300-linux.
+ * configure.tgt: Add h8300-*-linux
+ * doc/c-h8300.texi: Document --march.
+
+2015-02-23 Nick Clifton <nickc@redhat.com>
+
+ PR 17940
+ * dwarf2dbg.c (out_header): When generating dwarf sections use
+ real symbols not temps for the start and end symbols.
+ * config/tc-msp430.h (TC_FORCE_RELOCATION_SUB_SAME): Also prevent
+ adjustments to relocations in debug sections.
+ (TC_LINKRELAX_FIXUP): Likewise.
+
+2015-02-19 Alan Modra <amodra@gmail.com>
+
+ * doc/as.texinfo (Local Symbol Names): Don't use ':' in pxref.
+ * doc/c-i386.texi: Reorder i386-Bugs after i386-Arch.
+
+2015-02-11 Matthew Wahab <matthew.wahab@arm.com>
+
+ * config/tc-aarch64.c (aarch64_cpus): Fix code formatting.
+
+2015-02-11 Matthew Wahab <matthew.wahab@arm.com>
+
+ * config/tc-arm.c: Add support for Cortex-A72.
+
+2015-02-09 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
+
+ * config/tc-arm.c (warn_deprecated_sp): Use as_tsktsk instead
+ of as_warn for deprecation messages.
+ (encode_arm_addr_mode_2): Likewise.
+ (check_obsolete): Likewise.
+ (do_rd_rm_rn): Likewise.
+ (do_co_reg): Likewise.
+ (do_setend): Likewise.
+ (do_t_mov_cmp): Likewise.
+ (do_neon_ldr_str): Likewise.
+ (opcode_lookup): Likewise.
+ (if_fsm_post_encode): Likewise.
+ (md_assemble): Likewise.
+
+2015-02-06 Jan Beulich <jbeulich@suse.com>
+
+ * dw2gencfi.c (select_cie_for_fde): Also bail on CFI_label.
+ (cfi_change_reg_numbers): Also do nothing for CFI_label.
+ (cfi_pseudo_table): Also handle .cfi_label when not supporting
+ CFI directives.
+
+2015-02-05 Alan Modra <amodra@gmail.com>
+
+ * config/tc-msp430.c (md_assemble): Correct size passed to
+ extract_cmd. Remove index check.
+
+2015-02-04 Matthew Wahab <matthew.wahab@arm.com>
+
+ * config/tc-aarch64.c (aarch64_cpus): Add support for Cortex-A72.
+ * doc/c-aarch64.texi (-mcpu=): Add "cortex-a72".
+
+2015-02-04 Nick Clifton <nickc@redhat.com>
+
+ * config/rl78-parse.y (addsubw): Fix encoding of [HL] variant of
+ these instructions.
+
+2015-02-03 Renlin Li <renlin.li@arm.com>
+
+ * doc/c-aarch64.texi (.arch): Document the directive.
+ (.arch_extension): Likewise.
+
+2015-02-03 Nick Clifton <nickc@redhat.com>
+
+ * config/tc-rl78.h (TC_PARSE_CONS_EXPRESSION): Define.
+
+2015-01-28 James Bowman <james.bowman@ftdichip.com>
+
+ * Makefile.am: Add FT32 files.
+ * config/tc-ft32.c: New file.
+ * config/tc-ft32.h: New file.
+ * configure.tgt: Add FT32 support.
+ * Makefile.in: Regenerate.
+ * po/POTFILES.in: Regenerate.
+
+2015-01-27 Kuan-Lin Chen <kuanlinchentw@gmail.com>
+
+ * config/tc-nds32.c (do_pseudo_la_internal): Limit the second argument
+ of instruction la to a symbol.
+
+2015-01-27 Kuan-Lin Chen <kuanlinchentw@gmail.com>
+
+ * config/tc-nds32.c (nds32_parse_name): Ignore when the input is
+ section name.
+
+2015-01-19 Alan Modra <amodra@gmail.com>
+
+ * read.c (s_reloc): Match BFD_RELOC_NONE, BFD_RELOC{8,16,32,64}.
+ * write.c (get_frag_for_reloc): Allow match just past end of frag.
+
+2015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
+
+ * config/tc-s390.c (struct pd_reg): Remove.
+ (pre_defined_registers): Remove.
+ (REG_NAME_CNT): Remove.
+ (reg_name_search): Calculate the register number instead of doing
+ a lookup.
+ (register_name, tc_s390_regname_to_dw2regnum): Adopt to the new
+ reg_name_search signature.
+ (s390_parse_cpu): Support the new arch string z13.
+ (s390_insert_operand): Support for vector registers with the extra
+ field for the fifth bit of each vector register operand.
+ (md_gather_operand): Adjust to the new handling of optional
+ parameters.
+
+ * doc/as.texinfo: Document the z13 cpu string.
+
+2015-01-13 Matthew Wahab <matthew.wahab@arm.com>
+
+ * config/tc-arm.c (parse_ifimm_zero): Accept #0x0 as a synonym for
+ #0, restoring previous behaviour.
+
+2015-01-12 Jan Beulich <jbeulich@suse.com>
+
+ * dw2gencfi.c (cfi_add_label, dot_cfi_label): New.
+ (cfi_pseudo_table): Add "cfi_label".
+ (output_cfi_insn): Handle CFI_label.
+ (select_cie_for_fde): Als terminate CIE when encountering
+ CFI_label.
+ * dw2gencfi.h (cfi_add_label): Declare.
+ (struct cfi_insn_data): New member "sym_name".
+ (CFI_label): New.
+ * read.c (read_symbol_name): Drop "static".
+ * read.h (read_symbol_name): Declare.
+
+2015-01-12 Jan Beulich <jbeulich@suse.com>
+
+ * config/tc-arm.c (do_neon_shl_imm): Check immediate range.
+ (do_neon_qshl_imm): Likewise.
+
+2015-01-12 Alan Modra <amodra@gmail.com>
+
+ * read.c (s_altmacro, s_reloc): Make definition static.
+
+2015-01-10 Andrew Burgess <andrew.burgess@embecosm.com>
+
+ * config/tc-avr.c (md_apply_fix): Update the contents of VALP for
+ diff fixups.
+
+2015-01-09 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
+
+ * config/tc-arm.c (arm_cpus): Add support for APM X-Gene 1 and
+ X-Gene 2.
+ * doc/c-arm.texi (ARM Options): Mention xgene1 and xgene2.
+
+2015-01-07 Jan Beulich <jbeulich@suse.com>
+
+ * config/tc-arm.c (struct arm_option_extension_value_table):
+ Split field "value" into fields "merge_value" and "clear_value".
+ (arm_extensions): Adjust initializer accordingly.
+
+2015-01-01 Alan Modra <amodra@gmail.com>
+
+ * as.c (parse_args): Just print current year.
+
+2015-01-01 Alan Modra <amodra@gmail.com>
+
+ Update year range in copyright notice of all files.
+
+For older changes see ChangeLog-2014
+
+Copyright (C) 2015 Free Software Foundation, Inc.
+
+Copying and distribution of this file, with or without modification,
+are permitted in any medium without royalty provided the copyright
+notice and this notice are preserved.
+
+Local Variables:
+mode: change-log
+left-margin: 8
+fill-column: 74
+version-control: never
+End: