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+; Copyright 2011 Free Software Foundation, Inc.
+;
+; Contributed by Red Hat Inc;
+;
+; This file is part of the GNU Binutils.
+;
+; This program is free software; you can redistribute it and/or modify
+; it under the terms of the GNU General Public License as published by
+; the Free Software Foundation; either version 3 of the License, or
+; (at your option) any later version.
+;
+; This program is distributed in the hope that it will be useful,
+; but WITHOUT ANY WARRANTY; without even the implied warranty of
+; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+; GNU General Public License for more details.
+;
+; You should have received a copy of the GNU General Public License
+; along with this program; if not, write to the Free Software
+; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
+; MA 02110-1301, USA.
+
+;; This coprocessor definition is being used to verify vliw mode behaviour.
+;; This is a mock-up done by Red Hat and is in no way supposed to represent
+;; a real coprocessor. The hardware is defined in mep-core.cpu.
+
+; Coprocessor registers
+(define-pmacro rh-isa-1 () (ISA ext_cop1_16,ext_cop1_32,ext_cop1_48,ext_cop1_64))
+
+(define-hardware
+ (name h-cr64-rh-1)
+ (comment "64-bit coprocessor registers for rh coprocessor for core 1")
+ (attrs VIRTUAL rh-isa-1)
+ (type register DI (32))
+ (set (index newval) (c-call VOID "h_cr64_set" index newval))
+ (get (index) (c-call DI "h_cr64_get" index))
+ (indices keyword "$c" (.map -reg-pair (.iota 32)))
+)
+
+(define-hardware
+ (name h-cr-rh-1)
+ (comment "32-bit coprocessor registers for rh coprocessor for core 1")
+ (attrs VIRTUAL rh-isa-1)
+ (type register SI (32))
+ (set (index newval) (c-call VOID "h_cr64_set" index (ext DI newval)))
+ (get (index) (trunc SI (c-call DI "h_cr64_get" index)))
+ (indices keyword "$c" (.map -reg-pair (.iota 32)))
+)
+
+(define-hardware
+ (name h-ccr-rh-1)
+ (comment "Coprocessor control registers for rh coprocessor for core 1")
+ (attrs VIRTUAL rh-isa-1)
+ (type register SI (64))
+ (set (index newval) (c-call VOID "h_ccr_set" index newval))
+ (get (index) (c-call DI "h_ccr_get" index))
+ (indices keyword "" (.map -ccr-reg-pair (.iota 64)))
+)
+
+; ifields For 16-bit insns
+(dnf f-cphigh4 "High 4 bits" ((ISA ext_cop1_16,ext_cop1_32,ext_cop1_48,ext_cop1_64)) 0 4)
+(dnf f-cpcrn "Copro Reg" ((ISA ext_cop1_16,ext_cop1_32,ext_cop1_48,ext_cop1_64)) 4 5)
+(dnf f-cpcrm "Copro Reg" ((ISA ext_cop1_16,ext_cop1_32,ext_cop1_48,ext_cop1_64)) 11 5)
+(dnf f-uu2 "UU for 16-bit insns" ((ISA ext_cop1_16)) 9 2)
+(dnf f-uu3 "UU for 16-bit insns" ((ISA ext_cop1_16)) 9 3)
+(dnf f-cprm "Core GPR" ((ISA ext_cop1_16)) 12 4)
+
+; ifields For 32-bit insns (some of the above are used too)
+; Notes:
+;
+; f-alone: A value of 0111 means that the insn can run alone in
+; one of the vliw modes.
+;
+; f-seg32: Together f-seg32 and f-seg32-a allow 64 different 32-bit
+; f-seg32-a: insns to be defined.
+(dnf f-seg32 "Enumerate 32 bit-insns" ((ISA ext_cop1_32)) 9 3)
+(dnf f-alone "Run-alone indicator" ((ISA ext_cop1_16,ext_cop1_32,ext_cop1_64)) 12 4)
+(dnf f-seg32-a "Enumerate 32 bit-insns" ((ISA ext_cop1_32)) 21 3)
+(dnf f-code8 "8 bit unsigned immediate" ((ISA ext_cop1_32)) 24 8)
+(dnf f-cpcrm-32 "Corpocessor Reg" ((ISA ext_cop1_32)) 16 5)
+
+; ifields for 48-bit insns
+; Note: Part of f-uu12 can be broken off later to enumerate
+; any 48-bit insns that may be added.
+(dnf f-uu12 "Unusued 12 bits" ((ISA ext_cop1_48)) 4 12)
+(dnf f-code16a "Unsigned immediate" ((ISA ext_cop1_48)) 16 16)
+(dnf f-code16b "Unsigned immediate" ((ISA ext_cop1_48,ext_cop1_64)) 32 16)
+
+; ifields for 64-bit insns
+(dnf f-uu8 "Unsused 8 bits" ((ISA ext_cop1_64)) 4 8)
+(dnf f-uu8a "Unused 13 bits" ((ISA ext_cop1_64)) 16 8)
+(dnf f-seg64 "Enumerate 64-bit insns" ((ISA ext_cop1_64)) 24 8)
+(dnf f-code16c "Unsigned immediate" ((ISA ext_cop1_64)) 48 16)
+(dnf f-cpcrn-64 "Coprocessor Register" ((ISA ext_cop1_64)) 32 5)
+(dnf f-cpcrm-64 "Coprocessor Register" ((ISA ext_cop1_64)) 37 4)
+(dnf f-code23 "23 Bit Unisgned Immediate" ((ISA ext_cop1_64)) 41 23)
+(dnf f-cpccrn-64 "Coprocessor Register" ((ISA ext_cop1_64)) 32 4)
+(dnf f-cpccrm-64 "Core GPR" ((ISA ext_cop1_64)) 36 4)
+(dnf f-code24 "24 Bit Unisgned Immediate" ((ISA ext_cop1_64)) 40 24)
+
+
+; Operands for 16-bit insns
+(dnop cpcrn "cpcrn" ((ISA ext_cop1_16,ext_cop1_32)) h-cr64-rh-1 f-cpcrn)
+(dnop cpcrm "cpcrm" ((ISA ext_cop1_16,ext_cop1_32)) h-cr64-rh-1 f-cpcrm)
+(dnop cprm "cprm" ((ISA ext_cop1_16)) h-gpr f-cprm)
+
+; Additional operands for 32-bit insns
+(dnop code8 "imm8" ((ISA ext_cop1_32)) h-uint f-code8)
+
+; Operands for 48-bit insns
+(dnop code16a "code16a" ((ISA ext_cop1_48)) h-uint f-code16a)
+(dnop code16b "code16b" ((ISA ext_cop1_48,ext_cop1_64)) h-uint f-code16b)
+
+; Additional operands for 64-bit insns
+(dnop code16c "code16c" ((ISA ext_cop1_64)) h-uint f-code16c)
+(dnop cpcrn64 "cpcrn64" ((ISA ext_cop1_64)) h-cr64-rh-1 f-cpcrn-64)
+(dnop cpcrm64 "crm64" ((ISA ext_cop1_64)) h-gpr f-cpcrm-64)
+(dnop cpccrn64 "cpccrn64" ((ISA ext_cop1_64)) h-ccr-rh-1 f-cpccrn-64)
+(dnop cpccrm64 "cpccrm64" ((ISA ext_cop1_64)) h-gpr f-cpccrm-64)
+(dnop cpcode23 "cpcode23" ((ISA ext_cop1_64)) h-uint f-code23)
+(dnop cpcode24 "cpcode24" ((ISA ext_cop1_64)) h-uint f-code24)
+
+
+
+; 16- and 32-bit nops can be defined as normal instructions without
+; any problems. nops take no operands, so nops longer than 32
+; bits cannot be defined as normal insns since that would result in
+; decodable bits beyond cgen's 32-bit boundary. As a result, we
+; have to use macros and other real insns to create 48- and 64-bit nops.
+;
+; In addition, since the names of the nops that will be created as part
+; of future insn sets are not known at this time, the assembler needs a
+; fixed set of nop names that it can use for automatic nop insertion.
+; The idea is that no matter what those insns are called, we don't want
+; to have to change the C code in the assemblers vliw grouping validation
+; and nop insertion routines. We therefore have to create macros for
+; all nops to map the macro names which are known to the assembler to the
+; names of the real nop insns.
+;
+; These emitted insns in these macros will need to be modified when
+; new nops are defined in new coprocessor insn sets.
+
+; A real 16-bit nop insn exists
+(dnmi cpnop16 "cpnop16"
+ ((ISA ext_cop1_16))
+ "cpnop16"
+ (emit cp16nop)
+)
+
+; A real 32-bit nop insn exists
+(dnmi cpnop32 "cpnop32"
+ ((ISA ext_cop1_32))
+ "cpnop32"
+ (emit cp32nop)
+)
+
+; There is no 48-bit nop insn so we use a real "dummy" insn to enable the nop.
+(dnmi cpnop48 "cpnop48"
+ ((ISA ext_cop1_48))
+ "cpnop48"
+ (emit cpf1nop (code16a 0) (code16b 0))
+)
+
+; There is no 64-bit nop insn so we use a real "dummy" insn to enable the nop.
+(dnmi cpnop64 "cpnop64"
+ ((ISA ext_cop1_64))
+ "cpnop64"
+ (emit cpf3nop (code16b 0) (code16c 0))
+)
+
+
+(define-pmacro (dncp116i xname xcomment xattrs xsyntax xformat xsemantics xtiming) (dni-isa xname xcomment xattrs xsyntax xformat xsemantics xtiming ext_cop1_16))
+(define-pmacro (dncp132i xname xcomment xattrs xsyntax xformat xsemantics xtiming) (dni-isa xname xcomment xattrs xsyntax xformat xsemantics xtiming ext_cop1_32))
+(define-pmacro (dncp148i xname xcomment xattrs xsyntax xformat xsemantics xtiming) (dni-isa xname xcomment xattrs xsyntax xformat xsemantics xtiming ext_cop1_48))
+(define-pmacro (dncp164i xname xcomment xattrs xsyntax xformat xsemantics xtiming) (dni-isa xname xcomment xattrs xsyntax xformat xsemantics xtiming ext_cop1_64))
+
+; 16-Bit Insns
+(dncp116i movcp16 "16-bit coprocessor move insn"
+ (VLIW64_NO_MATCHING_NOP)
+ "movcp16 $cpcrn,$cpcrm"
+ (+ (f-cphigh4 1) cpcrn (f-uu2 0) cpcrm)
+ (set cpcrn cpcrm)
+ ()
+)
+
+(dncp116i movcp16a "16-bit coprocessor move insn"
+ (VLIW64_NO_MATCHING_NOP)
+ "movcp16a $cpcrn,$cprm"
+ (+ (f-cphigh4 2) cpcrn (f-uu3 0) cprm)
+ (set cpcrn (zext DI cprm))
+ ()
+)
+
+(dncp116i movcp16b "16-bit coprocessor move insn"
+ (VLIW64_NO_MATCHING_NOP)
+ "movcp16b $cprm,$cpcrn"
+ (+ (f-cphigh4 3) cpcrn (f-uu3 0) cprm)
+ (set cprm (subword SI cpcrn 1))
+ ()
+)
+
+(dncp116i cp16nop "16-bit coprocessor nop"
+ (VLIW64_NO_MATCHING_NOP)
+ "cp16nop"
+ (+ (f-cphigh4 0) (f-cpcrn 0) (f-uu2 0) (f-cpcrm 0))
+ (unimp "cp16nop")
+ ()
+)
+
+; 32-Bit Insns
+(dncp132i cp32nop "32-bit coprocessor nop"
+ (VLIW64_NO_MATCHING_NOP)
+ "cp32nop"
+ (+ (f-cphigh4 #xf ) (f-cpcrn 0) (f-seg32 0) (f-alone #x7)
+ (f-cpcrm-32 0) (f-seg32-a 0) (f-code8 0))
+ (unimp "cpnop32")
+ ()
+)
+
+(dncp132i cpf2 "General 32-bit insn for compatibility with toshiba's tests "
+ (VLIW64_NO_MATCHING_NOP)
+ "cpf2 $code8"
+ (+ (f-cphigh4 #xf ) (f-cpcrn 0) (f-seg32 0) (f-alone #x7)
+ (f-cpcrm-32 0) (f-seg32-a 1) code8)
+ (unimp "cpf2")
+ ()
+)
+
+; 48-Bit Insns
+(dncp148i cpf1 "48-bit coprocessor helper insn"
+ ()
+ "cpf1 $code16a,$code16b"
+ (+ (f-cphigh4 4) (f-uu12 0) code16a code16b)
+ (sequence ((HI result))
+ (if (eq code16a 0)
+ (set pc (c-call USI "cop_exception" pc))
+ ; Set branch condition flags to value of code16a[0:3]
+ ; Branch condition flags do not exist yet.
+ (nop)
+ )
+ )
+ ()
+)
+
+(dncp148i cpf1nop "48-bit coprocessor nop insn"
+ ()
+ "cpf1nop $code16a,$code16b"
+ (+ (f-cphigh4 5) (f-uu12 0) code16a code16b)
+ (sequence ((HI result))
+ (set result (add code16a code16b))
+ )
+ ()
+)
+
+; 64-Bit Insns
+(dncp164i cpf3 "64-bit coprocessor helper insn"
+ ()
+ "cpf3 $code16b,$code16c"
+ (+ (f-cphigh4 #xf) (f-uu8 0) (f-alone 7) (f-uu8a 0)
+ (f-seg64 0) code16b code16c)
+ (sequence ((HI result))
+ (set result (add code16b code16c))
+ )
+ ()
+)
+
+(dncp164i cpf3nop "64-bit coprocessor helper insn"
+ ()
+ "cpf3nop $code16b,$code16c"
+ (+ (f-cphigh4 #xf) (f-uu8 0) (f-alone 7) (f-uu8a 0)
+ (f-seg64 7) code16b code16c)
+ (sequence ((HI result))
+ (set result (add code16b code16c))
+ )
+ ()
+)
+
+(dncp164i cmov64a "64-bit cmov"
+ ()
+ "cmov64a $cpcrn64,$cpcrm64,$cpcode23"
+ (+ (f-cphigh4 #xf ) (f-uu8 0) (f-alone 7) (f-uu8a 0)
+ (f-seg64 1) cpcrn64 cpcrm64 cpcode23)
+ (sequence ((SI dummy))
+ (set dummy cpcode23)
+ (set cpcrn64 (zext DI cpcrm64)))
+ ()
+)
+
+(dncp164i cmov64b "64-bit cmov"
+ ()
+ "cmov64b $cpcrm64,$cpcrn64,$cpcode23"
+ (+ (f-cphigh4 #xf ) (f-uu8 0) (f-alone 7) (f-uu8a 0)
+ (f-seg64 2) cpcrn64 cpcrm64 cpcode23)
+ (sequence ((SI dummy))
+ (set dummy cpcode23)
+ (set cpcrm64 (subword SI cpcrn64 1)))
+ ()
+)
+
+(dncp164i cmovh64a "64-bit cmovh"
+ ()
+ "cmovh64a $cpcrn64,$cpcrm64,$cpcode23"
+ (+ (f-cphigh4 #xf ) (f-uu8 0) (f-alone 7) (f-uu8a 0)
+ (f-seg64 3) cpcrn64 cpcrm64 cpcode23)
+ (sequence ((SI dummy))
+ (set dummy cpcode23)
+ (set cpcrn64 (or (sll (zext DI cpcrm64) 32) (zext DI (subword SI cpcrn64 1)))))
+ ()
+)
+
+(dncp164i cmovh64b "64-bit cmovh"
+ ()
+ "cmovh64b $cpcrm64,$cpcrn64,$cpcode23"
+ (+ (f-cphigh4 #xf ) (f-uu8 0) (f-alone 7) (f-uu8a 0)
+ (f-seg64 4) cpcrn64 cpcrm64 cpcode23)
+ (sequence ((SI dummy))
+ (set dummy cpcode23)
+ (set cpcrm64 (subword SI cpcrn64 0)))
+ ()
+)
+
+(dncp164i cmovc64a "64-bit cmovc"
+ ()
+ "cmovc64a $cpccrn64,$cpccrm64,$cpcode24"
+ (+ (f-cphigh4 #xf ) (f-uu8 0) (f-alone 7) (f-uu8a 0)
+ (f-seg64 5) cpccrn64 cpccrm64 cpcode24)
+ (sequence ((SI dummy))
+ (set dummy cpcode24)
+ (set cpccrn64 cpccrm64))
+ ()
+)
+
+(dncp164i cmovc64b "64-bit cmovc"
+ ()
+ "cmovc64b $cpccrm64,$cpccrn64,$cpcode24"
+ (+ (f-cphigh4 #xf ) (f-uu8 0) (f-alone 7) (f-uu8a 0)
+ (f-seg64 6) cpccrn64 cpccrm64 cpcode24)
+ (sequence ((SI dummy))
+ (set dummy cpcode24)
+ (set cpccrm64 cpccrn64))
+ ()
+)
+