diff options
314 files changed, 5187 insertions, 364 deletions
diff --git a/bfd/ChangeLog b/bfd/ChangeLog index 9444812..abcd4ab 100644 --- a/bfd/ChangeLog +++ b/bfd/ChangeLog @@ -1,3 +1,35 @@ +2014-07-29 Matthew Fortune <matthew.fortune@imgtec.com> + + * elfxx-mips.c (ABI_O32_P, MIPS_ELF_ABIFLAGS_SECTION_NAME_P): New macro. + (mips_elf_obj_tdata): Add abiflags and abiflags_valid fields. + (bfd_mips_elf_swap_abiflags_v0_in): New function. + (bfd_mips_elf_swap_abiflags_v0_out): Likewise. + (_bfd_mips_elf_section_from_shdr): Handle SHT_MIPS_ABIFLAGS. + (_bfd_mips_elf_fake_sections): Likewise. + (_bfd_mips_elf_always_size_sections): Handle .MIPS.abiflags. + (_bfd_mips_elf_additional_program_headers): Account for new + PT_MIPS_ABIFLAGS program header. + (_bfd_mips_elf_modify_segment_map): Create PT_MIPS_ABIFLAGS segment and + associate with .MIPS.abiflags. + (_bfd_mips_elf_gc_mark_extra_sections): New function. + (bfd_mips_isa_ext, update_mips_abiflags_isa): New static function. + (infer_mips_abiflags): Likewise. + (_bfd_mips_elf_final_link): Handle .MIPS.abiflags. + (mips_32bit_flags_p): Moved higher. + (mips_elf_merge_obj_attributes, _bfd_mips_fp_abi_string): Error + checking for FP ABIs. + (_bfd_mips_elf_merge_private_bfd_data): Restructure and add abiflags + checks. Check EF_MIPS_FP64 flag consistency. + (print_mips_ases, print_mips_isa_ext): New static function. + (print_mips_fp_abi_value, get_mips_reg_size): Likewise. + (_bfd_mips_elf_print_private_bfd_data): Display abiflags data. + (_bfd_mips_post_process_headers): Set EI_ABIVERSION = 3 for + Val_GNU_MIPS_ABI_FP_64 or Val_GNU_MIPS_ABI_FP_64A. + * elfxx-mips.h (_bfd_mips_elf_gc_mark_extra_sections): New prototype. + * elf32-mips.c (elf_backend_gc_mark_extra_sections): Implement. + * elfn32-mips.c (elf_backend_gc_mark_extra_sections): Implement. + * elf64-mips.c (elf_backend_gc_mark_extra_sections): Implement. + 2014-07-28 Alan Modra <amodra@gmail.com> PR 13227 diff --git a/bfd/elf32-mips.c b/bfd/elf32-mips.c index 1de302f..af405bc 100644 --- a/bfd/elf32-mips.c +++ b/bfd/elf32-mips.c @@ -2315,6 +2315,8 @@ static const struct ecoff_debug_swap mips_elf32_ecoff_debug_swap = { #define elf_backend_collect TRUE #define elf_backend_type_change_ok TRUE #define elf_backend_can_gc_sections TRUE +#define elf_backend_gc_mark_extra_sections \ + _bfd_mips_elf_gc_mark_extra_sections #define elf_info_to_howto mips_info_to_howto_rela #define elf_info_to_howto_rel mips_info_to_howto_rel #define elf_backend_sym_is_global mips_elf_sym_is_global diff --git a/bfd/elf64-mips.c b/bfd/elf64-mips.c index 9d50a79..8662d66 100644 --- a/bfd/elf64-mips.c +++ b/bfd/elf64-mips.c @@ -4185,6 +4185,8 @@ const struct elf_size_info mips_elf64_size_info = #define elf_backend_collect TRUE #define elf_backend_type_change_ok TRUE #define elf_backend_can_gc_sections TRUE +#define elf_backend_gc_mark_extra_sections \ + _bfd_mips_elf_gc_mark_extra_sections #define elf_info_to_howto mips_elf64_info_to_howto_rela #define elf_info_to_howto_rel mips_elf64_info_to_howto_rel #define elf_backend_object_p mips_elf64_object_p diff --git a/bfd/elfn32-mips.c b/bfd/elfn32-mips.c index c37ff9d..1286cc1 100644 --- a/bfd/elfn32-mips.c +++ b/bfd/elfn32-mips.c @@ -3410,6 +3410,8 @@ static const struct ecoff_debug_swap mips_elf32_ecoff_debug_swap = { #define elf_backend_collect TRUE #define elf_backend_type_change_ok TRUE #define elf_backend_can_gc_sections TRUE +#define elf_backend_gc_mark_extra_sections \ + _bfd_mips_elf_gc_mark_extra_sections #define elf_info_to_howto mips_info_to_howto_rela #define elf_info_to_howto_rel mips_info_to_howto_rel #define elf_backend_sym_is_global mips_elf_sym_is_global diff --git a/bfd/elfxx-mips.c b/bfd/elfxx-mips.c index dddf83e..a72ccc3 100644 --- a/bfd/elfxx-mips.c +++ b/bfd/elfxx-mips.c @@ -547,6 +547,10 @@ struct mips_elf_obj_tdata /* Input BFD providing Tag_GNU_MIPS_ABI_MSA attribute for output. */ bfd *abi_msa_bfd; + /* The abiflags for this object. */ + Elf_Internal_ABIFlags_v0 abiflags; + bfd_boolean abiflags_valid; + /* The GOT requirements of input bfds. */ struct mips_got_info *got; @@ -776,6 +780,10 @@ static bfd *reldyn_sorting_bfd; #define PIC_OBJECT_P(abfd) \ ((elf_elfheader (abfd)->e_flags & EF_MIPS_PIC) != 0) +/* Nonzero if ABFD is using the O32 ABI. */ +#define ABI_O32_P(abfd) \ + ((elf_elfheader (abfd)->e_flags & EF_MIPS_ABI) == E_MIPS_ABI_O32) + /* Nonzero if ABFD is using the N32 ABI. */ #define ABI_N32_P(abfd) \ ((elf_elfheader (abfd)->e_flags & EF_MIPS_ABI2) != 0) @@ -808,6 +816,10 @@ static bfd *reldyn_sorting_bfd; #define MIPS_ELF_OPTIONS_SECTION_NAME_P(NAME) \ (strcmp (NAME, ".MIPS.options") == 0 || strcmp (NAME, ".options") == 0) +/* True if NAME is the recognized name of any SHT_MIPS_ABIFLAGS section. */ +#define MIPS_ELF_ABIFLAGS_SECTION_NAME_P(NAME) \ + (strcmp (NAME, ".MIPS.abiflags") == 0) + /* Whether the section is readonly. */ #define MIPS_ELF_READONLY_SECTION(sec) \ ((sec->flags & (SEC_ALLOC | SEC_LOAD | SEC_READONLY)) \ @@ -2664,6 +2676,46 @@ bfd_mips_elf_swap_options_out (bfd *abfd, const Elf_Internal_Options *in, H_PUT_16 (abfd, in->section, ex->section); H_PUT_32 (abfd, in->info, ex->info); } + +/* Swap in an abiflags structure. */ + +void +bfd_mips_elf_swap_abiflags_v0_in (bfd *abfd, + const Elf_External_ABIFlags_v0 *ex, + Elf_Internal_ABIFlags_v0 *in) +{ + in->version = H_GET_16 (abfd, ex->version); + in->isa_level = H_GET_8 (abfd, ex->isa_level); + in->isa_rev = H_GET_8 (abfd, ex->isa_rev); + in->gpr_size = H_GET_8 (abfd, ex->gpr_size); + in->cpr1_size = H_GET_8 (abfd, ex->cpr1_size); + in->cpr2_size = H_GET_8 (abfd, ex->cpr2_size); + in->fp_abi = H_GET_8 (abfd, ex->fp_abi); + in->isa_ext = H_GET_32 (abfd, ex->isa_ext); + in->ases = H_GET_32 (abfd, ex->ases); + in->flags1 = H_GET_32 (abfd, ex->flags1); + in->flags2 = H_GET_32 (abfd, ex->flags2); +} + +/* Swap out an abiflags structure. */ + +void +bfd_mips_elf_swap_abiflags_v0_out (bfd *abfd, + const Elf_Internal_ABIFlags_v0 *in, + Elf_External_ABIFlags_v0 *ex) +{ + H_PUT_16 (abfd, in->version, ex->version); + H_PUT_8 (abfd, in->isa_level, ex->isa_level); + H_PUT_8 (abfd, in->isa_rev, ex->isa_rev); + H_PUT_8 (abfd, in->gpr_size, ex->gpr_size); + H_PUT_8 (abfd, in->cpr1_size, ex->cpr1_size); + H_PUT_8 (abfd, in->cpr2_size, ex->cpr2_size); + H_PUT_8 (abfd, in->fp_abi, ex->fp_abi); + H_PUT_32 (abfd, in->isa_ext, ex->isa_ext); + H_PUT_32 (abfd, in->ases, ex->ases); + H_PUT_32 (abfd, in->flags1, ex->flags1); + H_PUT_32 (abfd, in->flags2, ex->flags2); +} /* This function is called via qsort() to sort the dynamic relocation entries by increasing r_symndx value. */ @@ -6910,6 +6962,11 @@ _bfd_mips_elf_section_from_shdr (bfd *abfd, if (!MIPS_ELF_OPTIONS_SECTION_NAME_P (name)) return FALSE; break; + case SHT_MIPS_ABIFLAGS: + if (!MIPS_ELF_ABIFLAGS_SECTION_NAME_P (name)) + return FALSE; + flags = (SEC_LINK_ONCE | SEC_LINK_DUPLICATES_SAME_SIZE); + break; case SHT_MIPS_DWARF: if (! CONST_STRNEQ (name, ".debug_") && ! CONST_STRNEQ (name, ".zdebug_")) @@ -6940,6 +6997,20 @@ _bfd_mips_elf_section_from_shdr (bfd *abfd, return FALSE; } + if (hdr->sh_type == SHT_MIPS_ABIFLAGS) + { + Elf_External_ABIFlags_v0 ext; + + if (! bfd_get_section_contents (abfd, hdr->bfd_section, + &ext, 0, sizeof ext)) + return FALSE; + bfd_mips_elf_swap_abiflags_v0_in (abfd, &ext, + &mips_elf_tdata (abfd)->abiflags); + if (mips_elf_tdata (abfd)->abiflags.version != 0) + return FALSE; + mips_elf_tdata (abfd)->abiflags_valid = TRUE; + } + /* FIXME: We should record sh_info for a .gptab section. */ /* For a .reginfo section, set the gp value in the tdata information @@ -7106,6 +7177,11 @@ _bfd_mips_elf_fake_sections (bfd *abfd, Elf_Internal_Shdr *hdr, asection *sec) hdr->sh_entsize = 1; hdr->sh_flags |= SHF_MIPS_NOSTRIP; } + else if (CONST_STRNEQ (name, ".MIPS.abiflags")) + { + hdr->sh_type = SHT_MIPS_ABIFLAGS; + hdr->sh_entsize = sizeof (Elf_External_ABIFlags_v0); + } else if (CONST_STRNEQ (name, ".debug_") || CONST_STRNEQ (name, ".zdebug_")) { @@ -9025,7 +9101,7 @@ bfd_boolean _bfd_mips_elf_always_size_sections (bfd *output_bfd, struct bfd_link_info *info) { - asection *ri; + asection *sect; struct mips_elf_link_hash_table *htab; struct mips_htab_traverse_info hti; @@ -9033,9 +9109,14 @@ _bfd_mips_elf_always_size_sections (bfd *output_bfd, BFD_ASSERT (htab != NULL); /* The .reginfo section has a fixed size. */ - ri = bfd_get_section_by_name (output_bfd, ".reginfo"); - if (ri != NULL) - bfd_set_section_size (output_bfd, ri, sizeof (Elf32_External_RegInfo)); + sect = bfd_get_section_by_name (output_bfd, ".reginfo"); + if (sect != NULL) + bfd_set_section_size (output_bfd, sect, sizeof (Elf32_External_RegInfo)); + + /* The .MIPS.abiflags section has a fixed size. */ + sect = bfd_get_section_by_name (output_bfd, ".MIPS.abiflags"); + if (sect != NULL) + bfd_set_section_size (output_bfd, sect, sizeof (Elf_External_ABIFlags_v0)); hti.info = info; hti.output_bfd = output_bfd; @@ -11782,6 +11863,10 @@ _bfd_mips_elf_additional_program_headers (bfd *abfd, if (s && (s->flags & SEC_LOAD)) ++ret; + /* See if we need a PT_MIPS_ABIFLAGS segment. */ + if (bfd_get_section_by_name (abfd, ".MIPS.abiflags")) + ++ret; + /* See if we need a PT_MIPS_OPTIONS segment. */ if (IRIX_COMPAT (abfd) == ict_irix6 && bfd_get_section_by_name (abfd, @@ -11844,6 +11929,37 @@ _bfd_mips_elf_modify_segment_map (bfd *abfd, } } + /* If there is a .MIPS.abiflags section, we need a PT_MIPS_ABIFLAGS + segment. */ + s = bfd_get_section_by_name (abfd, ".MIPS.abiflags"); + if (s != NULL && (s->flags & SEC_LOAD) != 0) + { + for (m = elf_seg_map (abfd); m != NULL; m = m->next) + if (m->p_type == PT_MIPS_ABIFLAGS) + break; + if (m == NULL) + { + amt = sizeof *m; + m = bfd_zalloc (abfd, amt); + if (m == NULL) + return FALSE; + + m->p_type = PT_MIPS_ABIFLAGS; + m->count = 1; + m->sections[0] = s; + + /* We want to put it after the PHDR and INTERP segments. */ + pm = &elf_seg_map (abfd); + while (*pm != NULL + && ((*pm)->p_type == PT_PHDR + || (*pm)->p_type == PT_INTERP)) + pm = &(*pm)->next; + + m->next = *pm; + *pm = m; + } + } + /* For IRIX 6, we don't have .mdebug sections, nor does anything but .dynamic end up in PT_DYNAMIC. However, we do have to insert a PT_MIPS_OPTIONS segment immediately following the program header @@ -12127,6 +12243,36 @@ _bfd_mips_elf_gc_sweep_hook (bfd *abfd ATTRIBUTE_UNUSED, return TRUE; } + +/* Prevent .MIPS.abiflags from being discarded with --gc-sections. */ + +bfd_boolean +_bfd_mips_elf_gc_mark_extra_sections (struct bfd_link_info *info, + elf_gc_mark_hook_fn gc_mark_hook) +{ + bfd *sub; + + _bfd_elf_gc_mark_extra_sections (info, gc_mark_hook); + + for (sub = info->input_bfds; sub != NULL; sub = sub->link.next) + { + asection *o; + + if (! is_mips_elf (sub)) + continue; + + for (o = sub->sections; o != NULL; o = o->next) + if (!o->gc_mark + && MIPS_ELF_ABIFLAGS_SECTION_NAME_P + (bfd_get_section_name (sub, o))) + { + if (!_bfd_elf_gc_mark (info, o, gc_mark_hook)) + return FALSE; + } + } + + return TRUE; +} /* Copy data from a MIPS ELF indirect symbol to its direct symbol, hiding the old indirect symbol. Process additional relocation @@ -13577,6 +13723,170 @@ _bfd_mips_elf_insn32 (struct bfd_link_info *info, bfd_boolean on) mips_elf_hash_table (info)->insn32 = on; } +/* Return the .MIPS.abiflags value representing each ISA Extension. */ + +unsigned int +bfd_mips_isa_ext (bfd *abfd) +{ + switch (bfd_get_mach (abfd)) + { + case bfd_mach_mips3900: + return AFL_EXT_3900; + case bfd_mach_mips4010: + return AFL_EXT_4010; + case bfd_mach_mips4100: + return AFL_EXT_4100; + case bfd_mach_mips4111: + return AFL_EXT_4111; + case bfd_mach_mips4120: + return AFL_EXT_4120; + case bfd_mach_mips4650: + return AFL_EXT_4650; + case bfd_mach_mips5400: + return AFL_EXT_5400; + case bfd_mach_mips5500: + return AFL_EXT_5500; + case bfd_mach_mips5900: + return AFL_EXT_5900; + case bfd_mach_mips10000: + return AFL_EXT_10000; + case bfd_mach_mips_loongson_2e: + return AFL_EXT_LOONGSON_2E; + case bfd_mach_mips_loongson_2f: + return AFL_EXT_LOONGSON_2F; + case bfd_mach_mips_loongson_3a: + return AFL_EXT_LOONGSON_3A; + case bfd_mach_mips_sb1: + return AFL_EXT_SB1; + case bfd_mach_mips_octeon: + return AFL_EXT_OCTEON; + case bfd_mach_mips_octeonp: + return AFL_EXT_OCTEONP; + case bfd_mach_mips_octeon2: + return AFL_EXT_OCTEON2; + case bfd_mach_mips_xlr: + return AFL_EXT_XLR; + } + return 0; +} + +/* Update the isa_level, isa_rev, isa_ext fields of abiflags. */ + +static void +update_mips_abiflags_isa (bfd *abfd, Elf_Internal_ABIFlags_v0 *abiflags) +{ + switch (elf_elfheader (abfd)->e_flags & EF_MIPS_ARCH) + { + case E_MIPS_ARCH_1: + abiflags->isa_level = 1; + abiflags->isa_rev = 0; + break; + case E_MIPS_ARCH_2: + abiflags->isa_level = 2; + abiflags->isa_rev = 0; + break; + case E_MIPS_ARCH_3: + abiflags->isa_level = 3; + abiflags->isa_rev = 0; + break; + case E_MIPS_ARCH_4: + abiflags->isa_level = 4; + abiflags->isa_rev = 0; + break; + case E_MIPS_ARCH_5: + abiflags->isa_level = 5; + abiflags->isa_rev = 0; + break; + case E_MIPS_ARCH_32: + abiflags->isa_level = 32; + abiflags->isa_rev = 1; + break; + case E_MIPS_ARCH_32R2: + abiflags->isa_level = 32; + /* Handle MIPS32r3 and MIPS32r5 which do not have a header flag. */ + if (abiflags->isa_rev < 2) + abiflags->isa_rev = 2; + break; + case E_MIPS_ARCH_64: + abiflags->isa_level = 64; + abiflags->isa_rev = 1; + break; + case E_MIPS_ARCH_64R2: + /* Handle MIPS64r3 and MIPS64r5 which do not have a header flag. */ + abiflags->isa_level = 64; + if (abiflags->isa_rev < 2) + abiflags->isa_rev = 2; + break; + default: + (*_bfd_error_handler) + (_("%B: Unknown architecture %s"), + abfd, bfd_printable_name (abfd)); + } + + abiflags->isa_ext = bfd_mips_isa_ext (abfd); +} + +/* Return true if the given ELF header flags describe a 32-bit binary. */ + +static bfd_boolean +mips_32bit_flags_p (flagword flags) +{ + return ((flags & EF_MIPS_32BITMODE) != 0 + || (flags & EF_MIPS_ABI) == E_MIPS_ABI_O32 + || (flags & EF_MIPS_ABI) == E_MIPS_ABI_EABI32 + || (flags & EF_MIPS_ARCH) == E_MIPS_ARCH_1 + || (flags & EF_MIPS_ARCH) == E_MIPS_ARCH_2 + || (flags & EF_MIPS_ARCH) == E_MIPS_ARCH_32 + || (flags & EF_MIPS_ARCH) == E_MIPS_ARCH_32R2); +} + +/* Infer the content of the ABI flags based on the elf header. */ + +static void +infer_mips_abiflags (bfd *abfd, Elf_Internal_ABIFlags_v0* abiflags) +{ + obj_attribute *in_attr; + + memset (abiflags, 0, sizeof (Elf_Internal_ABIFlags_v0)); + update_mips_abiflags_isa (abfd, abiflags); + + if (mips_32bit_flags_p (elf_elfheader (abfd)->e_flags)) + abiflags->gpr_size = AFL_REG_32; + else + abiflags->gpr_size = AFL_REG_64; + + abiflags->cpr1_size = AFL_REG_NONE; + + in_attr = elf_known_obj_attributes (abfd)[OBJ_ATTR_GNU]; + abiflags->fp_abi = in_attr[Tag_GNU_MIPS_ABI_FP].i; + + if (abiflags->fp_abi == Val_GNU_MIPS_ABI_FP_SINGLE + || abiflags->fp_abi == Val_GNU_MIPS_ABI_FP_XX + || (abiflags->fp_abi == Val_GNU_MIPS_ABI_FP_DOUBLE + && abiflags->gpr_size == AFL_REG_32)) + abiflags->cpr1_size = AFL_REG_32; + else if (abiflags->fp_abi == Val_GNU_MIPS_ABI_FP_DOUBLE + || abiflags->fp_abi == Val_GNU_MIPS_ABI_FP_64 + || abiflags->fp_abi == Val_GNU_MIPS_ABI_FP_64A) + abiflags->cpr1_size = AFL_REG_64; + + abiflags->cpr2_size = AFL_REG_NONE; + + if (elf_elfheader (abfd)->e_flags & EF_MIPS_ARCH_ASE_MDMX) + abiflags->ases |= AFL_ASE_MDMX; + if (elf_elfheader (abfd)->e_flags & EF_MIPS_ARCH_ASE_M16) + abiflags->ases |= AFL_ASE_MIPS16; + if (elf_elfheader (abfd)->e_flags & EF_MIPS_ARCH_ASE_MICROMIPS) + abiflags->ases |= AFL_ASE_MICROMIPS; + + if (abiflags->fp_abi != Val_GNU_MIPS_ABI_FP_ANY + && abiflags->fp_abi != Val_GNU_MIPS_ABI_FP_SOFT + && abiflags->fp_abi != Val_GNU_MIPS_ABI_FP_64A + && abiflags->isa_level >= 32 + && abiflags->isa_ext != AFL_EXT_LOONGSON_3A) + abiflags->flags1 |= AFL_FLAGS1_ODDSPREG; +} + /* We need to use a special link routine to handle the .reginfo and the .mdebug sections. We need to merge all instances of these sections together, not write them all out sequentially. */ @@ -13587,7 +13897,7 @@ _bfd_mips_elf_final_link (bfd *abfd, struct bfd_link_info *info) asection *o; struct bfd_link_order *p; asection *reginfo_sec, *mdebug_sec, *gptab_data_sec, *gptab_bss_sec; - asection *rtproc_sec; + asection *rtproc_sec, *abiflags_sec; Elf32_RegInfo reginfo; struct ecoff_debug_info debug; struct mips_htab_traverse_info hti; @@ -13669,12 +13979,46 @@ _bfd_mips_elf_final_link (bfd *abfd, struct bfd_link_info *info) /* Go through the sections and collect the .reginfo and .mdebug information. */ + abiflags_sec = NULL; reginfo_sec = NULL; mdebug_sec = NULL; gptab_data_sec = NULL; gptab_bss_sec = NULL; for (o = abfd->sections; o != NULL; o = o->next) { + if (strcmp (o->name, ".MIPS.abiflags") == 0) + { + /* We have found the .MIPS.abiflags section in the output file. + Look through all the link_orders comprising it and remove them. + The data is merged in _bfd_mips_elf_merge_private_bfd_data. */ + for (p = o->map_head.link_order; p != NULL; p = p->next) + { + asection *input_section; + + if (p->type != bfd_indirect_link_order) + { + if (p->type == bfd_data_link_order) + continue; + abort (); + } + + input_section = p->u.indirect.section; + + /* Hack: reset the SEC_HAS_CONTENTS flag so that + elf_link_input_bfd ignores this section. */ + input_section->flags &= ~SEC_HAS_CONTENTS; + } + + /* Size has been set in _bfd_mips_elf_always_size_sections. */ + BFD_ASSERT(o->size == sizeof (Elf_External_ABIFlags_v0)); + + /* Skip this section later on (I don't think this currently + matters, but someday it might). */ + o->map_head.link_order = NULL; + + abiflags_sec = o; + } + if (strcmp (o->name, ".reginfo") == 0) { memset (®info, 0, sizeof reginfo); @@ -14159,6 +14503,24 @@ _bfd_mips_elf_final_link (bfd *abfd, struct bfd_link_info *info) /* Now write out the computed sections. */ + if (abiflags_sec != NULL) + { + Elf_External_ABIFlags_v0 ext; + Elf_Internal_ABIFlags_v0 *abiflags; + + abiflags = &mips_elf_tdata (abfd)->abiflags; + + /* Set up the abiflags if no valid input sections were found. */ + if (!mips_elf_tdata (abfd)->abiflags_valid) + { + infer_mips_abiflags (abfd, abiflags); + mips_elf_tdata (abfd)->abiflags_valid = TRUE; + } + bfd_mips_elf_swap_abiflags_v0_out (abfd, abiflags, &ext); + if (! bfd_set_section_contents (abfd, abiflags_sec, &ext, 0, sizeof ext)) + return FALSE; + } + if (reginfo_sec != NULL) { Elf32_External_RegInfo ext; @@ -14316,21 +14678,6 @@ mips_mach_extends_p (unsigned long base, unsigned long extension) } -/* Return true if the given ELF header flags describe a 32-bit binary. */ - -static bfd_boolean -mips_32bit_flags_p (flagword flags) -{ - return ((flags & EF_MIPS_32BITMODE) != 0 - || (flags & EF_MIPS_ABI) == E_MIPS_ABI_O32 - || (flags & EF_MIPS_ABI) == E_MIPS_ABI_EABI32 - || (flags & EF_MIPS_ARCH) == E_MIPS_ARCH_1 - || (flags & EF_MIPS_ARCH) == E_MIPS_ARCH_2 - || (flags & EF_MIPS_ARCH) == E_MIPS_ARCH_32 - || (flags & EF_MIPS_ARCH) == E_MIPS_ARCH_32R2); -} - - /* Merge object attributes from IBFD into OBFD. Raise an error if there are conflicting attributes. */ static bfd_boolean @@ -14375,6 +14722,28 @@ mips_elf_merge_obj_attributes (bfd *ibfd, bfd *obfd) out_attr[Tag_GNU_MIPS_ABI_FP].type = 1; if (out_fp == Val_GNU_MIPS_ABI_FP_ANY) out_attr[Tag_GNU_MIPS_ABI_FP].i = in_fp; + else if (out_fp == Val_GNU_MIPS_ABI_FP_XX + && (in_fp == Val_GNU_MIPS_ABI_FP_DOUBLE + || in_fp == Val_GNU_MIPS_ABI_FP_64 + || in_fp == Val_GNU_MIPS_ABI_FP_64A)) + { + mips_elf_tdata (obfd)->abi_fp_bfd = ibfd; + out_attr[Tag_GNU_MIPS_ABI_FP].i = in_attr[Tag_GNU_MIPS_ABI_FP].i; + } + else if (in_fp == Val_GNU_MIPS_ABI_FP_XX + && (out_fp == Val_GNU_MIPS_ABI_FP_DOUBLE + || out_fp == Val_GNU_MIPS_ABI_FP_64 + || out_fp == Val_GNU_MIPS_ABI_FP_64A)) + /* Keep the current setting. */; + else if (out_fp == Val_GNU_MIPS_ABI_FP_64A + && in_fp == Val_GNU_MIPS_ABI_FP_64) + { + mips_elf_tdata (obfd)->abi_fp_bfd = ibfd; + out_attr[Tag_GNU_MIPS_ABI_FP].i = in_attr[Tag_GNU_MIPS_ABI_FP].i; + } + else if (in_fp == Val_GNU_MIPS_ABI_FP_64A + && out_fp == Val_GNU_MIPS_ABI_FP_64) + /* Keep the current setting. */; else if (in_fp != Val_GNU_MIPS_ABI_FP_ANY) { const char *out_string, *in_string; @@ -14471,6 +14840,7 @@ _bfd_mips_elf_merge_private_bfd_data (bfd *ibfd, bfd *obfd) bfd_boolean ok; bfd_boolean null_input_bfd = TRUE; asection *sec; + obj_attribute *out_attr; /* Check if we have the same endianness. */ if (! _bfd_generic_verify_endian_match (ibfd, obfd)) @@ -14492,17 +14862,98 @@ _bfd_mips_elf_merge_private_bfd_data (bfd *ibfd, bfd *obfd) return FALSE; } + /* Set up the FP ABI attribute from the abiflags if it is not already + set. */ + if (mips_elf_tdata (ibfd)->abiflags_valid) + { + obj_attribute *in_attr = elf_known_obj_attributes (ibfd)[OBJ_ATTR_GNU]; + if (in_attr[Tag_GNU_MIPS_ABI_FP].i == Val_GNU_MIPS_ABI_FP_ANY) + in_attr[Tag_GNU_MIPS_ABI_FP].i = + mips_elf_tdata (ibfd)->abiflags.fp_abi; + } + if (!mips_elf_merge_obj_attributes (ibfd, obfd)) return FALSE; - new_flags = elf_elfheader (ibfd)->e_flags; - elf_elfheader (obfd)->e_flags |= new_flags & EF_MIPS_NOREORDER; - old_flags = elf_elfheader (obfd)->e_flags; + /* Check to see if the input BFD actually contains any sections. + If not, its flags may not have been initialised either, but it cannot + actually cause any incompatibility. */ + for (sec = ibfd->sections; sec != NULL; sec = sec->next) + { + /* Ignore synthetic sections and empty .text, .data and .bss sections + which are automatically generated by gas. Also ignore fake + (s)common sections, since merely defining a common symbol does + not affect compatibility. */ + if ((sec->flags & SEC_IS_COMMON) == 0 + && strcmp (sec->name, ".reginfo") + && strcmp (sec->name, ".mdebug") + && (sec->size != 0 + || (strcmp (sec->name, ".text") + && strcmp (sec->name, ".data") + && strcmp (sec->name, ".bss")))) + { + null_input_bfd = FALSE; + break; + } + } + if (null_input_bfd) + return TRUE; + + /* Populate abiflags using existing information. */ + if (!mips_elf_tdata (ibfd)->abiflags_valid) + { + infer_mips_abiflags (ibfd, &mips_elf_tdata (ibfd)->abiflags); + mips_elf_tdata (ibfd)->abiflags_valid = TRUE; + } + else + { + Elf_Internal_ABIFlags_v0 abiflags; + Elf_Internal_ABIFlags_v0 in_abiflags; + infer_mips_abiflags (ibfd, &abiflags); + in_abiflags = mips_elf_tdata (ibfd)->abiflags; + + /* It is not possible to infer the correct ISA revision + for R3 or R5 so drop down to R2 for the checks. */ + if (in_abiflags.isa_rev == 3 || in_abiflags.isa_rev == 5) + in_abiflags.isa_rev = 2; + + if (in_abiflags.isa_level != abiflags.isa_level + || in_abiflags.isa_rev != abiflags.isa_rev + || in_abiflags.isa_ext != abiflags.isa_ext) + (*_bfd_error_handler) + (_("%B: warning: Inconsistent ISA between e_flags and " + ".MIPS.abiflags"), ibfd); + if (abiflags.fp_abi != Val_GNU_MIPS_ABI_FP_ANY + && in_abiflags.fp_abi != abiflags.fp_abi) + (*_bfd_error_handler) + (_("%B: warning: Inconsistent FP ABI between e_flags and " + ".MIPS.abiflags"), ibfd); + if ((in_abiflags.ases & abiflags.ases) != abiflags.ases) + (*_bfd_error_handler) + (_("%B: warning: Inconsistent ASEs between e_flags and " + ".MIPS.abiflags"), ibfd); + if (in_abiflags.isa_ext != abiflags.isa_ext) + (*_bfd_error_handler) + (_("%B: warning: Inconsistent ISA extensions between e_flags and " + ".MIPS.abiflags"), ibfd); + if (in_abiflags.flags2 != 0) + (*_bfd_error_handler) + (_("%B: warning: Unexpected flag in the flags2 field of " + ".MIPS.abiflags (0x%lx)"), ibfd, + (unsigned long) in_abiflags.flags2); + } + + if (!mips_elf_tdata (obfd)->abiflags_valid) + { + /* Copy input abiflags if output abiflags are not already valid. */ + mips_elf_tdata (obfd)->abiflags = mips_elf_tdata (ibfd)->abiflags; + mips_elf_tdata (obfd)->abiflags_valid = TRUE; + } if (! elf_flags_init (obfd)) { elf_flags_init (obfd) = TRUE; - elf_elfheader (obfd)->e_flags = new_flags; + elf_elfheader (obfd)->e_flags = elf_elfheader (ibfd)->e_flags; elf_elfheader (obfd)->e_ident[EI_CLASS] = elf_elfheader (ibfd)->e_ident[EI_CLASS]; @@ -14514,11 +14965,42 @@ _bfd_mips_elf_merge_private_bfd_data (bfd *ibfd, bfd *obfd) if (! bfd_set_arch_mach (obfd, bfd_get_arch (ibfd), bfd_get_mach (ibfd))) return FALSE; + + /* Update the ABI flags isa_level, isa_rev and isa_ext fields. */ + update_mips_abiflags_isa (obfd, &mips_elf_tdata (obfd)->abiflags); } return TRUE; } + /* Update the output abiflags fp_abi using the computed fp_abi. */ + out_attr = elf_known_obj_attributes (obfd)[OBJ_ATTR_GNU]; + mips_elf_tdata (obfd)->abiflags.fp_abi = out_attr[Tag_GNU_MIPS_ABI_FP].i; + +#define max(a,b) ((a) > (b) ? (a) : (b)) + /* Merge abiflags. */ + mips_elf_tdata (obfd)->abiflags.isa_rev + = max (mips_elf_tdata (obfd)->abiflags.isa_rev, + mips_elf_tdata (ibfd)->abiflags.isa_rev); + mips_elf_tdata (obfd)->abiflags.gpr_size + = max (mips_elf_tdata (obfd)->abiflags.gpr_size, + mips_elf_tdata (ibfd)->abiflags.gpr_size); + mips_elf_tdata (obfd)->abiflags.cpr1_size + = max (mips_elf_tdata (obfd)->abiflags.cpr1_size, + mips_elf_tdata (ibfd)->abiflags.cpr1_size); + mips_elf_tdata (obfd)->abiflags.cpr2_size + = max (mips_elf_tdata (obfd)->abiflags.cpr2_size, + mips_elf_tdata (ibfd)->abiflags.cpr2_size); +#undef max + mips_elf_tdata (obfd)->abiflags.ases + |= mips_elf_tdata (ibfd)->abiflags.ases; + mips_elf_tdata (obfd)->abiflags.flags1 + |= mips_elf_tdata (ibfd)->abiflags.flags1; + + new_flags = elf_elfheader (ibfd)->e_flags; + elf_elfheader (obfd)->e_flags |= new_flags & EF_MIPS_NOREORDER; + old_flags = elf_elfheader (obfd)->e_flags; + /* Check flag compatibility. */ new_flags &= ~EF_MIPS_NOREORDER; @@ -14541,30 +15023,6 @@ _bfd_mips_elf_merge_private_bfd_data (bfd *ibfd, bfd *obfd) if (new_flags == old_flags) return TRUE; - /* Check to see if the input BFD actually contains any sections. - If not, its flags may not have been initialised either, but it cannot - actually cause any incompatibility. */ - for (sec = ibfd->sections; sec != NULL; sec = sec->next) - { - /* Ignore synthetic sections and empty .text, .data and .bss sections - which are automatically generated by gas. Also ignore fake - (s)common sections, since merely defining a common symbol does - not affect compatibility. */ - if ((sec->flags & SEC_IS_COMMON) == 0 - && strcmp (sec->name, ".reginfo") - && strcmp (sec->name, ".mdebug") - && (sec->size != 0 - || (strcmp (sec->name, ".text") - && strcmp (sec->name, ".data") - && strcmp (sec->name, ".bss")))) - { - null_input_bfd = FALSE; - break; - } - } - if (null_input_bfd) - return TRUE; - ok = TRUE; if (((new_flags & (EF_MIPS_PIC | EF_MIPS_CPIC)) != 0) @@ -14605,6 +15063,9 @@ _bfd_mips_elf_merge_private_bfd_data (bfd *ibfd, bfd *obfd) elf_elfheader (obfd)->e_flags |= new_flags & (EF_MIPS_ARCH | EF_MIPS_MACH | EF_MIPS_32BITMODE); + /* Update the ABI flags isa_level, isa_rev, isa_ext fields. */ + update_mips_abiflags_isa (obfd, &mips_elf_tdata (obfd)->abiflags); + /* Copy across the ABI flags if OBFD doesn't use them and if that was what caused us to treat IBFD as 32-bit. */ if ((old_flags & EF_MIPS_ABI) == 0 @@ -14690,6 +15151,20 @@ _bfd_mips_elf_merge_private_bfd_data (bfd *ibfd, bfd *obfd) old_flags &= ~EF_MIPS_NAN2008; } + /* Compare FP64 state. */ + if ((new_flags & EF_MIPS_FP64) != (old_flags & EF_MIPS_FP64)) + { + _bfd_error_handler (_("%B: linking %s module with previous %s modules"), + ibfd, + (new_flags & EF_MIPS_FP64 + ? "-mfp64" : "-mfp32"), + (old_flags & EF_MIPS_FP64 + ? "-mfp64" : "-mfp32")); + ok = FALSE; + new_flags &= ~EF_MIPS_FP64; + old_flags &= ~EF_MIPS_FP64; + } + /* Warn about any other mismatches */ if (new_flags != old_flags) { @@ -14840,14 +15315,169 @@ _bfd_mips_fp_abi_string (int fp) case Val_GNU_MIPS_ABI_FP_SOFT: return "-msoft-float"; + case Val_GNU_MIPS_ABI_FP_OLD_64: + return _("-mips32r2 -mfp64 (12 callee-saved)"); + + case Val_GNU_MIPS_ABI_FP_XX: + return "-mfpxx"; + case Val_GNU_MIPS_ABI_FP_64: - return "-mips32r2 -mfp64"; + return "-mgp32 -mfp64"; + + case Val_GNU_MIPS_ABI_FP_64A: + return "-mgp32 -mfp64 -mno-odd-spreg"; default: return 0; } } +static void +print_mips_ases (FILE *file, unsigned int mask) +{ + if (mask & AFL_ASE_DSP) + fputs ("\n\tDSP ASE", file); + if (mask & AFL_ASE_DSPR2) + fputs ("\n\tDSP R2 ASE", file); + if (mask & AFL_ASE_EVA) + fputs ("\n\tEnhanced VA Scheme", file); + if (mask & AFL_ASE_MCU) + fputs ("\n\tMCU (MicroController) ASE", file); + if (mask & AFL_ASE_MDMX) + fputs ("\n\tMDMX ASE", file); + if (mask & AFL_ASE_MIPS3D) + fputs ("\n\tMIPS-3D ASE", file); + if (mask & AFL_ASE_MT) + fputs ("\n\tMT ASE", file); + if (mask & AFL_ASE_SMARTMIPS) + fputs ("\n\tSmartMIPS ASE", file); + if (mask & AFL_ASE_VIRT) + fputs ("\n\tVZ ASE", file); + if (mask & AFL_ASE_MSA) + fputs ("\n\tMSA ASE", file); + if (mask & AFL_ASE_MIPS16) + fputs ("\n\tMIPS16 ASE", file); + if (mask & AFL_ASE_MICROMIPS) + fputs ("\n\tMICROMIPS ASE", file); + if (mask & AFL_ASE_XPA) + fputs ("\n\tXPA ASE", file); + if (mask == 0) + fprintf (file, "\n\t%s", _("None")); +} + +static void +print_mips_isa_ext (FILE *file, unsigned int isa_ext) +{ + switch (isa_ext) + { + case 0: + fputs (_("None"), file); + break; + case AFL_EXT_XLR: + fputs ("RMI XLR", file); + break; + case AFL_EXT_OCTEON2: + fputs ("Cavium Networks Octeon2", file); + break; + case AFL_EXT_OCTEONP: + fputs ("Cavium Networks OcteonP", file); + break; + case AFL_EXT_LOONGSON_3A: + fputs ("Loongson 3A", file); + break; + case AFL_EXT_OCTEON: + fputs ("Cavium Networks Octeon", file); + break; + case AFL_EXT_5900: + fputs ("Toshiba R5900", file); + break; + case AFL_EXT_4650: + fputs ("MIPS R4650", file); + break; + case AFL_EXT_4010: + fputs ("LSI R4010", file); + break; + case AFL_EXT_4100: + fputs ("NEC VR4100", file); + break; + case AFL_EXT_3900: + fputs ("Toshiba R3900", file); + break; + case AFL_EXT_10000: + fputs ("MIPS R10000", file); + break; + case AFL_EXT_SB1: + fputs ("Broadcom SB-1", file); + break; + case AFL_EXT_4111: + fputs ("NEC VR4111/VR4181", file); + break; + case AFL_EXT_4120: + fputs ("NEC VR4120", file); + break; + case AFL_EXT_5400: + fputs ("NEC VR5400", file); + break; + case AFL_EXT_5500: + fputs ("NEC VR5500", file); + break; + case AFL_EXT_LOONGSON_2E: + fputs ("ST Microelectronics Loongson 2E", file); + break; + case AFL_EXT_LOONGSON_2F: + fputs ("ST Microelectronics Loongson 2F", file); + break; + default: + fputs (_("Unknown"), file); + break; + } +} + +static void +print_mips_fp_abi_value (FILE *file, int val) +{ + switch (val) + { + case Val_GNU_MIPS_ABI_FP_ANY: + fprintf (file, _("Hard or soft float\n")); + break; + case Val_GNU_MIPS_ABI_FP_DOUBLE: + fprintf (file, _("Hard float (double precision)\n")); + break; + case Val_GNU_MIPS_ABI_FP_SINGLE: + fprintf (file, _("Hard float (single precision)\n")); + break; + case Val_GNU_MIPS_ABI_FP_SOFT: + fprintf (file, _("Soft float\n")); + break; + case Val_GNU_MIPS_ABI_FP_OLD_64: + fprintf (file, _("Hard float (MIPS32r2 64-bit FPU 12 callee-saved)\n")); + break; + case Val_GNU_MIPS_ABI_FP_XX: + fprintf (file, _("Hard float (32-bit CPU, Any FPU)\n")); + break; + case Val_GNU_MIPS_ABI_FP_64: + fprintf (file, _("Hard float (32-bit CPU, 64-bit FPU)\n")); + break; + case Val_GNU_MIPS_ABI_FP_64A: + fprintf (file, _("Hard float compat (32-bit CPU, 64-bit FPU)\n")); + break; + default: + fprintf (file, "??? (%d)\n", val); + break; + } +} + +static int +get_mips_reg_size (int reg_size) +{ + return (reg_size == AFL_REG_NONE) ? 0 + : (reg_size == AFL_REG_32) ? 32 + : (reg_size == AFL_REG_64) ? 64 + : (reg_size == AFL_REG_128) ? 128 + : -1; +} + bfd_boolean _bfd_mips_elf_print_private_bfd_data (bfd *abfd, void *ptr) { @@ -14912,7 +15542,7 @@ _bfd_mips_elf_print_private_bfd_data (bfd *abfd, void *ptr) fprintf (file, " [nan2008]"); if (elf_elfheader (abfd)->e_flags & EF_MIPS_FP64) - fprintf (file, " [fp64]"); + fprintf (file, " [old fp64]"); if (elf_elfheader (abfd)->e_flags & EF_MIPS_32BITMODE) fprintf (file, " [32bitmode]"); @@ -14936,6 +15566,30 @@ _bfd_mips_elf_print_private_bfd_data (bfd *abfd, void *ptr) fputc ('\n', file); + if (mips_elf_tdata (abfd)->abiflags_valid) + { + Elf_Internal_ABIFlags_v0 *abiflags = &mips_elf_tdata (abfd)->abiflags; + fprintf (file, "\nMIPS ABI Flags Version: %d\n", abiflags->version); + fprintf (file, "\nISA: MIPS%d", abiflags->isa_level); + if (abiflags->isa_rev > 1) + fprintf (file, "r%d", abiflags->isa_rev); + fprintf (file, "\nGPR size: %d", + get_mips_reg_size (abiflags->gpr_size)); + fprintf (file, "\nCPR1 size: %d", + get_mips_reg_size (abiflags->cpr1_size)); + fprintf (file, "\nCPR2 size: %d", + get_mips_reg_size (abiflags->cpr2_size)); + fputs ("\nFP ABI: ", file); + print_mips_fp_abi_value (file, abiflags->fp_abi); + fputs ("ISA Extension: ", file); + print_mips_isa_ext (file, abiflags->isa_ext); + fputs ("\nASEs:", file); + print_mips_ases (file, abiflags->ases); + fprintf (file, "\nFLAGS 1: %8.8lx", abiflags->flags1); + fprintf (file, "\nFLAGS 2: %8.8lx", abiflags->flags2); + fputc ('\n', file); + } + return TRUE; } @@ -15258,4 +15912,8 @@ _bfd_mips_post_process_headers (bfd *abfd, struct bfd_link_info *link_info) } _bfd_elf_post_process_headers (abfd, link_info); + + if (mips_elf_tdata (abfd)->abiflags.fp_abi == Val_GNU_MIPS_ABI_FP_64 + || mips_elf_tdata (abfd)->abiflags.fp_abi == Val_GNU_MIPS_ABI_FP_64A) + i_ehdrp->e_ident[EI_ABIVERSION] = 3; } diff --git a/bfd/elfxx-mips.h b/bfd/elfxx-mips.h index 95b98ac..a4d1b27 100644 --- a/bfd/elfxx-mips.h +++ b/bfd/elfxx-mips.h @@ -157,6 +157,8 @@ extern bfd_vma _bfd_mips_elf_plt_sym_val (bfd_vma, const asection *, const arelent *rel); extern long _bfd_mips_elf_get_synthetic_symtab (bfd *, long, asymbol **, long, asymbol **, asymbol **); +extern bfd_boolean _bfd_mips_elf_gc_mark_extra_sections + (struct bfd_link_info *, elf_gc_mark_hook_fn); extern void _bfd_mips_post_process_headers (bfd *abfd, struct bfd_link_info *link_info); diff --git a/binutils/ChangeLog b/binutils/ChangeLog index cf01c90..4420b46 100644 --- a/binutils/ChangeLog +++ b/binutils/ChangeLog @@ -1,3 +1,13 @@ +2014-07-29 Matthew Fortune <matthew.fortune@imgtec.com> + + * readelf.c (get_mips_segment_type): Display name for PT_MIPS_ABIFLAGS. + (get_mips_section_type_name): Display name for SHT_MIPS_ABIFLAGS. + (display_mips_gnu_attribute): Abstracted fp abi printing to... + (print_mips_fp_abi_value): New static function. Handle new FP ABIs. + (print_mips_ases, print_mips_isa_ext): New static functions. + (get_mips_reg_size): Likewise. + (process_mips_specific): Display abiflags data. + 2014-07-28 Alan Modra <amodra@gmail.com> PR 13227 diff --git a/binutils/readelf.c b/binutils/readelf.c index f038422..7463c55 100644 --- a/binutils/readelf.c +++ b/binutils/readelf.c @@ -3167,6 +3167,8 @@ get_mips_segment_type (unsigned long type) return "RTPROC"; case PT_MIPS_OPTIONS: return "OPTIONS"; + case PT_MIPS_ABIFLAGS: + return "ABIFLAGS"; default: break; } @@ -3366,6 +3368,7 @@ get_mips_section_type_name (unsigned int sh_type) case SHT_MIPS_EH_REGION: return "MIPS_EH_REGION"; case SHT_MIPS_XLATE_OLD: return "MIPS_XLATE_OLD"; case SHT_MIPS_PDR_EXCEPTION: return "MIPS_PDR_EXCEPTION"; + case SHT_MIPS_ABIFLAGS: return "MIPS_ABIFLAGS"; default: break; } @@ -11990,6 +11993,41 @@ display_sparc_gnu_attribute (unsigned char * p, return display_tag_value (tag, p, end); } +static void +print_mips_fp_abi_value (int val) +{ + switch (val) + { + case Val_GNU_MIPS_ABI_FP_ANY: + printf (_("Hard or soft float\n")); + break; + case Val_GNU_MIPS_ABI_FP_DOUBLE: + printf (_("Hard float (double precision)\n")); + break; + case Val_GNU_MIPS_ABI_FP_SINGLE: + printf (_("Hard float (single precision)\n")); + break; + case Val_GNU_MIPS_ABI_FP_SOFT: + printf (_("Soft float\n")); + break; + case Val_GNU_MIPS_ABI_FP_OLD_64: + printf (_("Hard float (MIPS32r2 64-bit FPU 12 callee-saved)\n")); + break; + case Val_GNU_MIPS_ABI_FP_XX: + printf (_("Hard float (32-bit CPU, Any FPU)\n")); + break; + case Val_GNU_MIPS_ABI_FP_64: + printf (_("Hard float (32-bit CPU, 64-bit FPU)\n")); + break; + case Val_GNU_MIPS_ABI_FP_64A: + printf (_("Hard float compat (32-bit CPU, 64-bit FPU)\n")); + break; + default: + printf ("??? (%d)\n", val); + break; + } +} + static unsigned char * display_mips_gnu_attribute (unsigned char * p, int tag, @@ -12004,27 +12042,8 @@ display_mips_gnu_attribute (unsigned char * p, p += len; printf (" Tag_GNU_MIPS_ABI_FP: "); - switch (val) - { - case Val_GNU_MIPS_ABI_FP_ANY: - printf (_("Hard or soft float\n")); - break; - case Val_GNU_MIPS_ABI_FP_DOUBLE: - printf (_("Hard float (double precision)\n")); - break; - case Val_GNU_MIPS_ABI_FP_SINGLE: - printf (_("Hard float (single precision)\n")); - break; - case Val_GNU_MIPS_ABI_FP_SOFT: - printf (_("Soft float\n")); - break; - case Val_GNU_MIPS_ABI_FP_64: - printf (_("Hard float (MIPS32r2 64-bit FPU)\n")); - break; - default: - printf ("??? (%d)\n", val); - break; - } + print_mips_fp_abi_value (val); + return p; } @@ -12627,10 +12646,121 @@ print_mips_pltgot_entry (unsigned char * data, bfd_vma pltgot, bfd_vma addr) return addr + (is_32bit_elf ? 4 : 8); } +static void +print_mips_ases (unsigned int mask) +{ + if (mask & AFL_ASE_DSP) + fputs ("\n\tDSP ASE", stdout); + if (mask & AFL_ASE_DSPR2) + fputs ("\n\tDSP R2 ASE", stdout); + if (mask & AFL_ASE_EVA) + fputs ("\n\tEnhanced VA Scheme", stdout); + if (mask & AFL_ASE_MCU) + fputs ("\n\tMCU (MicroController) ASE", stdout); + if (mask & AFL_ASE_MDMX) + fputs ("\n\tMDMX ASE", stdout); + if (mask & AFL_ASE_MIPS3D) + fputs ("\n\tMIPS-3D ASE", stdout); + if (mask & AFL_ASE_MT) + fputs ("\n\tMT ASE", stdout); + if (mask & AFL_ASE_SMARTMIPS) + fputs ("\n\tSmartMIPS ASE", stdout); + if (mask & AFL_ASE_VIRT) + fputs ("\n\tVZ ASE", stdout); + if (mask & AFL_ASE_MSA) + fputs ("\n\tMSA ASE", stdout); + if (mask & AFL_ASE_MIPS16) + fputs ("\n\tMIPS16 ASE", stdout); + if (mask & AFL_ASE_MICROMIPS) + fputs ("\n\tMICROMIPS ASE", stdout); + if (mask & AFL_ASE_XPA) + fputs ("\n\tXPA ASE", stdout); + if (mask == 0) + fprintf (stdout, "\n\t%s", _("None")); +} + +static void +print_mips_isa_ext (unsigned int isa_ext) +{ + switch (isa_ext) + { + case 0: + fputs (_("None"), stdout); + break; + case AFL_EXT_XLR: + fputs ("RMI XLR", stdout); + break; + case AFL_EXT_OCTEON2: + fputs ("Cavium Networks Octeon2", stdout); + break; + case AFL_EXT_OCTEONP: + fputs ("Cavium Networks OcteonP", stdout); + break; + case AFL_EXT_LOONGSON_3A: + fputs ("Loongson 3A", stdout); + break; + case AFL_EXT_OCTEON: + fputs ("Cavium Networks Octeon", stdout); + break; + case AFL_EXT_5900: + fputs ("Toshiba R5900", stdout); + break; + case AFL_EXT_4650: + fputs ("MIPS R4650", stdout); + break; + case AFL_EXT_4010: + fputs ("LSI R4010", stdout); + break; + case AFL_EXT_4100: + fputs ("NEC VR4100", stdout); + break; + case AFL_EXT_3900: + fputs ("Toshiba R3900", stdout); + break; + case AFL_EXT_10000: + fputs ("MIPS R10000", stdout); + break; + case AFL_EXT_SB1: + fputs ("Broadcom SB-1", stdout); + break; + case AFL_EXT_4111: + fputs ("NEC VR4111/VR4181", stdout); + break; + case AFL_EXT_4120: + fputs ("NEC VR4120", stdout); + break; + case AFL_EXT_5400: + fputs ("NEC VR5400", stdout); + break; + case AFL_EXT_5500: + fputs ("NEC VR5500", stdout); + break; + case AFL_EXT_LOONGSON_2E: + fputs ("ST Microelectronics Loongson 2E", stdout); + break; + case AFL_EXT_LOONGSON_2F: + fputs ("ST Microelectronics Loongson 2F", stdout); + break; + default: + fputs (_("Unknown"), stdout); + } +} + +static int +get_mips_reg_size (int reg_size) +{ + return (reg_size == AFL_REG_NONE) ? 0 + : (reg_size == AFL_REG_32) ? 32 + : (reg_size == AFL_REG_64) ? 64 + : (reg_size == AFL_REG_128) ? 128 + : -1; +} + static int process_mips_specific (FILE * file) { Elf_Internal_Dyn * entry; + Elf_Internal_Shdr *sect = NULL; size_t liblist_offset = 0; size_t liblistno = 0; size_t conflictsno = 0; @@ -12648,6 +12778,57 @@ process_mips_specific (FILE * file) process_attributes (file, NULL, SHT_GNU_ATTRIBUTES, NULL, display_mips_gnu_attribute); + sect = find_section (".MIPS.abiflags"); + + if (sect != NULL) + { + Elf_External_ABIFlags_v0 *abiflags_ext; + Elf_Internal_ABIFlags_v0 abiflags_in; + + if (sizeof (Elf_External_ABIFlags_v0) != sect->sh_size) + fputs ("\nCorrupt ABI Flags section.\n", stdout); + else + { + abiflags_ext = get_data (NULL, file, sect->sh_offset, 1, + sect->sh_size, _("MIPS ABI Flags section")); + if (abiflags_ext) + { + abiflags_in.version = BYTE_GET (abiflags_ext->version); + abiflags_in.isa_level = BYTE_GET (abiflags_ext->isa_level); + abiflags_in.isa_rev = BYTE_GET (abiflags_ext->isa_rev); + abiflags_in.gpr_size = BYTE_GET (abiflags_ext->gpr_size); + abiflags_in.cpr1_size = BYTE_GET (abiflags_ext->cpr1_size); + abiflags_in.cpr2_size = BYTE_GET (abiflags_ext->cpr2_size); + abiflags_in.fp_abi = BYTE_GET (abiflags_ext->fp_abi); + abiflags_in.isa_ext = BYTE_GET (abiflags_ext->isa_ext); + abiflags_in.ases = BYTE_GET (abiflags_ext->ases); + abiflags_in.flags1 = BYTE_GET (abiflags_ext->flags1); + abiflags_in.flags2 = BYTE_GET (abiflags_ext->flags2); + + printf ("\nMIPS ABI Flags Version: %d\n", abiflags_in.version); + printf ("\nISA: MIPS%d", abiflags_in.isa_level); + if (abiflags_in.isa_rev > 1) + printf ("r%d", abiflags_in.isa_rev); + printf ("\nGPR size: %d", + get_mips_reg_size (abiflags_in.gpr_size)); + printf ("\nCPR1 size: %d", + get_mips_reg_size (abiflags_in.cpr1_size)); + printf ("\nCPR2 size: %d", + get_mips_reg_size (abiflags_in.cpr2_size)); + fputs ("\nFP ABI: ", stdout); + print_mips_fp_abi_value (abiflags_in.fp_abi); + fputs ("ISA Extension: ", stdout); + print_mips_isa_ext (abiflags_in.isa_ext); + fputs ("\nASEs:", stdout); + print_mips_ases (abiflags_in.ases); + printf ("\nFLAGS 1: %8.8lx", abiflags_in.flags1); + printf ("\nFLAGS 2: %8.8lx", abiflags_in.flags2); + fputc ('\n', stdout); + free (abiflags_ext); + } + } + } + /* We have a lot of special sections. Thanks SGI! */ if (dynamic_section == NULL) /* No information available. */ @@ -12787,11 +12968,11 @@ process_mips_specific (FILE * file) if (options_offset != 0) { Elf_External_Options * eopt; - Elf_Internal_Shdr * sect = section_headers; Elf_Internal_Options * iopt; Elf_Internal_Options * option; size_t offset; int cnt; + sect = section_headers; /* Find the section header so that we get the size. */ while (sect->sh_type != SHT_MIPS_OPTIONS) diff --git a/binutils/testsuite/ChangeLog b/binutils/testsuite/ChangeLog index bc7643b..5f0403d 100644 --- a/binutils/testsuite/ChangeLog +++ b/binutils/testsuite/ChangeLog @@ -1,3 +1,10 @@ +2014-07-29 Matthew Fortune <matthew.fortune@imgtec.com> + + * binutils-all/readelf.s: Account for .MIPS.abiflags and + .gnu.attributes. + * binutils-all/readelf.ss-tmips: Likewise. + * binutils-all/strip-3.d: Likewise. + 2014-07-10 Will Newton <will.newton@linaro.org> * binutils-all/objcopy.exp: Disable the strip-10 test on diff --git a/binutils/testsuite/binutils-all/readelf.s b/binutils/testsuite/binutils-all/readelf.s index 303e0c7..3b044b1 100644 --- a/binutils/testsuite/binutils-all/readelf.s +++ b/binutils/testsuite/binutils-all/readelf.s @@ -6,16 +6,16 @@ Section Headers: # On the normal MIPS systems, sections must be aligned to 16 byte # boundaries. On IA64, text sections are aligned to 16 byte boundaries. +\[ 1\] .text +PROGBITS +00000000 0000(34|40) 0000(08|10) 00 +AX +0 +0 +(.|..) - +\[ 2\] .rel.+text +REL. +0+ 0+.* 0000.. 0. +I +. +1 +4 + +\[ 2\] .rel.+text +REL. +0+ 0+.* 0000.. 0. +I +.+ +1 +4 # MIPS targets put .rela.text here. #... +\[ .\] .data +PROGBITS +00000000 0000(3c|48|50) 0000(04|10) 00 +WA +0 +0 +(.|..) +\[ .\] .bss +NOBITS +00000000 0000(40|4c|60) 000000 00 +WA +0 +0 +(.|..) -# MIPS targets put .reginfo and .mdebug here. +# MIPS targets put .reginfo, .mdebug, .MIPS.abiflags and .gnu.attributes here. # v850 targets put .call_table_data and .call_table_text here. #... +\[ .\] .shstrtab +STRTAB +00000000 0+.* 0+.* 00 +0 +0 +. - +\[ .\] .symtab +SYMTAB +00000000 0+.* 0+.* 10 +.. +. +4 + +\[..\] .symtab +SYMTAB +00000000 0+.* 0+.* 10 +.. +.+ +4 +\[..\] .strtab +STRTAB +00000000 0+.* 0+.* 00 +0 +0 +1 Key to Flags: #... diff --git a/binutils/testsuite/binutils-all/readelf.ss-tmips b/binutils/testsuite/binutils-all/readelf.ss-tmips index 1f87248..c59f753 100644 --- a/binutils/testsuite/binutils-all/readelf.ss-tmips +++ b/binutils/testsuite/binutils-all/readelf.ss-tmips @@ -1,5 +1,5 @@ -Symbol table '.symtab' contains 12 entries: +Symbol table '.symtab' contains 14 entries: +Num: +Value +Size +Type +Bind +Vis +Ndx +Name +0: 00000000 +0 +NOTYPE +LOCAL +DEFAULT +UND +1: 00000000 +0 +SECTION +LOCAL +DEFAULT +1 @@ -9,7 +9,9 @@ Symbol table '.symtab' contains 12 entries: +5: 00000000 +0 +NOTYPE +LOCAL +DEFAULT +3 static_data_symbol +6: 00000000 +0 +SECTION +LOCAL +DEFAULT +5 +7: 00000000 +0 +SECTION +LOCAL +DEFAULT +6 - +8: 00000000 +0 +OBJECT +GLOBAL +DEFAULT +1 text_symbol - +9: 00000000 +0 +NOTYPE +GLOBAL +DEFAULT +UND external_symbol - +10: 00000000 +0 +OBJECT +GLOBAL +DEFAULT +3 data_symbol - +11: 00000004 +4 +(COMMON|OBJECT) +GLOBAL +DEFAULT +(PRC|COM) common_symbol + +8: 00000000 +0 +SECTION +LOCAL +DEFAULT +7 + +9: 00000000 +0 +SECTION +LOCAL +DEFAULT +8 + +10: 00000000 +0 +OBJECT +GLOBAL +DEFAULT +1 text_symbol + +11: 00000000 +0 +NOTYPE +GLOBAL +DEFAULT +UND external_symbol + +12: 00000000 +0 +OBJECT +GLOBAL +DEFAULT +3 data_symbol + +13: 00000004 +4 +(COMMON|OBJECT) +GLOBAL +DEFAULT +(PRC|COM) common_symbol diff --git a/binutils/testsuite/binutils-all/strip-3.d b/binutils/testsuite/binutils-all/strip-3.d index acfec85..ee2708e 100644 --- a/binutils/testsuite/binutils-all/strip-3.d +++ b/binutils/testsuite/binutils-all/strip-3.d @@ -1,6 +1,6 @@ #PROG: strip #source: empty.s -#strip: -R .text -R .data -R .bss -R .ARM.attributes -R .reginfo -R .pdr -R .xtensa.info +#strip: -R .text -R .data -R .bss -R .ARM.attributes -R .reginfo -R .gnu.attributes -R .MIPS.abiflags -R .pdr -R .xtensa.info #readelf: -S --wide #name: strip empty file #target: *-*-linux* *-*-gnu* diff --git a/elfcpp/ChangeLog b/elfcpp/ChangeLog index d7dc3c3..043fb67 100644 --- a/elfcpp/ChangeLog +++ b/elfcpp/ChangeLog @@ -1,3 +1,7 @@ +2014-07-29 Matthew Fortune <matthew.fortune@imgtec.com> + + * elfcpp.h (PT_MIPS_ABIFLAGS): New program header type. + 2014-07-02 Jing Yu <jingyu@google.com> * aarch64.h: New file. New enums for aarch64-elf64 relocations. diff --git a/elfcpp/elfcpp.h b/elfcpp/elfcpp.h index 8e8e675..3e55db5 100644 --- a/elfcpp/elfcpp.h +++ b/elfcpp/elfcpp.h @@ -495,6 +495,8 @@ enum PT PT_MIPS_RTPROC = 0x70000001, // .MIPS.options section. PT_MIPS_OPTIONS = 0x70000002, + // .MIPS.abiflags section. + PT_MIPS_ABIFLAGS = 0x70000003, // Platform architecture compatibility information PT_AARCH64_ARCHEXT = 0x70000000, // Exception unwind tables diff --git a/gas/ChangeLog b/gas/ChangeLog index c44b7cc..487b0c7 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,40 @@ +2014-07-29 Matthew Fortune <matthew.fortune@imgtec.com> + + * config/tc-mips.c (mips_flags_frag): New static global. + (struct mips_set_options): Add oddspreg field. + (file_mips_opts, mips_opts): Initialize oddspreg. + (ISA_HAS_ODD_SINGLE_FPR): Add CPU argument and update for R5900 and + Loongson-3a. + (enum options, md_longopts, md_parse_option): Add -mfpxx, -modd-spreg + and -mno-odd-spreg options. + (md_begin): Create .MIPS.abiflags section. + (fpabi_incompatible_with, fpabi_requires): New static function. + (check_fpabi): Likewise. + (mips_check_options): Handle fp=xx and oddspreg restrictions. + (file_mips_check_options): Set oddspreg by default for fp=xx. + (mips_oddfpreg_ok): Re-write function. + (check_regno): Check odd numbered registers regardless of FPR size. + For fp != 32 use as_bad instead of as_warn. + (match_float_constant): Rewrite check regarding FP register width. Add + support for generating constants when MXHC1 is present. Handle fp=xx + to comply with the ABI. + (macro): Update M_LI_DD similarly to match_float_constant. Generate + MTHC1 when available. Check that correct code can be generated for + fp=xx and fp=64 ABIs. + (parse_code_option, s_mipsset): Add fp=xx, oddspreg and nooddspreg + options. + (mips_convert_ase_flags): New static function. + (mips_elf_final_processing): Use fpabi == Val_GNU_MIPS_ABI_FP_OLD_64 + to determine when to add the EF_MIPS_FP64 flag. Populate the + .MIPS.abiflags section. + (md_mips_end): Update .gnu_attribute based on command line and .module + as applicable. Use check_fpabi to ensure .gnu.attribute and command + line/.module options are consistent. + * doc/as.texinfo: Add missing -mgp64/-mfp64 options and document new + -mfpxx, -modd-spreg and -mno-odd-spreg options. + * doc/c-mips.texi: Document -mfpxx, -modd-spreg, -mno-odd-spreg, + gnu_attribute values and FP ABIs. + 2014-07-27 Joel Sherrill <joel.sherrill@oarcorp.com> Add RTEMS target support and simplify matching diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c index 4814a69..2340afc 100644 --- a/gas/config/tc-mips.c +++ b/gas/config/tc-mips.c @@ -89,6 +89,7 @@ int mips_flag_pdr = TRUE; #include "ecoff.h" static char *mips_regmask_frag; +static char *mips_flags_frag; #define ZERO 0 #define ATREG 1 @@ -257,6 +258,10 @@ struct mips_set_options Changed by .set singlefloat or .set doublefloat, command-line options -msingle-float or -mdouble-float. The default is false. */ bfd_boolean single_float; + + /* 1 if single-precision operations on odd-numbered registers are + allowed. */ + int oddspreg; }; /* Specifies whether module level options have been checked yet. */ @@ -275,7 +280,7 @@ static struct mips_set_options file_mips_opts = /* noreorder */ 0, /* at */ ATREG, /* warn_about_macros */ 0, /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE, /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN, /* sym32 */ FALSE, - /* soft_float */ FALSE, /* single_float */ FALSE + /* soft_float */ FALSE, /* single_float */ FALSE, /* oddspreg */ -1 }; /* This is similar to file_mips_opts, but for the current set of options. */ @@ -286,7 +291,7 @@ static struct mips_set_options mips_opts = /* noreorder */ 0, /* at */ ATREG, /* warn_about_macros */ 0, /* nomove */ 0, /* nobopt */ 0, /* noautoextend */ 0, /* insn32 */ FALSE, /* gp */ -1, /* fp */ -1, /* arch */ CPU_UNKNOWN, /* sym32 */ FALSE, - /* soft_float */ FALSE, /* single_float */ FALSE + /* soft_float */ FALSE, /* single_float */ FALSE, /* oddspreg */ -1 }; /* Which bits of file_ase were explicitly set or cleared by ASE options. */ @@ -392,15 +397,17 @@ static int mips_32bitmode = 0; ) /* Return true if ISA supports single-precision floats in odd registers. */ -#define ISA_HAS_ODD_SINGLE_FPR(ISA) \ - ((ISA) == ISA_MIPS32 \ - || (ISA) == ISA_MIPS32R2 \ - || (ISA) == ISA_MIPS32R3 \ - || (ISA) == ISA_MIPS32R5 \ - || (ISA) == ISA_MIPS64 \ - || (ISA) == ISA_MIPS64R2 \ - || (ISA) == ISA_MIPS64R3 \ - || (ISA) == ISA_MIPS64R5) +#define ISA_HAS_ODD_SINGLE_FPR(ISA, CPU)\ + (((ISA) == ISA_MIPS32 \ + || (ISA) == ISA_MIPS32R2 \ + || (ISA) == ISA_MIPS32R3 \ + || (ISA) == ISA_MIPS32R5 \ + || (ISA) == ISA_MIPS64 \ + || (ISA) == ISA_MIPS64R2 \ + || (ISA) == ISA_MIPS64R3 \ + || (ISA) == ISA_MIPS64R5 \ + || (CPU) == CPU_R5900) \ + && (CPU) != CPU_LOONGSON_3A) /* Return true if ISA supports move to/from high part of a 64-bit floating-point register. */ @@ -1407,6 +1414,7 @@ enum options OPTION_CONSTRUCT_FLOATS, OPTION_NO_CONSTRUCT_FLOATS, OPTION_FP64, + OPTION_FPXX, OPTION_GP64, OPTION_RELAX_BRANCH, OPTION_NO_RELAX_BRANCH, @@ -1434,6 +1442,8 @@ enum options OPTION_NO_PDR, OPTION_MVXWORKS_PIC, OPTION_NAN, + OPTION_ODD_SPREG, + OPTION_NO_ODD_SPREG, OPTION_END_OF_ENUM }; @@ -1526,6 +1536,7 @@ struct option md_longopts[] = {"construct-floats", no_argument, NULL, OPTION_CONSTRUCT_FLOATS}, {"no-construct-floats", no_argument, NULL, OPTION_NO_CONSTRUCT_FLOATS}, {"mfp64", no_argument, NULL, OPTION_FP64}, + {"mfpxx", no_argument, NULL, OPTION_FPXX}, {"mgp64", no_argument, NULL, OPTION_GP64}, {"relax-branch", no_argument, NULL, OPTION_RELAX_BRANCH}, {"no-relax-branch", no_argument, NULL, OPTION_NO_RELAX_BRANCH}, @@ -1539,6 +1550,8 @@ struct option md_longopts[] = {"mhard-float", no_argument, NULL, OPTION_HARD_FLOAT}, {"msingle-float", no_argument, NULL, OPTION_SINGLE_FLOAT}, {"mdouble-float", no_argument, NULL, OPTION_DOUBLE_FLOAT}, + {"modd-spreg", no_argument, NULL, OPTION_ODD_SPREG}, + {"mno-odd-spreg", no_argument, NULL, OPTION_NO_ODD_SPREG}, /* Strictly speaking this next option is ELF specific, but we allow it for other ports as well in order to @@ -3612,6 +3625,12 @@ md_begin (void) } } + sec = subseg_new (".MIPS.abiflags", (subsegT) 0); + bfd_set_section_flags (stdoutput, sec, + SEC_READONLY | SEC_DATA | SEC_ALLOC | SEC_LOAD); + bfd_set_section_alignment (stdoutput, sec, 3); + mips_flags_frag = frag_more (sizeof (Elf_External_ABIFlags_v0)); + if (ECOFF_DEBUGGING) { sec = subseg_new (".mdebug", (subsegT) 0); @@ -3635,6 +3654,88 @@ md_begin (void) init_vr4120_conflicts (); } +static inline void +fpabi_incompatible_with (int fpabi, const char *what) +{ + as_warn (_(".gnu_attribute %d,%d is incompatible with `%s'"), + Tag_GNU_MIPS_ABI_FP, fpabi, what); +} + +static inline void +fpabi_requires (int fpabi, const char *what) +{ + as_warn (_(".gnu_attribute %d,%d requires `%s'"), + Tag_GNU_MIPS_ABI_FP, fpabi, what); +} + +/* Check -mabi and register sizes against the specified FP ABI. */ +static void +check_fpabi (int fpabi) +{ + bfd_boolean needs_check = FALSE; + switch (fpabi) + { + case Val_GNU_MIPS_ABI_FP_DOUBLE: + if (file_mips_opts.gp == 64 && file_mips_opts.fp == 32) + fpabi_incompatible_with (fpabi, "gp=64 fp=32"); + else if (file_mips_opts.gp == 32 && file_mips_opts.fp == 64) + fpabi_incompatible_with (fpabi, "gp=32 fp=64"); + else + needs_check = TRUE; + break; + + case Val_GNU_MIPS_ABI_FP_XX: + if (mips_abi != O32_ABI) + fpabi_requires (fpabi, "-mabi=32"); + else if (file_mips_opts.fp != 0) + fpabi_requires (fpabi, "fp=xx"); + else + needs_check = TRUE; + break; + + case Val_GNU_MIPS_ABI_FP_64A: + case Val_GNU_MIPS_ABI_FP_64: + if (mips_abi != O32_ABI) + fpabi_requires (fpabi, "-mabi=32"); + else if (file_mips_opts.fp != 64) + fpabi_requires (fpabi, "fp=64"); + else if (fpabi == Val_GNU_MIPS_ABI_FP_64 && !file_mips_opts.oddspreg) + fpabi_incompatible_with (fpabi, "nooddspreg"); + else if (fpabi == Val_GNU_MIPS_ABI_FP_64A && file_mips_opts.oddspreg) + fpabi_requires (fpabi, "nooddspreg"); + else + needs_check = TRUE; + break; + + case Val_GNU_MIPS_ABI_FP_SINGLE: + if (file_mips_opts.soft_float) + fpabi_incompatible_with (fpabi, "softfloat"); + else if (!file_mips_opts.single_float) + fpabi_requires (fpabi, "singlefloat"); + break; + + case Val_GNU_MIPS_ABI_FP_SOFT: + if (!file_mips_opts.soft_float) + fpabi_requires (fpabi, "softfloat"); + break; + + case Val_GNU_MIPS_ABI_FP_OLD_64: + as_warn (_(".gnu_attribute %d,%d is no longer supported"), + Tag_GNU_MIPS_ABI_FP, fpabi); + break; + + default: + as_warn (_(".gnu_attribute %d,%d is not a recognized" + " floating-point ABI"), Tag_GNU_MIPS_ABI_FP, fpabi); + break; + } + + if (needs_check && file_mips_opts.soft_float) + fpabi_incompatible_with (fpabi, "softfloat"); + else if (needs_check && file_mips_opts.single_float) + fpabi_incompatible_with (fpabi, "singlefloat"); +} + /* Perform consistency checks on the current options. */ static void @@ -3653,6 +3754,12 @@ mips_check_options (struct mips_set_options *opts, bfd_boolean abi_checks) /* Check the size of the float registers agrees with the ABI and ISA. */ switch (opts->fp) { + case 0: + if (!CPU_HAS_LDC1_SDC1 (opts->arch)) + as_bad (_("`fp=xx' used with a cpu lacking ldc1/sdc1 instructions")); + else if (opts->single_float == 1) + as_bad (_("`fp=xx' cannot be used with `singlefloat'")); + break; case 64: if (!ISA_HAS_64BIT_FPRS (opts->isa)) as_bad (_("`fp=64' used with a 32-bit fpu")); @@ -3671,6 +3778,9 @@ mips_check_options (struct mips_set_options *opts, bfd_boolean abi_checks) break; } + if (ABI_NEEDS_64BIT_REGS (mips_abi) && !opts->oddspreg) + as_bad (_("`nooddspreg` cannot be used with a 64-bit ABI")); + if (opts->micromips == 1 && opts->mips16 == 1) as_bad (_("`mips16' cannot be used with `micromips'")); } @@ -3728,6 +3838,16 @@ file_mips_check_options (void) arch_info = mips_cpu_info_from_arch (file_mips_opts.arch); + /* Disable operations on odd-numbered floating-point registers by default + when using the FPXX ABI. */ + if (file_mips_opts.oddspreg < 0) + { + if (file_mips_opts.fp == 0) + file_mips_opts.oddspreg = 0; + else + file_mips_opts.oddspreg = 1; + } + /* End of GCC-shared inference code. */ /* This flag is set when we have a 64-bit capable CPU but use only @@ -4377,39 +4497,42 @@ static bfd_boolean mips_oddfpreg_ok (const struct mips_opcode *insn, int opnum) { const char *s = insn->name; + bfd_boolean oddspreg = (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa, mips_opts.arch) + || FPR_SIZE == 64) + && mips_opts.oddspreg; if (insn->pinfo == INSN_MACRO) /* Let a macro pass, we'll catch it later when it is expanded. */ return TRUE; - if (ISA_HAS_ODD_SINGLE_FPR (mips_opts.isa) || mips_opts.arch == CPU_R5900) - { - /* Allow odd registers for single-precision ops. */ - switch (insn->pinfo & (FP_S | FP_D)) - { - case FP_S: - case 0: - return TRUE; - case FP_D: - return FALSE; - default: - break; - } + /* Single-precision coprocessor loads and moves are OK for 32-bit registers, + otherwise it depends on oddspreg. */ + if ((insn->pinfo & FP_S) + && (insn->pinfo & (INSN_LOAD_MEMORY | INSN_STORE_MEMORY + | INSN_LOAD_COPROC_DELAY | INSN_COPROC_MOVE_DELAY))) + return FPR_SIZE == 32 || oddspreg; - /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */ - s = strchr (insn->name, '.'); - if (s != NULL && opnum == 2) - s = strchr (s + 1, '.'); - return (s != NULL && (s[1] == 'w' || s[1] == 's')); + /* Allow odd registers for single-precision ops and double-precision if the + floating-point registers are 64-bit wide. */ + switch (insn->pinfo & (FP_S | FP_D)) + { + case FP_S: + case 0: + return oddspreg; + case FP_D: + return FPR_SIZE == 64; + default: + break; } - /* Single-precision coprocessor loads and moves are OK too. */ - if ((insn->pinfo & FP_S) - && (insn->pinfo & (INSN_COPROC_MEMORY_DELAY | INSN_STORE_MEMORY - | INSN_LOAD_COPROC_DELAY | INSN_COPROC_MOVE_DELAY))) - return TRUE; + /* Cvt.w.x and cvt.x.w allow an odd register for a 'w' or 's' operand. */ + s = strchr (insn->name, '.'); + if (s != NULL && opnum == 2) + s = strchr (s + 1, '.'); + if (s != NULL && (s[1] == 'w' || s[1] == 's')) + return oddspreg; - return FALSE; + return FPR_SIZE == 64; } /* Information about an instruction argument that we're trying to match. */ @@ -4632,9 +4755,16 @@ check_regno (struct mips_arg_info *arg, if (type == OP_REG_FP && (regno & 1) != 0 - && FPR_SIZE != 64 && !mips_oddfpreg_ok (arg->insn->insn_mo, arg->opnum)) - as_warn (_("float register should be even, was %d"), regno); + { + /* This was a warning prior to introducing O32 FPXX and FP64 support + so maintain a warning for FP32 but raise an error for the new + cases. */ + if (FPR_SIZE == 32) + as_warn (_("float register should be even, was %d"), regno); + else + as_bad (_("float register should be even, was %d"), regno); + } if (type == OP_REG_CCC) { @@ -5488,13 +5618,16 @@ match_float_constant (struct mips_arg_info *arg, expressionS *imm, /* Handle 64-bit constants for which an immediate value is best. */ if (length == 8 && !mips_disable_float_construction - /* Constants can only be constructed in GPRs and copied - to FPRs if the GPRs are at least as wide as the FPRs. - Force the constant into memory if we are using 64-bit FPRs - but the GPRs are only 32 bits wide. */ - /* ??? No longer true with the addition of MTHC1, but this - is legacy code... */ - && (using_gprs || !(FPR_SIZE == 64 && GPR_SIZE == 32)) + /* Constants can only be constructed in GPRs and copied to FPRs if the + GPRs are at least as wide as the FPRs or MTHC1 is available. + Unlike most tests for 32-bit floating-point registers this check + specifically looks for GPR_SIZE == 32 as the FPXX ABI does not + permit 64-bit moves without MXHC1. + Force the constant into memory otherwise. */ + && (using_gprs + || GPR_SIZE == 64 + || ISA_HAS_MXHC1 (mips_opts.isa) + || FPR_SIZE == 32) && ((data[0] == 0 && data[1] == 0) || (data[2] == 0 && data[3] == 0)) && ((data[4] == 0 && data[5] == 0) @@ -5504,7 +5637,7 @@ match_float_constant (struct mips_arg_info *arg, expressionS *imm, If using 32-bit registers, set IMM to the high order 32 bits and OFFSET to the low order 32 bits. Otherwise, set IMM to the entire 64 bit constant. */ - if (using_gprs ? GPR_SIZE == 32 : FPR_SIZE != 64) + if (GPR_SIZE == 32 || (!using_gprs && FPR_SIZE != 64)) { imm->X_op = O_constant; offset->X_op = O_constant; @@ -11686,14 +11819,18 @@ macro (struct mips_cl_insn *ip, char *str) { used_at = 1; load_register (AT, &imm_expr, FPR_SIZE == 64); - if (FPR_SIZE == 64) - { - gas_assert (GPR_SIZE == 64); - macro_build (NULL, "dmtc1", "t,S", AT, op[0]); - } + if (FPR_SIZE == 64 && GPR_SIZE == 64) + macro_build (NULL, "dmtc1", "t,S", AT, op[0]); else { - macro_build (NULL, "mtc1", "t,G", AT, op[0] + 1); + if (ISA_HAS_MXHC1 (mips_opts.isa)) + macro_build (NULL, "mthc1", "t,G", AT, op[0]); + else if (FPR_SIZE != 32) + as_bad (_("Unable to generate `%s' compliant code " + "without mthc1"), + (FPR_SIZE == 64) ? "fp64" : "fpxx"); + else + macro_build (NULL, "mtc1", "t,G", AT, op[0] + 1); if (offset_expr.X_op == O_absent) macro_build (NULL, "mtc1", "t,G", 0, op[0]); else @@ -13939,10 +14076,22 @@ md_parse_option (int c, char *arg) file_mips_opts.fp = 32; break; + case OPTION_FPXX: + file_mips_opts.fp = 0; + break; + case OPTION_FP64: file_mips_opts.fp = 64; break; + case OPTION_ODD_SPREG: + file_mips_opts.oddspreg = 1; + break; + + case OPTION_NO_ODD_SPREG: + file_mips_opts.oddspreg = 0; + break; + case OPTION_SINGLE_FLOAT: file_mips_opts.single_float = 1; break; @@ -15031,6 +15180,8 @@ parse_code_option (char * name) mips_opts.gp = 64; else if (strcmp (name, "fp=32") == 0) mips_opts.fp = 32; + else if (strcmp (name, "fp=xx") == 0) + mips_opts.fp = 0; else if (strcmp (name, "fp=64") == 0) mips_opts.fp = 64; else if (strcmp (name, "softfloat") == 0) @@ -15041,6 +15192,10 @@ parse_code_option (char * name) mips_opts.single_float = 1; else if (strcmp (name, "doublefloat") == 0) mips_opts.single_float = 0; + else if (strcmp (name, "nooddspreg") == 0) + mips_opts.oddspreg = 0; + else if (strcmp (name, "oddspreg") == 0) + mips_opts.oddspreg = 1; else if (strcmp (name, "mips16") == 0 || strcmp (name, "MIPS-16") == 0) mips_opts.mips16 = 1; @@ -15202,13 +15357,17 @@ s_mipsset (int x ATTRIBUTE_UNUSED) case 0: break; case ISA_MIPS1: + /* MIPS I cannot support FPXX. */ + mips_opts.fp = 32; + /* fall-through. */ case ISA_MIPS2: case ISA_MIPS32: case ISA_MIPS32R2: case ISA_MIPS32R3: case ISA_MIPS32R5: mips_opts.gp = 32; - mips_opts.fp = 32; + if (mips_opts.fp != 0) + mips_opts.fp = 32; break; case ISA_MIPS3: case ISA_MIPS4: @@ -15218,10 +15377,13 @@ s_mipsset (int x ATTRIBUTE_UNUSED) case ISA_MIPS64R3: case ISA_MIPS64R5: mips_opts.gp = 64; - if (mips_opts.arch == CPU_R5900) - mips_opts.fp = 32; - else - mips_opts.fp = 64; + if (mips_opts.fp != 0) + { + if (mips_opts.arch == CPU_R5900) + mips_opts.fp = 32; + else + mips_opts.fp = 64; + } break; default: as_bad (_("unknown ISA level %s"), name + 4); @@ -17371,11 +17533,123 @@ mips_add_dot_label (symbolS *sym) mips_compressed_mark_label (sym); } +/* Converting ASE flags from internal to .MIPS.abiflags values. */ +static unsigned int +mips_convert_ase_flags (int ase) +{ + unsigned int ext_ases = 0; + + if (ase & ASE_DSP) + ext_ases |= AFL_ASE_DSP; + if (ase & ASE_DSPR2) + ext_ases |= AFL_ASE_DSPR2; + if (ase & ASE_EVA) + ext_ases |= AFL_ASE_EVA; + if (ase & ASE_MCU) + ext_ases |= AFL_ASE_MCU; + if (ase & ASE_MDMX) + ext_ases |= AFL_ASE_MDMX; + if (ase & ASE_MIPS3D) + ext_ases |= AFL_ASE_MIPS3D; + if (ase & ASE_MT) + ext_ases |= AFL_ASE_MT; + if (ase & ASE_SMARTMIPS) + ext_ases |= AFL_ASE_SMARTMIPS; + if (ase & ASE_VIRT) + ext_ases |= AFL_ASE_VIRT; + if (ase & ASE_MSA) + ext_ases |= AFL_ASE_MSA; + if (ase & ASE_XPA) + ext_ases |= AFL_ASE_XPA; + + return ext_ases; +} /* Some special processing for a MIPS ELF file. */ void mips_elf_final_processing (void) { + int fpabi; + Elf_Internal_ABIFlags_v0 flags; + + flags.version = 0; + flags.isa_rev = 0; + switch (file_mips_opts.isa) + { + case INSN_ISA1: + flags.isa_level = 1; + break; + case INSN_ISA2: + flags.isa_level = 2; + break; + case INSN_ISA3: + flags.isa_level = 3; + break; + case INSN_ISA4: + flags.isa_level = 4; + break; + case INSN_ISA5: + flags.isa_level = 5; + break; + case INSN_ISA32: + flags.isa_level = 32; + flags.isa_rev = 1; + break; + case INSN_ISA32R2: + flags.isa_level = 32; + flags.isa_rev = 2; + break; + case INSN_ISA32R3: + flags.isa_level = 32; + flags.isa_rev = 3; + break; + case INSN_ISA32R5: + flags.isa_level = 32; + flags.isa_rev = 5; + break; + case INSN_ISA64: + flags.isa_level = 64; + flags.isa_rev = 1; + break; + case INSN_ISA64R2: + flags.isa_level = 64; + flags.isa_rev = 2; + break; + case INSN_ISA64R3: + flags.isa_level = 64; + flags.isa_rev = 3; + break; + case INSN_ISA64R5: + flags.isa_level = 64; + flags.isa_rev = 5; + break; + } + + flags.gpr_size = file_mips_opts.gp == 32 ? AFL_REG_32 : AFL_REG_64; + flags.cpr1_size = file_mips_opts.soft_float ? AFL_REG_NONE + : (file_mips_opts.ase & ASE_MSA) ? AFL_REG_128 + : (file_mips_opts.fp == 64) ? AFL_REG_64 + : AFL_REG_32; + flags.cpr2_size = AFL_REG_NONE; + flags.fp_abi = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_GNU, + Tag_GNU_MIPS_ABI_FP); + flags.isa_ext = bfd_mips_isa_ext (stdoutput); + flags.ases = mips_convert_ase_flags (file_mips_opts.ase); + if (file_ase_mips16) + flags.ases |= AFL_ASE_MIPS16; + if (file_ase_micromips) + flags.ases |= AFL_ASE_MICROMIPS; + flags.flags1 = 0; + if ((ISA_HAS_ODD_SINGLE_FPR (file_mips_opts.isa, file_mips_opts.arch) + || file_mips_opts.fp == 64) + && file_mips_opts.oddspreg) + flags.flags1 |= AFL_FLAGS1_ODDSPREG; + flags.flags2 = 0; + + bfd_mips_elf_swap_abiflags_v0_out (stdoutput, &flags, + ((Elf_External_ABIFlags_v0 *) + mips_flags_frag)); + /* Write out the register information. */ if (mips_abi != N64_ABI) { @@ -17454,7 +17728,9 @@ mips_elf_final_processing (void) elf_elfheader (stdoutput)->e_flags |= EF_MIPS_NAN2008; /* 32 bit code with 64 bit FP registers. */ - if (file_mips_opts.fp == 64 && ABI_NEEDS_32BIT_REGS (mips_abi)) + fpabi = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_GNU, + Tag_GNU_MIPS_ABI_FP); + if (fpabi == Val_GNU_MIPS_ABI_FP_OLD_64) elf_elfheader (stdoutput)->e_flags |= EF_MIPS_FP64; } @@ -18402,10 +18678,56 @@ mips_convert_symbolic_attribute (const char *name) void md_mips_end (void) { + int fpabi = Val_GNU_MIPS_ABI_FP_ANY; + mips_emit_delays (); if (cur_proc_ptr) as_warn (_("missing .end at end of assembly")); /* Just in case no code was emitted, do the consistency check. */ file_mips_check_options (); + + /* Set a floating-point ABI if the user did not. */ + if (obj_elf_seen_attribute (OBJ_ATTR_GNU, Tag_GNU_MIPS_ABI_FP)) + { + /* Perform consistency checks on the floating-point ABI. */ + fpabi = bfd_elf_get_obj_attr_int (stdoutput, OBJ_ATTR_GNU, + Tag_GNU_MIPS_ABI_FP); + if (fpabi != Val_GNU_MIPS_ABI_FP_ANY) + check_fpabi (fpabi); + } + else + { + /* Soft-float gets precedence over single-float, the two options should + not be used together so this should not matter. */ + if (file_mips_opts.soft_float == 1) + fpabi = Val_GNU_MIPS_ABI_FP_SOFT; + /* Single-float gets precedence over all double_float cases. */ + else if (file_mips_opts.single_float == 1) + fpabi = Val_GNU_MIPS_ABI_FP_SINGLE; + else + { + switch (file_mips_opts.fp) + { + case 32: + if (file_mips_opts.gp == 32) + fpabi = Val_GNU_MIPS_ABI_FP_DOUBLE; + break; + case 0: + fpabi = Val_GNU_MIPS_ABI_FP_XX; + break; + case 64: + if (file_mips_opts.gp == 32 && !file_mips_opts.oddspreg) + fpabi = Val_GNU_MIPS_ABI_FP_64A; + else if (file_mips_opts.gp == 32) + fpabi = Val_GNU_MIPS_ABI_FP_64; + else + fpabi = Val_GNU_MIPS_ABI_FP_DOUBLE; + break; + } + } + + bfd_elf_add_obj_attr_int (stdoutput, OBJ_ATTR_GNU, + Tag_GNU_MIPS_ABI_FP, fpabi); + } } diff --git a/gas/doc/as.texinfo b/gas/doc/as.texinfo index 0f0956c..251b6d5 100644 --- a/gas/doc/as.texinfo +++ b/gas/doc/as.texinfo @@ -399,6 +399,8 @@ gcc(1), ld(1), and the Info entries for @file{binutils} and @file{ld}. [@b{-g}[@var{debug level}]] [@b{-G} @var{num}] [@b{-KPIC}] [@b{-call_shared}] [@b{-non_shared}] [@b{-xgot} [@b{-mvxworks-pic}] [@b{-mabi}=@var{ABI}] [@b{-32}] [@b{-n32}] [@b{-64}] [@b{-mfp32}] [@b{-mgp32}] + [@b{-mfp64}] [@b{-mgp64}] [@b{-mfpxx}] + [@b{-modd-spreg}] [@b{-mno-odd-spreg}] [@b{-march}=@var{CPU}] [@b{-mtune}=@var{CPU}] [@b{-mips1}] [@b{-mips2}] [@b{-mips3}] [@b{-mips4}] [@b{-mips5}] [@b{-mips32}] [@b{-mips32r2}] [@b{-mips32r3}] [@b{-mips32r5}] [@b{-mips64}] [@b{-mips64r2}] @@ -1321,6 +1323,25 @@ flags force a certain group of registers to be treated as 32 bits wide at all times. @samp{-mgp32} controls the size of general-purpose registers and @samp{-mfp32} controls the size of floating-point registers. +@item -mgp64 +@itemx -mfp64 +The register sizes are normally inferred from the ISA and ABI, but these +flags force a certain group of registers to be treated as 64 bits wide at +all times. @samp{-mgp64} controls the size of general-purpose registers +and @samp{-mfp64} controls the size of floating-point registers. + +@item -mfpxx +The register sizes are normally inferred from the ISA and ABI, but using +this flag in combination with @samp{-mabi=32} enables an ABI variant +which will operate correctly with floating-point registers which are +32 or 64 bits wide. + +@item -modd-spreg +@itemx -mno-odd-spreg +Enable use of floating-point operations on odd-numbered single-precision +registers when supported by the ISA. @samp{-mfpxx} implies +@samp{-mno-odd-spreg}, otherwise the default is @samp{-modd-spreg}. + @item -mips16 @itemx -no-mips16 Generate code for the MIPS 16 processor. This is equivalent to putting diff --git a/gas/doc/c-mips.texi b/gas/doc/c-mips.texi index d2795e7..1e52e09 100644 --- a/gas/doc/c-mips.texi +++ b/gas/doc/c-mips.texi @@ -28,6 +28,7 @@ Assembly Language Programming'' in the same work. * MIPS assembly options:: Directives to control code generation * MIPS autoextend:: Directives for extending MIPS 16 bit instructions * MIPS insn:: Directive to mark data as an instruction +* MIPS FP ABIs:: Marking which FP ABI is in use * MIPS NaN Encodings:: Directives to record which NaN encoding is being used * MIPS Option Stack:: Directives to save and restore options * MIPS ASE Instruction Generation Overrides:: Directives to control @@ -125,6 +126,22 @@ The @code{.set gp=64} and @code{.set fp=64} directives allow the size of registers to be changed for parts of an object. The default value is restored by @code{.set gp=default} and @code{.set fp=default}. +@item -mfpxx +Make no assumptions about whether 32-bit or 64-bit floating-point +registers are available. This is provided to support having modules +compatible with either @samp{-mfp32} or @samp{-mfp64}. This option can +only be used with MIPS II and above. + +The @code{.set fp=xx} directive allows a part of an object to be marked +as not making assumptions about 32-bit or 64-bit FP registers. The +default value is restored by @code{.set fp=default}. + +@item -modd-spreg +@itemx -mno-odd-spreg +Enable use of floating-point operations on odd-numbered single-precision +registers when supported by the ISA. @samp{-mfpxx} implies +@samp{-mno-odd-spreg}, otherwise the default is @samp{-modd-spreg} + @item -mips16 @itemx -no-mips16 Generate code for the MIPS 16 processor. This is equivalent to putting @@ -769,6 +786,115 @@ baz: @end example +@node MIPS FP ABIs +@section Directives to control the FP ABI +@menu +* MIPS FP ABI History:: History of FP ABIs +* MIPS FP ABI Variants:: Supported FP ABIs +* MIPS FP ABI Selection:: Automatic selection of FP ABI +* MIPS FP ABI Compatibility:: Linking different FP ABI variants +@end menu + +@node MIPS FP ABI History +@subsection History of FP ABIs +@cindex @code{.gnu_attribute 4, @var{n}} directive, MIPS +@cindex @code{.gnu_attribute Tag_GNU_MIPS_ABI_FP, @var{n}} directive, MIPS +The MIPS ABIs support a variety of different floating-point extensions +where calling-convention and register sizes vary for floating-point data. +The extensions exist to support a wide variety of optional architecture +features. The resulting ABI variants are generally incompatible with each +other and must be tracked carefully. + +Traditionally the use of an explicit @code{.gnu_attribute 4, @var{n}} +directive is used to indicate which ABI is in use by a specific module. +It was then left to the user to ensure that command line options and the +selected ABI were compatible with some potential for inconsistencies. + +@node MIPS FP ABI Variants +@subsection Supported FP ABIs +The supported floating-point ABI variants are: + +@table @code +@item 0 - No floating-point +This variant is used to indicate that floating-point is not used within +the module at all and therefore has no impact on the ABI. This is the +default. + +@item 1 - Double-precision +This variant indicates that double-precision support is used. For 64-bit +ABIs this means that 64-bit wide floating-point registers are required. +For 32-bit ABIs this means that 32-bit wide floating-point registers are +required and double-precision operations use pairs of registers. + +@item 2 - Single-precision +This variant indicates that single-precision support is used. Double +precision operations will be supported via soft-float routines. + +@item 3 - Soft-float +This variant indicates that although floating-point support is used all +operations are emulated in software. This means the ABI is modified to +pass all floating-point data in general-purpose registers. + +@item 4 - Deprecated +This variant existed as an initial attempt at supporting 64-bit wide +floating-point registers for O32 ABI on a MIPS32r2 cpu. This has been +superceded by @value{5}, @value{6} and @value{7}. + +@item 5 - Double-precision 32-bit CPU, 32-bit or 64-bit FPU +This variant is used by 32-bit ABIs to indicate that the floating-point +code in the module has been designed to operate correctly with either +32-bit wide or 64-bit wide floating-point registers. Double-precision +support is used. Only O32 currently supports this variant and requires +a minimum architecture of MIPS II. + +@item 6 - Double-precision 32-bit FPU, 64-bit FPU +This variant is used by 32-bit ABIs to indicate that the floating-point +code in the module requires 64-bit wide floating-point registers. +Double-precision support is used. Only O32 currently supports this +variant and requires a minimum architecture of MIPS32r2. + +@item 7 - Double-precision compat 32-bit FPU, 64-bit FPU +This variant is used by 32-bit ABIs to indicate that the floating-point +code in the module requires 64-bit wide floating-point registers. +Double-precision support is used. This differs from the previous ABI +as it restricts use of odd-numbered single-precision registers. Only +O32 currently supports this variant and requires a minimum architecture +of MIPS32r2. +@end table + +@node MIPS FP ABI Selection +@subsection Automatic selection of FP ABI +@cindex @code{.module fp=@var{nn}} directive, MIPS +In order to simplify and add safety to the process of selecting the +correct floating-point ABI, the assembler will automatically infer the +correct @code{.gnu_attribute 4, @var{n}} directive based on command line +options and @code{.module} overrides. Where an explicit +@code{.gnu_attribute 4, @var{n}} directive has been seen then a warning +will be raised if it does not match an inferred setting. + +The floating-point ABI is inferred as follows. If @samp{-msoft-float} +has been used the module will be marked as soft-float. If +@samp{-msingle-float} has been used then the module will be marked as +single-precision. The remaining ABIs are then selected based +on the FP register width. Double-precision is selected if the width +of GP and FP registers match and the special double-precision variants +for 32-bit ABIs are then selected depending on @samp{-mfpxx}, +@samp{-mfp64} and @samp{-mno-odd-spreg}. + +@node MIPS FP ABI Compatibility +@subsection Linking different FP ABI variants +Modules using the default FP ABI (no floating-point) can be linked with +any other (singular) FP ABI variant. + +Special compatibility support exists for O32 with the four +double-precision FP ABI variants. The @samp{-mfpxx} FP ABI is specifically +designed to be compatible with the standard double-precision ABI and the +@samp{-mfp64} FP ABIs. This makes it desirable for O32 modules to be +built as @samp{-mfpxx} to ensure the maximum compatibility with other +modules produced for more specific needs. The only FP ABIs which cannot +be linked together are the standard double-precision ABI and the full +@samp{-mfp64} ABI with @samp{-modd-spreg}. + @node MIPS NaN Encodings @section Directives to record which NaN encoding is being used diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog index 93ee465..9d93224 100644 --- a/gas/testsuite/ChangeLog +++ b/gas/testsuite/ChangeLog @@ -1,3 +1,127 @@ +2014-07-29 Matthew Fortune <matthew.fortune@imgtec.com> + + * gas/mips/attr-gnu-4-0.d: New. + * gas/mips/attr-gnu-4-0.s: Likewise. + * gas/mips/attr-gnu-4-1-mfp32.l: Likewise. + * gas/mips/attr-gnu-4-1-mfp32.s: Likewise. + * gas/mips/attr-gnu-4-1-mfp64.l: Likewise. + * gas/mips/attr-gnu-4-1-mfp64.s: Likewise. + * gas/mips/attr-gnu-4-1-mfpxx.s: Likewise. + * gas/mips/attr-gnu-4-1-msingle-float.l: Likewise. + * gas/mips/attr-gnu-4-1-msingle-float.s: Likewise. + * gas/mips/attr-gnu-4-1-msoft-float.l: Likewise. + * gas/mips/attr-gnu-4-1-msoft-float.s: Likewise. + * gas/mips/attr-gnu-4-1.d: Likewise. + * gas/mips/attr-gnu-4-1.s: Likewise. + * gas/mips/attr-gnu-4-2-mdouble-float.l: Likewise. + * gas/mips/attr-gnu-4-2-mdouble-float.s: Likewise. + * gas/mips/attr-gnu-4-2-msoft-float.l: Likewise. + * gas/mips/attr-gnu-4-2-msoft-float.s: Likewise. + * gas/mips/attr-gnu-4-2.d: Likewise. + * gas/mips/attr-gnu-4-2.s: Likewise. + * gas/mips/attr-gnu-4-3-mhard-float.l: Likewise. + * gas/mips/attr-gnu-4-3-mhard-float.s: Likewise. + * gas/mips/attr-gnu-4-3.d: Likewise. + * gas/mips/attr-gnu-4-3.s: Likewise. + * gas/mips/attr-gnu-4-4.l: Likewise. + * gas/mips/attr-gnu-4-4.s: Likewise. + * gas/mips/attr-gnu-4-5-64.l: Likewise. + * gas/mips/attr-gnu-4-5-64.s: Likewise. + * gas/mips/attr-gnu-4-5.d: Likewise. + * gas/mips/attr-gnu-4-5.l: Likewise. + * gas/mips/attr-gnu-4-5.s: Likewise. + * gas/mips/attr-gnu-4-6-64.l: Likewise. + * gas/mips/attr-gnu-4-6-64.s: Likewise. + * gas/mips/attr-gnu-4-6.d: Likewise. + * gas/mips/attr-gnu-4-6.l: Likewise. + * gas/mips/attr-gnu-4-6.s: Likewise. + * gas/mips/attr-gnu-4-6-msingle-float.l: Likewise. + * gas/mips/attr-gnu-4-6-msingle-float.s: Likewise. + * gas/mips/attr-gnu-4-6-msoft-float.l: Likewise. + * gas/mips/attr-gnu-4-6-msoft-float.s: Likewise. + * gas/mips/attr-gnu-4-6-noodd.l: Likewise. + * gas/mips/attr-gnu-4-6-noodd.s: Likewise. + * gas/mips/attr-gnu-4-7-64.l: Likewise. + * gas/mips/attr-gnu-4-7-64.s: Likewise. + * gas/mips/attr-gnu-4-7-msingle-float.l: Likewise. + * gas/mips/attr-gnu-4-7-msingle-float.s: Likewise. + * gas/mips/attr-gnu-4-7-msoft-float.l: Likewise. + * gas/mips/attr-gnu-4-7-msoft-float.s: Likewise. + * gas/mips/attr-gnu-4-7-odd.l: Likewise. + * gas/mips/attr-gnu-4-7-odd.s: Likewise. + * gas/mips/attr-gnu-4-7.d: Likewise. + * gas/mips/attr-gnu-4-7.l: Likewise. + * gas/mips/attr-gnu-4-7.s: Likewise. + * gas/mips/attr-none-double.d: Likewise. + * gas/mips/attr-none-o32-fp64.d: Likewise. + * gas/mips/attr-none-o32-fp64-nooddspreg.d + * gas/mips/attr-none-o32-fpxx.d: Likewise. + * gas/mips/attr-none-single-float.d: Likewise. + * gas/mips/attr-none-soft-float.d: Likewise. + * gas/mips/elf_arch_mips32r3.d: Likewise. + * gas/mips/elf_arch_mips32r5.d: Likewise. + * gas/mips/elf_arch_mips64r3.d: Likewise. + * gas/mips/elf_arch_mips64r5.d: Likewise. + * gas/mips/li-d.d: Likewise. + * gas/mips/li-d.s: Likewise. + * gas/mips/module-check-warn.l: Likewise. + * gas/mips/module-check-warn.s: Likewise. + * gas/mips/module-check.d: Likewise. + * gas/mips/module-check.s: Likewise. + * gas/mips/module-mfp32.d: Likewise. + * gas/mips/module-mfp32.s: Likewise. + * gas/mips/module-mfp64.d: Likewise. + * gas/mips/module-mfp64.s: Likewise. + * gas/mips/module-mfp64-noodd.d: Likewise. + * gas/mips/module-mfp64-noodd.s: Likewise. + * gas/mips/module-mfpxx.d: Likewise. + * gas/mips/module-mfpxx.s: Likewise. + * gas/mips/module-msingle-float.d: Likewise. + * gas/mips/module-msingle-float.s: Likewise. + * gas/mips/module-msoft-float.d: Likewise. + * gas/mips/module-msoft-float.s: Likewise. + * gas/mips/module-set-mfpxx.d: Likewise. + * gas/mips/module-set-mfpxx.s: Likewise. + * gas/mips/fpxx-oddfpreg.d: Likewise. + * gas/mips/fpxx-oddfpreg.l: Likewise. + * gas/mips/fpxx-oddfpreg.s: Likewise. + * gas/mips/no-odd-spreg.d: Likewise. + * gas/mips/odd-spreg.d: Likewise. + * gas/elf/section2.e-mips: Adjust expected output. + * gas/mips/attr-gnu-abi-fp-1.d: Likewise. + * gas/mips/attr-gnu-abi-msa-1.d: Likewise. + * gas/mips/call-nonpic-1.d: Likewise. + * gas/mips/elf_arch_mips1.d: Likewise. + * gas/mips/elf_arch_mips2.d: Likewise. + * gas/mips/elf_arch_mips3.d: Likewise. + * gas/mips/elf_arch_mips32.d: Likewise. + * gas/mips/elf_arch_mips32r2.d: Likewise. + * gas/mips/elf_arch_mips4.d: Likewise. + * gas/mips/elf_arch_mips5.d: Likewise. + * gas/mips/elf_arch_mips64.d: Likewise. + * gas/mips/elf_arch_mips64r2.d: Likewise. + * gas/mips/elf_ase_micromips-2.d: Likewise. + * gas/mips/elf_ase_micromips.d: Likewise. + * gas/mips/elf_ase_mips16-2.d: Likewise. + * gas/mips/elf_ase_mips16.d: Likewise. + * gas/mips/module-defer-warn1.d: Likewise. + * gas/mips/module-override.d: Likewise. + * gas/mips/n32-consec.d: Likewise. + * gas/mips/nan-2008-1.d: Likewise. + * gas/mips/nan-2008-2.d: Likewise. + * gas/mips/nan-2008-3.d: Likewise. + * gas/mips/nan-2008-4.d: Likewise. + * gas/mips/nan-legacy-1.d: Likewise. + * gas/mips/nan-legacy-2.d: Likewise. + * gas/mips/nan-legacy-3.d: Likewise. + * gas/mips/nan-legacy-4.d: Likewise. + * gas/mips/nan-legacy-5.d: Likewise. + * gas/mips/tmips16-e.d: Likewise. + * gas/mips/tmips16-f.d: Likewise. + * gas/mips/tmipsel16-e.d: Likewise. + * gas/mips/tmipsel16-f.d: Likewise. + * gas/testsuite/gas/mips/mips.exp: Add new tests. + 2014-07-22 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> diff --git a/gas/testsuite/gas/elf/section2.e-mips b/gas/testsuite/gas/elf/section2.e-mips index 9e70f5c..e7588cf 100644 --- a/gas/testsuite/gas/elf/section2.e-mips +++ b/gas/testsuite/gas/elf/section2.e-mips @@ -1,10 +1,12 @@ -Symbol table '.symtab' contains 7 entries: +Symbol table '.symtab' contains 9 entries: +Num: +Value +Size +Type +Bind +Vis +Ndx +Name +0: 0+0 +0 +NOTYPE +LOCAL +DEFAULT +UND +1: 0+0 +0 +SECTION +LOCAL +DEFAULT +1 (|\.text) +2: 0+0 +0 +SECTION +LOCAL +DEFAULT +2 (|\.data) +3: 0+0 +0 +SECTION +LOCAL +DEFAULT +3 (|\.bss) - +4: 0+0 +0 +SECTION +LOCAL +DEFAULT +6 (|A) + +4: 0+0 +0 +SECTION +LOCAL +DEFAULT +7 (|A) +5: 0+0 +0 +SECTION +LOCAL +DEFAULT +4 (|\.reginfo) - +6: 0+0 +0 +SECTION +LOCAL +DEFAULT +5 (|\.pdr) + +6: 0+0 +0 +SECTION +LOCAL +DEFAULT +5 (|\.MIPS\.abiflags) + +7: 0+0 +0 +SECTION +LOCAL +DEFAULT +6 (|\.pdr) + +8: 0+0 +0 +SECTION +LOCAL +DEFAULT +8 (|\.gnu\.attributes) diff --git a/gas/testsuite/gas/mips/attr-gnu-4-0.d b/gas/testsuite/gas/mips/attr-gnu-4-0.d new file mode 100644 index 0000000..7728079 --- /dev/null +++ b/gas/testsuite/gas/mips/attr-gnu-4-0.d @@ -0,0 +1,17 @@ +#PROG: readelf +#readelf: -A +#name: MIPS gnu_attribute 4,0 + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Hard or soft float +ISA Extension: .* +ASEs: +#... +FLAGS 1: 0000000. +FLAGS 2: 00000000 + diff --git a/gas/testsuite/gas/mips/attr-gnu-4-0.s b/gas/testsuite/gas/mips/attr-gnu-4-0.s new file mode 100644 index 0000000..a143746 --- /dev/null +++ b/gas/testsuite/gas/mips/attr-gnu-4-0.s @@ -0,0 +1 @@ +.gnu_attribute 4,0 diff --git a/gas/testsuite/gas/mips/attr-gnu-4-1-mfp32.l b/gas/testsuite/gas/mips/attr-gnu-4-1-mfp32.l new file mode 100644 index 0000000..96db3ce --- /dev/null +++ b/gas/testsuite/gas/mips/attr-gnu-4-1-mfp32.l @@ -0,0 +1,3 @@ +.*: Assembler messages: +.*: Warning: `fp=32' used with a 64-bit ABI +.*: Warning: .gnu_attribute 4,1 is incompatible with `gp=64 fp=32' diff --git a/gas/testsuite/gas/mips/attr-gnu-4-1-mfp32.s b/gas/testsuite/gas/mips/attr-gnu-4-1-mfp32.s new file mode 100644 index 0000000..e985a56 --- /dev/null +++ b/gas/testsuite/gas/mips/attr-gnu-4-1-mfp32.s @@ -0,0 +1 @@ +.gnu_attribute 4,1 diff --git a/gas/testsuite/gas/mips/attr-gnu-4-1-mfp64.l b/gas/testsuite/gas/mips/attr-gnu-4-1-mfp64.l new file mode 100644 index 0000000..78b5fc4 --- /dev/null +++ b/gas/testsuite/gas/mips/attr-gnu-4-1-mfp64.l @@ -0,0 +1,2 @@ +.*: Assembler messages: +.*: Warning: .gnu_attribute 4,1 is incompatible with `gp=32 fp=64' diff --git a/gas/testsuite/gas/mips/attr-gnu-4-1-mfp64.s b/gas/testsuite/gas/mips/attr-gnu-4-1-mfp64.s new file mode 100644 index 0000000..e985a56 --- /dev/null +++ b/gas/testsuite/gas/mips/attr-gnu-4-1-mfp64.s @@ -0,0 +1 @@ +.gnu_attribute 4,1 diff --git a/gas/testsuite/gas/mips/attr-gnu-4-1-mfpxx.s b/gas/testsuite/gas/mips/attr-gnu-4-1-mfpxx.s new file mode 100644 index 0000000..e985a56 --- /dev/null +++ b/gas/testsuite/gas/mips/attr-gnu-4-1-mfpxx.s @@ -0,0 +1 @@ +.gnu_attribute 4,1 diff --git a/gas/testsuite/gas/mips/attr-gnu-4-1-msingle-float.l b/gas/testsuite/gas/mips/attr-gnu-4-1-msingle-float.l new file mode 100644 index 0000000..c37c520 --- /dev/null +++ b/gas/testsuite/gas/mips/attr-gnu-4-1-msingle-float.l @@ -0,0 +1,2 @@ +.*: Assembler messages: +.*: Warning: .gnu_attribute 4,1 is incompatible with `singlefloat' diff --git a/gas/testsuite/gas/mips/attr-gnu-4-1-msingle-float.s b/gas/testsuite/gas/mips/attr-gnu-4-1-msingle-float.s new file mode 100644 index 0000000..e985a56 --- /dev/null +++ b/gas/testsuite/gas/mips/attr-gnu-4-1-msingle-float.s @@ -0,0 +1 @@ +.gnu_attribute 4,1 diff --git a/gas/testsuite/gas/mips/attr-gnu-4-1-msoft-float.l b/gas/testsuite/gas/mips/attr-gnu-4-1-msoft-float.l new file mode 100644 index 0000000..819abfa --- /dev/null +++ b/gas/testsuite/gas/mips/attr-gnu-4-1-msoft-float.l @@ -0,0 +1,2 @@ +.*: Assembler messages: +.*: Warning: .gnu_attribute 4,1 is incompatible with `softfloat' diff --git a/gas/testsuite/gas/mips/attr-gnu-4-1-msoft-float.s b/gas/testsuite/gas/mips/attr-gnu-4-1-msoft-float.s new file mode 100644 index 0000000..e985a56 --- /dev/null +++ b/gas/testsuite/gas/mips/attr-gnu-4-1-msoft-float.s @@ -0,0 +1 @@ +.gnu_attribute 4,1 diff --git a/gas/testsuite/gas/mips/attr-gnu-4-1.d b/gas/testsuite/gas/mips/attr-gnu-4-1.d new file mode 100644 index 0000000..ee1bc49 --- /dev/null +++ b/gas/testsuite/gas/mips/attr-gnu-4-1.d @@ -0,0 +1,22 @@ +#source: attr-gnu-4-1.s +#PROG: readelf +#readelf: -A +#name: MIPS gnu_attribute 4,1 (double precision) + +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float \(double precision\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Hard float \(double precision\) +ISA Extension: .* +ASEs: +#... +FLAGS 1: 0000000. +FLAGS 2: 00000000 + diff --git a/gas/testsuite/gas/mips/attr-gnu-4-1.s b/gas/testsuite/gas/mips/attr-gnu-4-1.s new file mode 100644 index 0000000..e985a56 --- /dev/null +++ b/gas/testsuite/gas/mips/attr-gnu-4-1.s @@ -0,0 +1 @@ +.gnu_attribute 4,1 diff --git a/gas/testsuite/gas/mips/attr-gnu-4-2-mdouble-float.l b/gas/testsuite/gas/mips/attr-gnu-4-2-mdouble-float.l new file mode 100644 index 0000000..b138323 --- /dev/null +++ b/gas/testsuite/gas/mips/attr-gnu-4-2-mdouble-float.l @@ -0,0 +1,2 @@ +.*: Assembler messages: +.*: Warning: .gnu_attribute 4,2 requires `singlefloat' diff --git a/gas/testsuite/gas/mips/attr-gnu-4-2-mdouble-float.s b/gas/testsuite/gas/mips/attr-gnu-4-2-mdouble-float.s new file mode 100644 index 0000000..54ebf4e --- /dev/null +++ b/gas/testsuite/gas/mips/attr-gnu-4-2-mdouble-float.s @@ -0,0 +1 @@ +.gnu_attribute 4,2 diff --git a/gas/testsuite/gas/mips/attr-gnu-4-2-msoft-float.l b/gas/testsuite/gas/mips/attr-gnu-4-2-msoft-float.l new file mode 100644 index 0000000..9d421bd --- /dev/null +++ b/gas/testsuite/gas/mips/attr-gnu-4-2-msoft-float.l @@ -0,0 +1,2 @@ +.*: Assembler messages: +.*: Warning: .gnu_attribute 4,2 is incompatible with `softfloat' diff --git a/gas/testsuite/gas/mips/attr-gnu-4-2-msoft-float.s b/gas/testsuite/gas/mips/attr-gnu-4-2-msoft-float.s new file mode 100644 index 0000000..54ebf4e --- /dev/null +++ b/gas/testsuite/gas/mips/attr-gnu-4-2-msoft-float.s @@ -0,0 +1 @@ +.gnu_attribute 4,2 diff --git a/gas/testsuite/gas/mips/attr-gnu-4-2.d b/gas/testsuite/gas/mips/attr-gnu-4-2.d new file mode 100644 index 0000000..eb06a1f --- /dev/null +++ b/gas/testsuite/gas/mips/attr-gnu-4-2.d @@ -0,0 +1,23 @@ +#source: attr-gnu-4-2.s +#as: -msingle-float +#PROG: readelf +#readelf: -A +#name: MIPS gnu_attribute 4,2 (single precision) + +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float \(single precision\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Hard float \(single precision\) +ISA Extension: .* +ASEs: +#... +FLAGS 1: 0000000. +FLAGS 2: 00000000 + diff --git a/gas/testsuite/gas/mips/attr-gnu-4-2.s b/gas/testsuite/gas/mips/attr-gnu-4-2.s new file mode 100644 index 0000000..54ebf4e --- /dev/null +++ b/gas/testsuite/gas/mips/attr-gnu-4-2.s @@ -0,0 +1 @@ +.gnu_attribute 4,2 diff --git a/gas/testsuite/gas/mips/attr-gnu-4-3-mhard-float.l b/gas/testsuite/gas/mips/attr-gnu-4-3-mhard-float.l new file mode 100644 index 0000000..21b1039 --- /dev/null +++ b/gas/testsuite/gas/mips/attr-gnu-4-3-mhard-float.l @@ -0,0 +1,2 @@ +.*: Assembler messages: +.*: Warning: .gnu_attribute 4,3 requires `softfloat' diff --git a/gas/testsuite/gas/mips/attr-gnu-4-3-mhard-float.s b/gas/testsuite/gas/mips/attr-gnu-4-3-mhard-float.s new file mode 100644 index 0000000..32e5f5d --- /dev/null +++ b/gas/testsuite/gas/mips/attr-gnu-4-3-mhard-float.s @@ -0,0 +1 @@ +.gnu_attribute 4,3 diff --git a/gas/testsuite/gas/mips/attr-gnu-4-3.d b/gas/testsuite/gas/mips/attr-gnu-4-3.d new file mode 100644 index 0000000..ed0be23 --- /dev/null +++ b/gas/testsuite/gas/mips/attr-gnu-4-3.d @@ -0,0 +1,23 @@ +#as: -msoft-float +#source: attr-gnu-4-3.s +#PROG: readelf +#readelf: -A +#name: MIPS gnu_attribute 4,3 (-msoft-float) + +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Soft float + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Soft float +ISA Extension: .* +ASEs: +#... +FLAGS 1: 0000000. +FLAGS 2: 00000000 + diff --git a/gas/testsuite/gas/mips/attr-gnu-4-3.s b/gas/testsuite/gas/mips/attr-gnu-4-3.s new file mode 100644 index 0000000..32e5f5d --- /dev/null +++ b/gas/testsuite/gas/mips/attr-gnu-4-3.s @@ -0,0 +1 @@ +.gnu_attribute 4,3 diff --git a/gas/testsuite/gas/mips/attr-gnu-4-4.l b/gas/testsuite/gas/mips/attr-gnu-4-4.l new file mode 100644 index 0000000..c7d611d --- /dev/null +++ b/gas/testsuite/gas/mips/attr-gnu-4-4.l @@ -0,0 +1,2 @@ +.*: Assembler messages: +.*: Warning: .gnu_attribute 4,4 is no longer supported diff --git a/gas/testsuite/gas/mips/attr-gnu-4-4.s b/gas/testsuite/gas/mips/attr-gnu-4-4.s new file mode 100644 index 0000000..3ff129a --- /dev/null +++ b/gas/testsuite/gas/mips/attr-gnu-4-4.s @@ -0,0 +1 @@ +.gnu_attribute 4,4 diff --git a/gas/testsuite/gas/mips/attr-gnu-4-5-64.l b/gas/testsuite/gas/mips/attr-gnu-4-5-64.l new file mode 100644 index 0000000..26c187b --- /dev/null +++ b/gas/testsuite/gas/mips/attr-gnu-4-5-64.l @@ -0,0 +1,2 @@ +.*: Assembler messages: +.*: Warning: .gnu_attribute 4,5 requires `-mabi=32' diff --git a/gas/testsuite/gas/mips/attr-gnu-4-5-64.s b/gas/testsuite/gas/mips/attr-gnu-4-5-64.s new file mode 100644 index 0000000..b21ec3b --- /dev/null +++ b/gas/testsuite/gas/mips/attr-gnu-4-5-64.s @@ -0,0 +1 @@ +.gnu_attribute 4,5 diff --git a/gas/testsuite/gas/mips/attr-gnu-4-5.d b/gas/testsuite/gas/mips/attr-gnu-4-5.d new file mode 100644 index 0000000..e6eb677 --- /dev/null +++ b/gas/testsuite/gas/mips/attr-gnu-4-5.d @@ -0,0 +1,23 @@ +#as: -32 -mfpxx +#source: attr-gnu-4-5.s +#PROG: readelf +#readelf: -A +#name: MIPS gnu_attribute 4,5 (-mfpxx) + +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float \(32-bit CPU, Any FPU\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: 32 +CPR1 size: 32 +CPR2 size: 0 +FP ABI: Hard float \(32-bit CPU, Any FPU\) +ISA Extension: .* +ASEs: + None +FLAGS 1: 0000000. +FLAGS 2: 00000000 + diff --git a/gas/testsuite/gas/mips/attr-gnu-4-5.l b/gas/testsuite/gas/mips/attr-gnu-4-5.l new file mode 100644 index 0000000..018d692 --- /dev/null +++ b/gas/testsuite/gas/mips/attr-gnu-4-5.l @@ -0,0 +1,2 @@ +.*: Assembler messages: +.*: Warning: .gnu_attribute 4,5 requires `fp=xx' diff --git a/gas/testsuite/gas/mips/attr-gnu-4-5.s b/gas/testsuite/gas/mips/attr-gnu-4-5.s new file mode 100644 index 0000000..b21ec3b --- /dev/null +++ b/gas/testsuite/gas/mips/attr-gnu-4-5.s @@ -0,0 +1 @@ +.gnu_attribute 4,5 diff --git a/gas/testsuite/gas/mips/attr-gnu-4-6-64.l b/gas/testsuite/gas/mips/attr-gnu-4-6-64.l new file mode 100644 index 0000000..fa1764e --- /dev/null +++ b/gas/testsuite/gas/mips/attr-gnu-4-6-64.l @@ -0,0 +1,2 @@ +.*: Assembler messages: +.*: Warning: .gnu_attribute 4,6 requires `-mabi=32' diff --git a/gas/testsuite/gas/mips/attr-gnu-4-6-64.s b/gas/testsuite/gas/mips/attr-gnu-4-6-64.s new file mode 100644 index 0000000..96ace49 --- /dev/null +++ b/gas/testsuite/gas/mips/attr-gnu-4-6-64.s @@ -0,0 +1 @@ +.gnu_attribute 4,6 diff --git a/gas/testsuite/gas/mips/attr-gnu-4-6-msingle-float.l b/gas/testsuite/gas/mips/attr-gnu-4-6-msingle-float.l new file mode 100644 index 0000000..999b5e2 --- /dev/null +++ b/gas/testsuite/gas/mips/attr-gnu-4-6-msingle-float.l @@ -0,0 +1,2 @@ +.*: Assembler messages: +.*: Warning: .gnu_attribute 4,6 is incompatible with `fp=32' diff --git a/gas/testsuite/gas/mips/attr-gnu-4-6-msingle-float.s b/gas/testsuite/gas/mips/attr-gnu-4-6-msingle-float.s new file mode 100644 index 0000000..96ace49 --- /dev/null +++ b/gas/testsuite/gas/mips/attr-gnu-4-6-msingle-float.s @@ -0,0 +1 @@ +.gnu_attribute 4,6 diff --git a/gas/testsuite/gas/mips/attr-gnu-4-6-msoft-float.l b/gas/testsuite/gas/mips/attr-gnu-4-6-msoft-float.l new file mode 100644 index 0000000..999b5e2 --- /dev/null +++ b/gas/testsuite/gas/mips/attr-gnu-4-6-msoft-float.l @@ -0,0 +1,2 @@ +.*: Assembler messages: +.*: Warning: .gnu_attribute 4,6 is incompatible with `fp=32' diff --git a/gas/testsuite/gas/mips/attr-gnu-4-6-msoft-float.s b/gas/testsuite/gas/mips/attr-gnu-4-6-msoft-float.s new file mode 100644 index 0000000..96ace49 --- /dev/null +++ b/gas/testsuite/gas/mips/attr-gnu-4-6-msoft-float.s @@ -0,0 +1 @@ +.gnu_attribute 4,6 diff --git a/gas/testsuite/gas/mips/attr-gnu-4-6-noodd.l b/gas/testsuite/gas/mips/attr-gnu-4-6-noodd.l new file mode 100644 index 0000000..e885317 --- /dev/null +++ b/gas/testsuite/gas/mips/attr-gnu-4-6-noodd.l @@ -0,0 +1,2 @@ +.*: Assembler messages: +.*: Warning: .gnu_attribute 4,6 is incompatible with `nooddspreg' diff --git a/gas/testsuite/gas/mips/attr-gnu-4-6-noodd.s b/gas/testsuite/gas/mips/attr-gnu-4-6-noodd.s new file mode 100644 index 0000000..96ace49 --- /dev/null +++ b/gas/testsuite/gas/mips/attr-gnu-4-6-noodd.s @@ -0,0 +1 @@ +.gnu_attribute 4,6 diff --git a/gas/testsuite/gas/mips/attr-gnu-4-6.d b/gas/testsuite/gas/mips/attr-gnu-4-6.d new file mode 100644 index 0000000..5df111f --- /dev/null +++ b/gas/testsuite/gas/mips/attr-gnu-4-6.d @@ -0,0 +1,23 @@ +#as: -32 +#source: attr-gnu-4-6.s +#PROG: readelf +#readelf: -A +#name: MIPS gnu_attribute 4,6 (-mfp64) + +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float \(32-bit CPU, 64-bit FPU\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: 32 +CPR1 size: .* +CPR2 size: 0 +FP ABI: Hard float \(32-bit CPU, 64-bit FPU\) +ISA Extension: .* +ASEs: + None +FLAGS 1: 00000001 +FLAGS 2: 00000000 + diff --git a/gas/testsuite/gas/mips/attr-gnu-4-6.l b/gas/testsuite/gas/mips/attr-gnu-4-6.l new file mode 100644 index 0000000..f8f1733 --- /dev/null +++ b/gas/testsuite/gas/mips/attr-gnu-4-6.l @@ -0,0 +1,2 @@ +.*: Assembler messages: +.*: Warning: .gnu_attribute 4,6 requires `fp=64' diff --git a/gas/testsuite/gas/mips/attr-gnu-4-6.s b/gas/testsuite/gas/mips/attr-gnu-4-6.s new file mode 100644 index 0000000..96ace49 --- /dev/null +++ b/gas/testsuite/gas/mips/attr-gnu-4-6.s @@ -0,0 +1 @@ +.gnu_attribute 4,6 diff --git a/gas/testsuite/gas/mips/attr-gnu-4-7-64.l b/gas/testsuite/gas/mips/attr-gnu-4-7-64.l new file mode 100644 index 0000000..53b914e --- /dev/null +++ b/gas/testsuite/gas/mips/attr-gnu-4-7-64.l @@ -0,0 +1,2 @@ +.*: Assembler messages: +.*: Warning: .gnu_attribute 4,7 requires `-mabi=32' diff --git a/gas/testsuite/gas/mips/attr-gnu-4-7-64.s b/gas/testsuite/gas/mips/attr-gnu-4-7-64.s new file mode 100644 index 0000000..0ab9aea --- /dev/null +++ b/gas/testsuite/gas/mips/attr-gnu-4-7-64.s @@ -0,0 +1 @@ +.gnu_attribute 4,7 diff --git a/gas/testsuite/gas/mips/attr-gnu-4-7-msingle-float.l b/gas/testsuite/gas/mips/attr-gnu-4-7-msingle-float.l new file mode 100644 index 0000000..999b5e2 --- /dev/null +++ b/gas/testsuite/gas/mips/attr-gnu-4-7-msingle-float.l @@ -0,0 +1,2 @@ +.*: Assembler messages: +.*: Warning: .gnu_attribute 4,6 is incompatible with `fp=32' diff --git a/gas/testsuite/gas/mips/attr-gnu-4-7-msingle-float.s b/gas/testsuite/gas/mips/attr-gnu-4-7-msingle-float.s new file mode 100644 index 0000000..96ace49 --- /dev/null +++ b/gas/testsuite/gas/mips/attr-gnu-4-7-msingle-float.s @@ -0,0 +1 @@ +.gnu_attribute 4,6 diff --git a/gas/testsuite/gas/mips/attr-gnu-4-7-msoft-float.l b/gas/testsuite/gas/mips/attr-gnu-4-7-msoft-float.l new file mode 100644 index 0000000..999b5e2 --- /dev/null +++ b/gas/testsuite/gas/mips/attr-gnu-4-7-msoft-float.l @@ -0,0 +1,2 @@ +.*: Assembler messages: +.*: Warning: .gnu_attribute 4,6 is incompatible with `fp=32' diff --git a/gas/testsuite/gas/mips/attr-gnu-4-7-msoft-float.s b/gas/testsuite/gas/mips/attr-gnu-4-7-msoft-float.s new file mode 100644 index 0000000..96ace49 --- /dev/null +++ b/gas/testsuite/gas/mips/attr-gnu-4-7-msoft-float.s @@ -0,0 +1 @@ +.gnu_attribute 4,6 diff --git a/gas/testsuite/gas/mips/attr-gnu-4-7-odd.l b/gas/testsuite/gas/mips/attr-gnu-4-7-odd.l new file mode 100644 index 0000000..cb4f739 --- /dev/null +++ b/gas/testsuite/gas/mips/attr-gnu-4-7-odd.l @@ -0,0 +1,2 @@ +.*: Assembler messages: +.*: Warning: .gnu_attribute 4,7 requires `nooddspreg' diff --git a/gas/testsuite/gas/mips/attr-gnu-4-7-odd.s b/gas/testsuite/gas/mips/attr-gnu-4-7-odd.s new file mode 100644 index 0000000..0ab9aea --- /dev/null +++ b/gas/testsuite/gas/mips/attr-gnu-4-7-odd.s @@ -0,0 +1 @@ +.gnu_attribute 4,7 diff --git a/gas/testsuite/gas/mips/attr-gnu-4-7.d b/gas/testsuite/gas/mips/attr-gnu-4-7.d new file mode 100644 index 0000000..b453218 --- /dev/null +++ b/gas/testsuite/gas/mips/attr-gnu-4-7.d @@ -0,0 +1,23 @@ +#as: -32 +#source: attr-gnu-4-7.s +#PROG: readelf +#readelf: -A +#name: MIPS gnu_attribute 4,7 (-mfp64 -mno-odd-spreg) + +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float compat \(32-bit CPU, 64-bit FPU\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: 32 +CPR1 size: .* +CPR2 size: 0 +FP ABI: Hard float compat \(32-bit CPU, 64-bit FPU\) +ISA Extension: .* +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 + diff --git a/gas/testsuite/gas/mips/attr-gnu-4-7.l b/gas/testsuite/gas/mips/attr-gnu-4-7.l new file mode 100644 index 0000000..e3abfb5 --- /dev/null +++ b/gas/testsuite/gas/mips/attr-gnu-4-7.l @@ -0,0 +1,2 @@ +.*: Assembler messages: +.*: Warning: .gnu_attribute 4,7 requires `fp=64' diff --git a/gas/testsuite/gas/mips/attr-gnu-4-7.s b/gas/testsuite/gas/mips/attr-gnu-4-7.s new file mode 100644 index 0000000..0ab9aea --- /dev/null +++ b/gas/testsuite/gas/mips/attr-gnu-4-7.s @@ -0,0 +1 @@ +.gnu_attribute 4,7 diff --git a/gas/testsuite/gas/mips/attr-gnu-abi-fp-1.d b/gas/testsuite/gas/mips/attr-gnu-abi-fp-1.d index 63eaf8d..ce5bbc2 100644 --- a/gas/testsuite/gas/mips/attr-gnu-abi-fp-1.d +++ b/gas/testsuite/gas/mips/attr-gnu-abi-fp-1.d @@ -6,3 +6,17 @@ Attribute Section: gnu File Attributes Tag_GNU_MIPS_ABI_FP: Hard float \(double precision\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS1 +GPR size: 32 +CPR1 size: 32 +CPR2 size: 0 +FP ABI: Hard float \(double precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 + diff --git a/gas/testsuite/gas/mips/attr-gnu-abi-msa-1.d b/gas/testsuite/gas/mips/attr-gnu-abi-msa-1.d index 4720029..97fc8bf 100644 --- a/gas/testsuite/gas/mips/attr-gnu-abi-msa-1.d +++ b/gas/testsuite/gas/mips/attr-gnu-abi-msa-1.d @@ -4,4 +4,7 @@ Attribute Section: gnu File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float \(double precision\) Tag_GNU_MIPS_ABI_MSA: 128-bit MSA + +#... diff --git a/gas/testsuite/gas/mips/attr-none-double.d b/gas/testsuite/gas/mips/attr-none-double.d new file mode 100644 index 0000000..639bb53 --- /dev/null +++ b/gas/testsuite/gas/mips/attr-none-double.d @@ -0,0 +1,22 @@ +#PROG: readelf +#source: empty.s +#readelf: -A +#name: MIPS infer fpabi (double-precision) + +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float \(double precision\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Hard float \(double precision\) +ISA Extension: .* +ASEs: +#... +FLAGS 1: 0000000. +FLAGS 2: 00000000 + diff --git a/gas/testsuite/gas/mips/attr-none-o32-fp64-nooddspreg.d b/gas/testsuite/gas/mips/attr-none-o32-fp64-nooddspreg.d new file mode 100644 index 0000000..d122268 --- /dev/null +++ b/gas/testsuite/gas/mips/attr-none-o32-fp64-nooddspreg.d @@ -0,0 +1,23 @@ +#as: -mfp64 -mno-odd-spreg -32 +#source: empty.s +#PROG: readelf +#readelf: -A +#name: MIPS infer fpabi (O32 fp64 nooddspreg) + +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float compat \(32-bit CPU, 64-bit FPU\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: 32 +CPR1 size: 64 +CPR2 size: 0 +FP ABI: Hard float compat \(32-bit CPU, 64-bit FPU\) +ISA Extension: .* +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 + diff --git a/gas/testsuite/gas/mips/attr-none-o32-fp64.d b/gas/testsuite/gas/mips/attr-none-o32-fp64.d new file mode 100644 index 0000000..1f5abd2 --- /dev/null +++ b/gas/testsuite/gas/mips/attr-none-o32-fp64.d @@ -0,0 +1,23 @@ +#as: -mfp64 -32 +#source: empty.s +#PROG: readelf +#readelf: -A +#name: MIPS infer fpabi (O32 fp64) + +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float \(32-bit CPU, 64-bit FPU\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: 32 +CPR1 size: 64 +CPR2 size: 0 +FP ABI: Hard float \(32-bit CPU, 64-bit FPU\) +ISA Extension: .* +ASEs: + None +FLAGS 1: 00000001 +FLAGS 2: 00000000 + diff --git a/gas/testsuite/gas/mips/attr-none-o32-fpxx.d b/gas/testsuite/gas/mips/attr-none-o32-fpxx.d new file mode 100644 index 0000000..1e440bd --- /dev/null +++ b/gas/testsuite/gas/mips/attr-none-o32-fpxx.d @@ -0,0 +1,23 @@ +#as: -mfpxx -32 +#source: empty.s +#PROG: readelf +#readelf: -A +#name: MIPS infer fpabi (O32 fpxx) + +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float \(32-bit CPU, Any FPU\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: 32 +CPR1 size: 32 +CPR2 size: 0 +FP ABI: Hard float \(32-bit CPU, Any FPU\) +ISA Extension: .* +ASEs: + None +FLAGS 1: 0000000. +FLAGS 2: 00000000 + diff --git a/gas/testsuite/gas/mips/attr-none-single-float.d b/gas/testsuite/gas/mips/attr-none-single-float.d new file mode 100644 index 0000000..9c03a51 --- /dev/null +++ b/gas/testsuite/gas/mips/attr-none-single-float.d @@ -0,0 +1,23 @@ +#as: -msingle-float +#PROG: readelf +#source: empty.s +#readelf: -A +#name: MIPS infer fpabi (single-precision) + +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float \(single precision\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Hard float \(single precision\) +ISA Extension: .* +ASEs: +#... +FLAGS 1: 0000000. +FLAGS 2: 00000000 + diff --git a/gas/testsuite/gas/mips/attr-none-soft-float.d b/gas/testsuite/gas/mips/attr-none-soft-float.d new file mode 100644 index 0000000..0b4cf7a --- /dev/null +++ b/gas/testsuite/gas/mips/attr-none-soft-float.d @@ -0,0 +1,23 @@ +#as: -msoft-float +#PROG: readelf +#source: empty.s +#readelf: -A +#name: MIPS infer fpabi (soft-precision) + +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Soft float + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: 0 +CPR2 size: 0 +FP ABI: Soft float +ISA Extension: .* +ASEs: +#... +FLAGS 1: 0000000. +FLAGS 2: 00000000 + diff --git a/gas/testsuite/gas/mips/call-nonpic-1.d b/gas/testsuite/gas/mips/call-nonpic-1.d index 61d2b09..cd1b442 100644 --- a/gas/testsuite/gas/mips/call-nonpic-1.d +++ b/gas/testsuite/gas/mips/call-nonpic-1.d @@ -4,6 +4,19 @@ .* private flags = 10001004: .* +MIPS ABI Flags Version: 0 + +ISA: MIPS2 +GPR size: 32 +CPR1 size: 32 +CPR2 size: 0 +FP ABI: Hard float \(double precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 + Disassembly of section \.text: diff --git a/gas/testsuite/gas/mips/elf_arch_mips1.d b/gas/testsuite/gas/mips/elf_arch_mips1.d index a7af692..3a3da16 100644 --- a/gas/testsuite/gas/mips/elf_arch_mips1.d +++ b/gas/testsuite/gas/mips/elf_arch_mips1.d @@ -8,3 +8,16 @@ # flags are _not_ 8 chars long. private flags = (.......|......|.....|....|...|..|.): .*\[mips1\].* +MIPS ABI Flags Version: 0 + +ISA: MIPS1 +GPR size: 32 +CPR1 size: 32 +CPR2 size: 0 +FP ABI: Hard float \(double precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 + diff --git a/gas/testsuite/gas/mips/elf_arch_mips2.d b/gas/testsuite/gas/mips/elf_arch_mips2.d index c2c0c54..db8baf5 100644 --- a/gas/testsuite/gas/mips/elf_arch_mips2.d +++ b/gas/testsuite/gas/mips/elf_arch_mips2.d @@ -6,3 +6,16 @@ .*:.*file format.*elf.*mips.* private flags = 1.......: .*\[mips2\].* +MIPS ABI Flags Version: 0 + +ISA: MIPS2 +GPR size: 32 +CPR1 size: 32 +CPR2 size: 0 +FP ABI: Hard float \(double precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 + diff --git a/gas/testsuite/gas/mips/elf_arch_mips3.d b/gas/testsuite/gas/mips/elf_arch_mips3.d index cf42635..1ff003c 100644 --- a/gas/testsuite/gas/mips/elf_arch_mips3.d +++ b/gas/testsuite/gas/mips/elf_arch_mips3.d @@ -6,3 +6,16 @@ .*:.*file format.*elf.*mips.* private flags = 2.......: .*\[mips3\].* +MIPS ABI Flags Version: 0 + +ISA: MIPS3 +GPR size: 32 +CPR1 size: 32 +CPR2 size: 0 +FP ABI: Hard float \(double precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 + diff --git a/gas/testsuite/gas/mips/elf_arch_mips32.d b/gas/testsuite/gas/mips/elf_arch_mips32.d index 0c4bc93..922e803 100644 --- a/gas/testsuite/gas/mips/elf_arch_mips32.d +++ b/gas/testsuite/gas/mips/elf_arch_mips32.d @@ -6,3 +6,16 @@ .*:.*file format.*elf.*mips.* private flags = 5.......: .*\[mips32\].* +MIPS ABI Flags Version: 0 + +ISA: MIPS32 +GPR size: 32 +CPR1 size: 32 +CPR2 size: 0 +FP ABI: Hard float \(double precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 0000000. +FLAGS 2: 00000000 + diff --git a/gas/testsuite/gas/mips/elf_arch_mips32r2.d b/gas/testsuite/gas/mips/elf_arch_mips32r2.d index b0044ba..aa30299 100644 --- a/gas/testsuite/gas/mips/elf_arch_mips32r2.d +++ b/gas/testsuite/gas/mips/elf_arch_mips32r2.d @@ -6,3 +6,16 @@ .*:.*file format.*elf.*mips.* private flags = 7.......: .*\[mips32r2\].* +MIPS ABI Flags Version: 0 + +ISA: MIPS32r2 +GPR size: 32 +CPR1 size: 32 +CPR2 size: 0 +FP ABI: Hard float \(double precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 0000000. +FLAGS 2: 00000000 + diff --git a/gas/testsuite/gas/mips/elf_arch_mips32r3.d b/gas/testsuite/gas/mips/elf_arch_mips32r3.d new file mode 100644 index 0000000..0b43353 --- /dev/null +++ b/gas/testsuite/gas/mips/elf_arch_mips32r3.d @@ -0,0 +1,21 @@ +# name: ELF MIPS32r3 markings +# source: empty.s +# objdump: -p +# as: -32 -march=mips32r3 + +.*:.*file format.*elf.*mips.* +private flags = 7.......: .*\[mips32r2\].* + +MIPS ABI Flags Version: 0 + +ISA: MIPS32r3 +GPR size: 32 +CPR1 size: 32 +CPR2 size: 0 +FP ABI: Hard float \(double precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 0000000. +FLAGS 2: 00000000 + diff --git a/gas/testsuite/gas/mips/elf_arch_mips32r5.d b/gas/testsuite/gas/mips/elf_arch_mips32r5.d new file mode 100644 index 0000000..1da7b13 --- /dev/null +++ b/gas/testsuite/gas/mips/elf_arch_mips32r5.d @@ -0,0 +1,21 @@ +# name: ELF MIPS32r5 markings +# source: empty.s +# objdump: -p +# as: -32 -march=mips32r5 + +.*:.*file format.*elf.*mips.* +private flags = 7.......: .*\[mips32r2\].* + +MIPS ABI Flags Version: 0 + +ISA: MIPS32r5 +GPR size: 32 +CPR1 size: 32 +CPR2 size: 0 +FP ABI: Hard float \(double precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 0000000. +FLAGS 2: 00000000 + diff --git a/gas/testsuite/gas/mips/elf_arch_mips4.d b/gas/testsuite/gas/mips/elf_arch_mips4.d index d465582..d550e14 100644 --- a/gas/testsuite/gas/mips/elf_arch_mips4.d +++ b/gas/testsuite/gas/mips/elf_arch_mips4.d @@ -6,3 +6,16 @@ .*:.*file format.*elf.*mips.* private flags = 3.......: .*\[mips4\].* +MIPS ABI Flags Version: 0 + +ISA: MIPS4 +GPR size: 32 +CPR1 size: 32 +CPR2 size: 0 +FP ABI: Hard float \(double precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 + diff --git a/gas/testsuite/gas/mips/elf_arch_mips5.d b/gas/testsuite/gas/mips/elf_arch_mips5.d index 39327ae..31a0f18 100644 --- a/gas/testsuite/gas/mips/elf_arch_mips5.d +++ b/gas/testsuite/gas/mips/elf_arch_mips5.d @@ -6,3 +6,16 @@ .*:.*file format.*elf.*mips.* private flags = 4.......: .*\[mips5\].* +MIPS ABI Flags Version: 0 + +ISA: MIPS5 +GPR size: 32 +CPR1 size: 32 +CPR2 size: 0 +FP ABI: Hard float \(double precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 + diff --git a/gas/testsuite/gas/mips/elf_arch_mips64.d b/gas/testsuite/gas/mips/elf_arch_mips64.d index c3aea0f..25277b3 100644 --- a/gas/testsuite/gas/mips/elf_arch_mips64.d +++ b/gas/testsuite/gas/mips/elf_arch_mips64.d @@ -6,3 +6,16 @@ .*:.*file format.*elf.*mips.* private flags = 6.......: .*\[mips64\].* +MIPS ABI Flags Version: 0 + +ISA: MIPS64 +GPR size: 32 +CPR1 size: 32 +CPR2 size: 0 +FP ABI: Hard float \(double precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 0000000. +FLAGS 2: 00000000 + diff --git a/gas/testsuite/gas/mips/elf_arch_mips64r2.d b/gas/testsuite/gas/mips/elf_arch_mips64r2.d index aa318ce..2f5063b 100644 --- a/gas/testsuite/gas/mips/elf_arch_mips64r2.d +++ b/gas/testsuite/gas/mips/elf_arch_mips64r2.d @@ -1,8 +1,21 @@ # name: ELF MIPS64r2 markings # source: empty.s # objdump: -p -# as: -march=mips64r2 +# as: -32 -march=mips64r2 .*:.*file format.*elf.*mips.* private flags = 8.......: .*\[mips64r2\].* +MIPS ABI Flags Version: 0 + +ISA: MIPS64r2 +GPR size: 32 +CPR1 size: 32 +CPR2 size: 0 +FP ABI: Hard float \(double precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 0000000. +FLAGS 2: 00000000 + diff --git a/gas/testsuite/gas/mips/elf_arch_mips64r3.d b/gas/testsuite/gas/mips/elf_arch_mips64r3.d new file mode 100644 index 0000000..5b74f2d --- /dev/null +++ b/gas/testsuite/gas/mips/elf_arch_mips64r3.d @@ -0,0 +1,21 @@ +# name: ELF MIPS64r3 markings +# source: empty.s +# objdump: -p +# as: -32 -march=mips64r3 + +.*:.*file format.*elf.*mips.* +private flags = 8.......: .*\[mips64r2\].* + +MIPS ABI Flags Version: 0 + +ISA: MIPS64r3 +GPR size: 32 +CPR1 size: 32 +CPR2 size: 0 +FP ABI: Hard float \(double precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 0000000. +FLAGS 2: 00000000 + diff --git a/gas/testsuite/gas/mips/elf_arch_mips64r5.d b/gas/testsuite/gas/mips/elf_arch_mips64r5.d new file mode 100644 index 0000000..da4ee31 --- /dev/null +++ b/gas/testsuite/gas/mips/elf_arch_mips64r5.d @@ -0,0 +1,21 @@ +# name: ELF MIPS64r5 markings +# source: empty.s +# objdump: -p +# as: -32 -march=mips64r5 + +.*:.*file format.*elf.*mips.* +private flags = 8.......: .*\[mips64r2\].* + +MIPS ABI Flags Version: 0 + +ISA: MIPS64r5 +GPR size: 32 +CPR1 size: 32 +CPR2 size: 0 +FP ABI: Hard float \(double precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 0000000. +FLAGS 2: 00000000 + diff --git a/gas/testsuite/gas/mips/elf_ase_micromips-2.d b/gas/testsuite/gas/mips/elf_ase_micromips-2.d index 28b7f81..e600880 100644 --- a/gas/testsuite/gas/mips/elf_ase_micromips-2.d +++ b/gas/testsuite/gas/mips/elf_ase_micromips-2.d @@ -6,3 +6,16 @@ .*:.*file format.*mips.* private flags = [0-9a-f]*[2367abef]......: .*[[,]micromips[],].* +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: 32 +CPR1 size: 32 +CPR2 size: 0 +FP ABI: Hard float \(double precision\) +ISA Extension: None +ASEs: + MICROMIPS ASE +FLAGS 1: 00000000 +FLAGS 2: 00000000 + diff --git a/gas/testsuite/gas/mips/elf_ase_micromips.d b/gas/testsuite/gas/mips/elf_ase_micromips.d index c748dfb..13bb65a 100644 --- a/gas/testsuite/gas/mips/elf_ase_micromips.d +++ b/gas/testsuite/gas/mips/elf_ase_micromips.d @@ -6,3 +6,16 @@ .*:.*file format.*mips.* !private flags = .*micromips.* +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: 32 +CPR1 size: 32 +CPR2 size: 0 +FP ABI: Hard float \(double precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 + diff --git a/gas/testsuite/gas/mips/elf_ase_mips16-2.d b/gas/testsuite/gas/mips/elf_ase_mips16-2.d index 89b28b0..afd923c 100644 --- a/gas/testsuite/gas/mips/elf_ase_mips16-2.d +++ b/gas/testsuite/gas/mips/elf_ase_mips16-2.d @@ -6,3 +6,16 @@ .*:.*file format.*mips.* private flags = [0-9a-f]*[4-7c-f]......: .*[[,]mips16[],].* +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: 32 +CPR1 size: 32 +CPR2 size: 0 +FP ABI: Hard float \(double precision\) +ISA Extension: None +ASEs: + MIPS16 ASE +FLAGS 1: 00000000 +FLAGS 2: 00000000 + diff --git a/gas/testsuite/gas/mips/elf_ase_mips16.d b/gas/testsuite/gas/mips/elf_ase_mips16.d index 89fbc5b..27135f1 100644 --- a/gas/testsuite/gas/mips/elf_ase_mips16.d +++ b/gas/testsuite/gas/mips/elf_ase_mips16.d @@ -6,3 +6,16 @@ .*:.*file format.*mips.* !private flags = .*mips16.* +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: 32 +CPR1 size: 32 +CPR2 size: 0 +FP ABI: Hard float \(double precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 + diff --git a/gas/testsuite/gas/mips/fpxx-oddfpreg.d b/gas/testsuite/gas/mips/fpxx-oddfpreg.d new file mode 100644 index 0000000..b1fdc06 --- /dev/null +++ b/gas/testsuite/gas/mips/fpxx-oddfpreg.d @@ -0,0 +1,12 @@ +#as: -32 -mfpxx -modd-spreg +#objdump: -d +#name: FPXX with odd-singles test +.*: file format .* + +Disassembly of section .text: + +[ 0-9a-f]+ <.text>: +[ 0-9a-f]+: 44840800 mtc1 a0,\$f1 +[ 0-9a-f]+: 44040800 mfc1 a0,\$f1 +[ 0-9a-f]+: c4610000 lwc1 \$f1,0\(v1\) +[ 0-9a-f]+: e4610000 swc1 \$f1,0\(v1\) diff --git a/gas/testsuite/gas/mips/fpxx-oddfpreg.l b/gas/testsuite/gas/mips/fpxx-oddfpreg.l new file mode 100644 index 0000000..f441b6f --- /dev/null +++ b/gas/testsuite/gas/mips/fpxx-oddfpreg.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*:1: Error: float register should be even, was 1 +.*:2: Error: float register should be even, was 1 +.*:3: Error: float register should be even, was 1 +.*:4: Error: float register should be even, was 1 diff --git a/gas/testsuite/gas/mips/fpxx-oddfpreg.s b/gas/testsuite/gas/mips/fpxx-oddfpreg.s new file mode 100644 index 0000000..2136619 --- /dev/null +++ b/gas/testsuite/gas/mips/fpxx-oddfpreg.s @@ -0,0 +1,4 @@ +mtc1 $4, $f1 +mfc1 $4, $f1 +lwc1 $f1, 0($3) +swc1 $f1, 0($3) diff --git a/gas/testsuite/gas/mips/li-d.d b/gas/testsuite/gas/mips/li-d.d new file mode 100644 index 0000000..ca24570 --- /dev/null +++ b/gas/testsuite/gas/mips/li-d.d @@ -0,0 +1,31 @@ +#objdump: -d --prefix-addresses +#as: -mips64r2 +#name: MIPS li.d +#source: li-d.s + +# Test the li.d macro. + +.*: +file format .*mips.* + +Disassembly of section \.text: +[0-9a-f]+ <[^>]*> li v(0|1),0 +[0-9a-f]+ <[^>]*> move v(1|0),zero +[0-9a-f]+ <[^>]*> li at,0 +[0-9a-f]+ <[^>]*> mtc1 at,\$f1 +[0-9a-f]+ <[^>]*> mtc1 zero,\$f0 +[0-9a-f]+ <[^>]*> li at,0 +[0-9a-f]+ <[^>]*> mtc1 at,\$f1 +[0-9a-f]+ <[^>]*> mtc1 zero,\$f0 +[0-9a-f]+ <[^>]*> ldc1 \$f0,0\(gp\) +[0-9a-f]+ <[^>]*> li at,0 +[0-9a-f]+ <[^>]*> mthc1 at,\$f0 +[0-9a-f]+ <[^>]*> mtc1 zero,\$f0 +[0-9a-f]+ <[^>]*> li at,0 +[0-9a-f]+ <[^>]*> mthc1 at,\$f0 +[0-9a-f]+ <[^>]*> mtc1 zero,\$f0 +[0-9a-f]+ <[^>]*> li at,0 +[0-9a-f]+ <[^>]*> mthc1 at,\$f0 +[0-9a-f]+ <[^>]*> mtc1 zero,\$f0 +[0-9a-f]+ <[^>]*> li at,0 +[0-9a-f]+ <[^>]*> dmtc1 at,\$f0 + \.\.\. diff --git a/gas/testsuite/gas/mips/li-d.s b/gas/testsuite/gas/mips/li-d.s new file mode 100644 index 0000000..8578097 --- /dev/null +++ b/gas/testsuite/gas/mips/li-d.s @@ -0,0 +1,24 @@ +# Source file used to test the li macro. + +foo: + .set mips1 + .set fp=32 + li.d $2, 0 + li.d $f0, 0 + .set mips2 + li.d $f0, 0 + .set fp=xx + li.d $f0, 0 + .set mips32r2 + .set fp=32 + li.d $f0, 0 + .set fp=xx + li.d $f0, 0 + .set fp=64 + li.d $f0, 0 + .set mips3 + li.d $f0, 0 + +# Force at least 8 (non-delay-slot) zero bytes, to make 'objdump' print ... + .align 2 + .space 8 diff --git a/gas/testsuite/gas/mips/micromips@mips1-fp.d b/gas/testsuite/gas/mips/micromips@mips1-fp.d index 60e605f..7cfb2d8 100644 --- a/gas/testsuite/gas/mips/micromips@mips1-fp.d +++ b/gas/testsuite/gas/mips/micromips@mips1-fp.d @@ -8,5 +8,5 @@ Disassembly of section \.text: [0-9a-f]+ <foo>: [0-9a-f ]+: 5482 0030 add\.s \$f0,\$f2,\$f4 -[0-9a-f ]+: 5440 103b cfc1 \$2,\$0 +[0-9a-f ]+: 5440 203b mfc1 \$2,\$f0 #pass diff --git a/gas/testsuite/gas/mips/mips.exp b/gas/testsuite/gas/mips/mips.exp index c3135ca..ed63cdc 100644 --- a/gas/testsuite/gas/mips/mips.exp +++ b/gas/testsuite/gas/mips/mips.exp @@ -86,6 +86,10 @@ # nollsc # The CPU doesn't support ll, sc, lld and scd instructions. # +# oddspreg +# The CPU has odd-numbered single-precision registers +# available and GAS enables use of them by default. +# # as_flags: The assembler flags used when assembling tests for this # architecture. # @@ -452,19 +456,19 @@ mips_arch_create r4000 64 mips3 {} \ { -march=r4000 -mtune=r4000 } { -mmips:4000 } mips_arch_create vr5400 64 mips4 { ror } \ { -march=vr5400 -mtune=vr5400 } { -mmips:5400 } -mips_arch_create sb1 64 mips64 { mips3d } \ +mips_arch_create sb1 64 mips64 { mips3d oddspreg } \ { -march=sb1 -mtune=sb1 } { -mmips:sb1 } \ { mipsisa64sb1-*-* mipsisa64sb1el-*-* } -mips_arch_create octeon 64 mips64r2 {} \ +mips_arch_create octeon 64 mips64r2 { oddspreg } \ { -march=octeon -mtune=octeon } { -mmips:octeon } \ { mips64octeon*-*-* } -mips_arch_create octeonp 64 octeon {} \ +mips_arch_create octeonp 64 octeon { oddspreg } \ { -march=octeon+ -mtune=octeon+ } { -mmips:octeon+ } \ { } -mips_arch_create octeon2 64 octeonp {} \ +mips_arch_create octeon2 64 octeonp { oddspreg } \ { -march=octeon2 -mtune=octeon2 } { -mmips:octeon2 } \ { } -mips_arch_create xlr 64 mips64 {} \ +mips_arch_create xlr 64 mips64 { oddspreg } \ { -march=xlr -mtune=xlr } { -mmips:xlr } mips_arch_create r5900 64 mips3 { gpr_ilocks singlefloat nollsc } \ { -march=r5900 -mtune=r5900 } { -mmips:5900 } \ @@ -824,8 +828,12 @@ if { [istarget mips*-*-vxworks*] } { run_dump_test "elf_arch_mips5" run_dump_test "elf_arch_mips32" run_dump_test "elf_arch_mips32r2" + run_dump_test "elf_arch_mips32r3" + run_dump_test "elf_arch_mips32r5" run_dump_test "elf_arch_mips64" run_dump_test "elf_arch_mips64r2" + run_dump_test "elf_arch_mips64r3" + run_dump_test "elf_arch_mips64r5" # Verify that ASE markings are handled properly. run_dump_test "elf_ase_mips16" @@ -1187,7 +1195,7 @@ if { [istarget mips*-*-vxworks*] } { run_dump_test_arches "msa-branch" [mips_arch_list_matching mips32r2] run_dump_test_arches "xpa" [mips_arch_list_matching mips32r2 !micromips] - run_dump_test_arches "r5" [mips_arch_list_matching mips32r5 !micromips] + run_dump_test_arches "r5" "-32" [mips_arch_list_matching mips32r5 !micromips] run_dump_test "pcrel-1" run_dump_test "pcrel-2" @@ -1198,10 +1206,192 @@ if { [istarget mips*-*-vxworks*] } { run_dump_test "pcrel-4-64" } + run_dump_test_arches "attr-gnu-4-0" "-32" \ + [mips_arch_list_matching mips1] + run_dump_test_arches "attr-gnu-4-0" "-64" \ + [mips_arch_list_matching mips3] + run_dump_test_arches "attr-gnu-4-0" "-mfp32 -32" \ + [mips_arch_list_matching mips1] + run_dump_test_arches "attr-gnu-4-0" "-mfpxx -32" \ + [mips_arch_list_matching mips2 !r5900] + run_dump_test_arches "attr-gnu-4-0" "-mfp64 -32" \ + [mips_arch_list_matching mips32r2] + run_dump_test_arches "attr-gnu-4-0" "-mfp64 -mno-odd-spreg -32" \ + [mips_arch_list_matching mips32r2] + run_dump_test_arches "attr-gnu-4-0" "-mfp64 -64" \ + [mips_arch_list_matching mips3] + run_dump_test_arches "attr-gnu-4-0" "-msingle-float -32" \ + [mips_arch_list_matching mips1] + run_dump_test_arches "attr-gnu-4-0" "-msingle-float -64" \ + [mips_arch_list_matching mips3] + run_dump_test_arches "attr-gnu-4-0" "-msoft-float -32" \ + [mips_arch_list_matching mips1] + run_dump_test_arches "attr-gnu-4-0" "-msoft-float -64" \ + [mips_arch_list_matching mips3] + run_dump_test_arches "attr-none-double" "-32" \ + [mips_arch_list_matching mips1] + run_dump_test_arches "attr-none-double" "-64" \ + [mips_arch_list_matching mips3] + run_dump_test_arches "attr-none-o32-fpxx" \ + [mips_arch_list_matching mips2 !r5900] + run_dump_test_arches "attr-none-o32-fp64" \ + [mips_arch_list_matching mips32r2] + run_dump_test_arches "attr-none-o32-fp64-nooddspreg" \ + [mips_arch_list_matching mips32r2] + run_dump_test_arches "attr-none-single-float" "-32" \ + [mips_arch_list_matching mips1] + run_dump_test_arches "attr-none-single-float" "-64" \ + [mips_arch_list_matching mips3] + run_dump_test_arches "attr-none-soft-float" "-32 -msoft-float" \ + [mips_arch_list_matching mips1] + run_dump_test_arches "attr-none-soft-float" "-64 -msoft-float" \ + [mips_arch_list_matching mips3] + + run_list_test_arches "attr-gnu-4-1-mfp64" \ + "-32 -mfp64 -mno-odd-spreg" \ + [mips_arch_list_matching mips32r2] + run_list_test_arches "attr-gnu-4-1-mfp64" "-32 -mfp64" \ + [mips_arch_list_matching mips32r2] + run_list_test_arches "attr-gnu-4-1-mfp32" "-64 -mfp32" \ + [mips_arch_list_matching mips3] + run_list_test_arches "attr-gnu-4-1-msingle-float" "-32 -msingle-float" \ + [mips_arch_list_matching mips1] + run_list_test_arches "attr-gnu-4-1-msoft-float" "-32 -msoft-float" \ + [mips_arch_list_matching mips1] + run_dump_test_arches "attr-gnu-4-1" "-32 -mfpxx" \ + [mips_arch_list_matching mips2 !r5900] + run_dump_test_arches "attr-gnu-4-1" "-32 -mfp32" \ + [mips_arch_list_matching mips1] + run_dump_test_arches "attr-gnu-4-1" "-64 -mfp64" \ + [mips_arch_list_matching mips3] + + run_list_test_arches "attr-gnu-4-2-mdouble-float" "-32 -mfp32" \ + [mips_arch_list_matching mips1] + run_list_test_arches "attr-gnu-4-2-mdouble-float" "-32 -mfpxx" \ + [mips_arch_list_matching mips2 !r5900] + run_list_test_arches "attr-gnu-4-2-mdouble-float" "-32 -mfp64" \ + [mips_arch_list_matching mips32r2] + run_list_test_arches "attr-gnu-4-2-mdouble-float" \ + "-32 -mfp64 -mno-odd-spreg" \ + [mips_arch_list_matching mips32r2] + run_list_test_arches "attr-gnu-4-2-mdouble-float" "-64 -mfp64" \ + [mips_arch_list_matching mips3] + run_list_test_arches "attr-gnu-4-2-msoft-float" "-32 -msoft-float" \ + [mips_arch_list_matching mips1] + run_dump_test_arches "attr-gnu-4-2" "-32" \ + [mips_arch_list_matching mips1] + run_dump_test_arches "attr-gnu-4-2" "-64" \ + [mips_arch_list_matching mips3] + + run_list_test_arches "attr-gnu-4-3-mhard-float" "-32 -mfp32" \ + [mips_arch_list_matching mips1] + run_list_test_arches "attr-gnu-4-3-mhard-float" "-32 -mfpxx" \ + [mips_arch_list_matching mips2 !r5900] + run_list_test_arches "attr-gnu-4-3-mhard-float" "-32 -mfp64" \ + [mips_arch_list_matching mips32r2] + run_list_test_arches "attr-gnu-4-3-mhard-float" \ + "-32 -mfp64 -mno-odd-spreg" \ + [mips_arch_list_matching mips32r2] + run_list_test_arches "attr-gnu-4-3-mhard-float" "-64 -mfp64" \ + [mips_arch_list_matching mips3] + run_list_test_arches "attr-gnu-4-3-mhard-float" "-32 -msingle-float" \ + [mips_arch_list_matching mips1] + run_dump_test_arches "attr-gnu-4-3" "-32" \ + [mips_arch_list_matching mips1] + run_dump_test_arches "attr-gnu-4-3" "-64" \ + [mips_arch_list_matching mips3] + + run_list_test_arches "attr-gnu-4-4" "-32 -mfp32" \ + [mips_arch_list_matching mips1] + run_list_test_arches "attr-gnu-4-4" "-32 -mfpxx" \ + [mips_arch_list_matching mips2 !r5900] + run_list_test_arches "attr-gnu-4-4" "-32 -mfp64" \ + [mips_arch_list_matching mips32r2] + run_list_test_arches "attr-gnu-4-4" "-32 -mfp64 -mno-odd-spreg" \ + [mips_arch_list_matching mips32r2] + run_list_test_arches "attr-gnu-4-4" "-64 -mfp64" \ + [mips_arch_list_matching mips3] + run_list_test_arches "attr-gnu-4-4" "-32 -msingle-float" \ + [mips_arch_list_matching mips1] + run_list_test_arches "attr-gnu-4-4" "-32 -msoft-float" \ + [mips_arch_list_matching mips1] + + run_list_test_arches "attr-gnu-4-5" "-32 -mfp32" \ + [mips_arch_list_matching mips1] + run_list_test_arches "attr-gnu-4-5" "-32 -mfp64" \ + [mips_arch_list_matching mips32r2] + run_list_test_arches "attr-gnu-4-5" "-32 -mfp64 -mno-odd-spreg" \ + [mips_arch_list_matching mips32r2] + run_list_test_arches "attr-gnu-4-5-64" "-64 -mfp64" \ + [mips_arch_list_matching mips3] + run_list_test_arches "attr-gnu-4-5" "-32 -msingle-float" \ + [mips_arch_list_matching mips1] + run_list_test_arches "attr-gnu-4-5" "-32 -msoft-float" \ + [mips_arch_list_matching mips1] + run_dump_test_arches "attr-gnu-4-5" \ + [mips_arch_list_matching mips2 !r5900] + + run_list_test_arches "attr-gnu-4-6" "-32 -mfp32" \ + [mips_arch_list_matching mips1] + run_list_test_arches "attr-gnu-4-6-noodd" "-32 -mfp64 -mno-odd-spreg" \ + [mips_arch_list_matching mips32r2] + run_list_test_arches "attr-gnu-4-6-64" "-64 -mfp64" \ + [mips_arch_list_matching mips3] + run_list_test_arches "attr-gnu-4-6" "-32 -msingle-float" \ + [mips_arch_list_matching mips1] + run_list_test_arches "attr-gnu-4-6" "-32 -msoft-float" \ + [mips_arch_list_matching mips1] + run_list_test_arches "attr-gnu-4-6" "-32 -mfpxx" \ + [mips_arch_list_matching mips2 !r5900] + run_dump_test_arches "attr-gnu-4-6" "-32 -mfp64" \ + [mips_arch_list_matching mips32r2] + + run_list_test_arches "attr-gnu-4-7" "-32 -mfp32" \ + [mips_arch_list_matching mips1] + run_list_test_arches "attr-gnu-4-7-odd" "-32 -mfp64" \ + [mips_arch_list_matching mips32r2] + run_list_test_arches "attr-gnu-4-7-64" "-64 -mfp64" \ + [mips_arch_list_matching mips3] + run_list_test_arches "attr-gnu-4-7" "-32 -msingle-float" \ + [mips_arch_list_matching mips1] + run_list_test_arches "attr-gnu-4-7" "-32 -msoft-float" \ + [mips_arch_list_matching mips1] + run_list_test_arches "attr-gnu-4-7" "-32 -mfpxx" \ + [mips_arch_list_matching mips2 !r5900] + run_dump_test_arches "attr-gnu-4-7" "-32 -mfp64 -mno-odd-spreg" \ + [mips_arch_list_matching mips32r2] + run_dump_test "attr-gnu-abi-fp-1" run_dump_test "attr-gnu-abi-msa-1" run_dump_test "module-override" run_dump_test "module-defer-warn1" - run_list_test "module-defer-warn2" -32 + run_list_test "module-defer-warn2" "-32" + + foreach testopt [list -mfp32 -mfpxx -mfp64 "-mfp64-noodd" \ + -msingle-float -msoft-float] { + foreach cmdopt [list -mfp32 -mfpxx -mfp64 "-mfp64 -mno-odd-spreg" \ + -msingle-float -msoft-float] { + run_dump_test "module${testopt}" \ + [list [list as $cmdopt] [list name ($cmdopt)]] + } + } + + run_dump_test "module-set-mfpxx" + run_list_test_arches "fpxx-oddfpreg" "-32 -mfpxx" \ + [mips_arch_list_matching mips2 !singlefloat] + run_list_test_arches "fpxx-oddfpreg" "-32 -mfpxx -mno-odd-spreg" \ + [mips_arch_list_matching mips2 !singlefloat] + run_dump_test_arches "fpxx-oddfpreg" \ + [mips_arch_list_matching oddspreg] + run_dump_test_arches "odd-spreg" "-mfp32" [mips_arch_list_matching oddspreg] + run_dump_test_arches "odd-spreg" "-mfpxx" [mips_arch_list_matching oddspreg] + run_dump_test_arches "odd-spreg" "-mfp64" [mips_arch_list_matching mips32r2] + run_dump_test_arches "no-odd-spreg" "-mfp32" [mips_arch_list_matching mips1] + run_dump_test_arches "no-odd-spreg" "-mfpxx" [mips_arch_list_matching mips2 !r5900] + run_dump_test_arches "no-odd-spreg" "-mfp64" [mips_arch_list_matching mips32r2] + run_dump_test "module-check" + run_list_test "module-check-warn" "-32" + + run_dump_test "li-d" } diff --git a/gas/testsuite/gas/mips/mips1-fp.d b/gas/testsuite/gas/mips/mips1-fp.d index 1ab89ca..2aa229b 100644 --- a/gas/testsuite/gas/mips/mips1-fp.d +++ b/gas/testsuite/gas/mips/mips1-fp.d @@ -8,5 +8,5 @@ Disassembly of section .text: [0-9a-f]+ <.*>: .*: 46041000 add.s \$f0,\$f2,\$f4 -.*: 44420000 cfc1 \$2,\$0 +.*: 44020000 mfc1 \$2,\$f0 #pass diff --git a/gas/testsuite/gas/mips/mips1-fp.l b/gas/testsuite/gas/mips/mips1-fp.l index 72ed043..7526e2f 100644 --- a/gas/testsuite/gas/mips/mips1-fp.l +++ b/gas/testsuite/gas/mips/mips1-fp.l @@ -1,3 +1,3 @@ .*: Assembler messages: .*:6: Error: opcode not supported on this processor: .* \(.*\) `add.s \$f0,\$f2,\$f4' -.*:7: Error: opcode not supported on this processor: .* \(.*\) `cfc1 \$2,\$0' +.*:7: Error: opcode not supported on this processor: .* \(.*\) `mfc1 \$2,\$f0' diff --git a/gas/testsuite/gas/mips/mips1-fp.s b/gas/testsuite/gas/mips/mips1-fp.s index 0c71761..5509ddb 100644 --- a/gas/testsuite/gas/mips/mips1-fp.s +++ b/gas/testsuite/gas/mips/mips1-fp.s @@ -4,4 +4,4 @@ foo: add.s $f0,$f2,$f4 - cfc1 $2,$0 + mfc1 $2,$f0 diff --git a/gas/testsuite/gas/mips/module-check-warn.l b/gas/testsuite/gas/mips/module-check-warn.l new file mode 100644 index 0000000..2670b91 --- /dev/null +++ b/gas/testsuite/gas/mips/module-check-warn.l @@ -0,0 +1,5 @@ +.*: Assembler messages: +.*:3: Error: `fp=64' used with a 32-bit fpu +.*:3: Warning: float register should be even, was 1 +.*:3: Warning: float register should be even, was 1 +.*:3: Warning: float register should be even, was 1 diff --git a/gas/testsuite/gas/mips/module-check-warn.s b/gas/testsuite/gas/mips/module-check-warn.s new file mode 100644 index 0000000..ee5c3f0 --- /dev/null +++ b/gas/testsuite/gas/mips/module-check-warn.s @@ -0,0 +1,3 @@ +.module mips1 +.module fp=64 +add.s $f1,$f1,$f1 diff --git a/gas/testsuite/gas/mips/module-check.d b/gas/testsuite/gas/mips/module-check.d new file mode 100644 index 0000000..5542e74 --- /dev/null +++ b/gas/testsuite/gas/mips/module-check.d @@ -0,0 +1,21 @@ +#as: -32 +#readelf: -A +#name: MIPS module check + +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float \(32-bit CPU, 64-bit FPU\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS32r2 +GPR size: 32 +CPR1 size: 64 +CPR2 size: 0 +FP ABI: Hard float \(32-bit CPU, 64-bit FPU\) +ISA Extension: None +ASEs: + None +FLAGS 1: 0000000. +FLAGS 2: 00000000 + diff --git a/gas/testsuite/gas/mips/module-check.s b/gas/testsuite/gas/mips/module-check.s new file mode 100644 index 0000000..09dec20 --- /dev/null +++ b/gas/testsuite/gas/mips/module-check.s @@ -0,0 +1,4 @@ +.module mips1 +.module fp=64 +.module mips32r2 +add.s $f1,$f1,$f1 diff --git a/gas/testsuite/gas/mips/module-defer-warn1.d b/gas/testsuite/gas/mips/module-defer-warn1.d index d5ee70e..c20f367 100644 --- a/gas/testsuite/gas/mips/module-defer-warn1.d +++ b/gas/testsuite/gas/mips/module-defer-warn1.d @@ -5,3 +5,16 @@ .*:.*file format.*elf.*mips.* private flags = 1.......: .*\[mips2\].* + +MIPS ABI Flags Version: 0 + +ISA: MIPS2 +GPR size: 32 +CPR1 size: 32 +CPR2 size: 0 +FP ABI: Hard float \(double precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 diff --git a/gas/testsuite/gas/mips/module-mfp32.d b/gas/testsuite/gas/mips/module-mfp32.d new file mode 100644 index 0000000..f5c66f6 --- /dev/null +++ b/gas/testsuite/gas/mips/module-mfp32.d @@ -0,0 +1,21 @@ +#as: -32 +#readelf: -A +#name: MIPS module fp=32 + +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float \(double precision\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS1 +GPR size: 32 +CPR1 size: 32 +CPR2 size: 0 +FP ABI: Hard float \(double precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 + diff --git a/gas/testsuite/gas/mips/module-mfp32.s b/gas/testsuite/gas/mips/module-mfp32.s new file mode 100644 index 0000000..8f247b4 --- /dev/null +++ b/gas/testsuite/gas/mips/module-mfp32.s @@ -0,0 +1,3 @@ +.module fp=32 +.module doublefloat +.module hardfloat diff --git a/gas/testsuite/gas/mips/module-mfp64-noodd.d b/gas/testsuite/gas/mips/module-mfp64-noodd.d new file mode 100644 index 0000000..3a9b459 --- /dev/null +++ b/gas/testsuite/gas/mips/module-mfp64-noodd.d @@ -0,0 +1,21 @@ +#as: -mips32r2 -32 +#readelf: -A +#name: MIPS module fp=64 nooddspreg + +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float compat \(32-bit CPU, 64-bit FPU\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS32r2 +GPR size: 32 +CPR1 size: 64 +CPR2 size: 0 +FP ABI: Hard float compat \(32-bit CPU, 64-bit FPU\) +ISA Extension: None +ASEs: + None +FLAGS 1: 0000000. +FLAGS 2: 00000000 + diff --git a/gas/testsuite/gas/mips/module-mfp64-noodd.s b/gas/testsuite/gas/mips/module-mfp64-noodd.s new file mode 100644 index 0000000..6eff127 --- /dev/null +++ b/gas/testsuite/gas/mips/module-mfp64-noodd.s @@ -0,0 +1,4 @@ +.module fp=64 +.module doublefloat +.module hardfloat +.module nooddspreg diff --git a/gas/testsuite/gas/mips/module-mfp64.d b/gas/testsuite/gas/mips/module-mfp64.d new file mode 100644 index 0000000..8060b3e --- /dev/null +++ b/gas/testsuite/gas/mips/module-mfp64.d @@ -0,0 +1,21 @@ +#as: -mips32r2 -32 +#readelf: -A +#name: MIPS module fp=64 + +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float \(32-bit CPU, 64-bit FPU\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS32r2 +GPR size: 32 +CPR1 size: 64 +CPR2 size: 0 +FP ABI: Hard float \(32-bit CPU, 64-bit FPU\) +ISA Extension: None +ASEs: + None +FLAGS 1: 0000000. +FLAGS 2: 00000000 + diff --git a/gas/testsuite/gas/mips/module-mfp64.s b/gas/testsuite/gas/mips/module-mfp64.s new file mode 100644 index 0000000..6847eed --- /dev/null +++ b/gas/testsuite/gas/mips/module-mfp64.s @@ -0,0 +1,4 @@ +.module fp=64 +.module doublefloat +.module hardfloat +.module oddspreg diff --git a/gas/testsuite/gas/mips/module-mfpxx.d b/gas/testsuite/gas/mips/module-mfpxx.d new file mode 100644 index 0000000..2387eb1 --- /dev/null +++ b/gas/testsuite/gas/mips/module-mfpxx.d @@ -0,0 +1,21 @@ +#as: -mips32r2 -32 +#readelf: -A +#name: MIPS module fp=xx + +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float \(32-bit CPU, Any FPU\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS32r2 +GPR size: 32 +CPR1 size: 32 +CPR2 size: 0 +FP ABI: Hard float \(32-bit CPU, Any FPU\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 + diff --git a/gas/testsuite/gas/mips/module-mfpxx.s b/gas/testsuite/gas/mips/module-mfpxx.s new file mode 100644 index 0000000..8dd2a4c --- /dev/null +++ b/gas/testsuite/gas/mips/module-mfpxx.s @@ -0,0 +1,3 @@ +.module fp=xx +.module doublefloat +.module hardfloat diff --git a/gas/testsuite/gas/mips/module-msingle-float.d b/gas/testsuite/gas/mips/module-msingle-float.d new file mode 100644 index 0000000..588003f --- /dev/null +++ b/gas/testsuite/gas/mips/module-msingle-float.d @@ -0,0 +1,21 @@ +#as: -32 +#readelf: -A +#name: MIPS module singlefloat + +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float \(single precision\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS1 +GPR size: 32 +CPR1 size: 32 +CPR2 size: 0 +FP ABI: Hard float \(single precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 + diff --git a/gas/testsuite/gas/mips/module-msingle-float.s b/gas/testsuite/gas/mips/module-msingle-float.s new file mode 100644 index 0000000..082cccf --- /dev/null +++ b/gas/testsuite/gas/mips/module-msingle-float.s @@ -0,0 +1,3 @@ +.module fp=32 +.module singlefloat +.module hardfloat diff --git a/gas/testsuite/gas/mips/module-msoft-float.d b/gas/testsuite/gas/mips/module-msoft-float.d new file mode 100644 index 0000000..98a9ea1 --- /dev/null +++ b/gas/testsuite/gas/mips/module-msoft-float.d @@ -0,0 +1,21 @@ +#as: -32 +#readelf: -A +#name: MIPS module softfloat + +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Soft float + +MIPS ABI Flags Version: 0 + +ISA: MIPS1 +GPR size: 32 +CPR1 size: 0 +CPR2 size: 0 +FP ABI: Soft float +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 + diff --git a/gas/testsuite/gas/mips/module-msoft-float.s b/gas/testsuite/gas/mips/module-msoft-float.s new file mode 100644 index 0000000..4de4be7 --- /dev/null +++ b/gas/testsuite/gas/mips/module-msoft-float.s @@ -0,0 +1,3 @@ +.module fp=32 +.module doublefloat +.module softfloat diff --git a/gas/testsuite/gas/mips/module-override.d b/gas/testsuite/gas/mips/module-override.d index 0305b02..464eb06 100644 --- a/gas/testsuite/gas/mips/module-override.d +++ b/gas/testsuite/gas/mips/module-override.d @@ -5,3 +5,16 @@ .*:.*file format.*elf.*mips.* private flags = 1.......: .*\[mips2\].* + +MIPS ABI Flags Version: 0 + +ISA: MIPS2 +GPR size: 32 +CPR1 size: 32 +CPR2 size: 0 +FP ABI: Hard float \(double precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 diff --git a/gas/testsuite/gas/mips/module-set-mfpxx.d b/gas/testsuite/gas/mips/module-set-mfpxx.d new file mode 100644 index 0000000..d2e4ffe --- /dev/null +++ b/gas/testsuite/gas/mips/module-set-mfpxx.d @@ -0,0 +1,21 @@ +#as: -32 +#readelf: -A +#name: MIPS module fp=xx set + +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float \(32-bit CPU, Any FPU\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS32r2 +GPR size: 32 +CPR1 size: 32 +CPR2 size: 0 +FP ABI: Hard float \(32-bit CPU, Any FPU\) +ISA Extension: None +ASEs: + None +FLAGS 1: 0000000. +FLAGS 2: 00000000 + diff --git a/gas/testsuite/gas/mips/module-set-mfpxx.s b/gas/testsuite/gas/mips/module-set-mfpxx.s new file mode 100644 index 0000000..313d768 --- /dev/null +++ b/gas/testsuite/gas/mips/module-set-mfpxx.s @@ -0,0 +1,16 @@ +.module mips32r2 +.module fp=xx +.module doublefloat +.module hardfloat +.module oddspreg + +add.s $f1,$f1,$f1 +.set push +.set fp=32 +add.s $f1,$f1,$f1 +.set pop + +.set push +.set fp=64 +add.d $f1,$f1,$f1 +.set pop diff --git a/gas/testsuite/gas/mips/n32-consec.d b/gas/testsuite/gas/mips/n32-consec.d index 806857e..03b4970 100644 --- a/gas/testsuite/gas/mips/n32-consec.d +++ b/gas/testsuite/gas/mips/n32-consec.d @@ -12,3 +12,16 @@ Disassembly of section .data: 0: R_MIPS_32 .data\+0x4 Disassembly of section .reginfo: ... + +Disassembly of section .MIPS.abiflags: +.* +.* + ... +.* +.* + +Disassembly of section .gnu.attributes: +.* +.* +.* +.* diff --git a/gas/testsuite/gas/mips/nan-2008-1.d b/gas/testsuite/gas/mips/nan-2008-1.d index 3649fd2..78556f5 100644 --- a/gas/testsuite/gas/mips/nan-2008-1.d +++ b/gas/testsuite/gas/mips/nan-2008-1.d @@ -4,3 +4,4 @@ .*:.*file format.*mips.* private flags = [0-9a-f]*[4-7c-f]..: .*[[,]nan2008[],].* +#pass diff --git a/gas/testsuite/gas/mips/nan-2008-2.d b/gas/testsuite/gas/mips/nan-2008-2.d index e8a07ce..c98455b 100644 --- a/gas/testsuite/gas/mips/nan-2008-2.d +++ b/gas/testsuite/gas/mips/nan-2008-2.d @@ -5,3 +5,4 @@ .*:.*file format.*mips.* private flags = [0-9a-f]*[4-7c-f]..: .*[[,]nan2008[],].* +#pass diff --git a/gas/testsuite/gas/mips/nan-2008-3.d b/gas/testsuite/gas/mips/nan-2008-3.d index 7c3c4a3..8f179fb 100644 --- a/gas/testsuite/gas/mips/nan-2008-3.d +++ b/gas/testsuite/gas/mips/nan-2008-3.d @@ -4,3 +4,4 @@ .*:.*file format.*mips.* private flags = [0-9a-f]*[4-7c-f]..: .*[[,]nan2008[],].* +#pass diff --git a/gas/testsuite/gas/mips/nan-2008-4.d b/gas/testsuite/gas/mips/nan-2008-4.d index 22ba87f..44d5d22 100644 --- a/gas/testsuite/gas/mips/nan-2008-4.d +++ b/gas/testsuite/gas/mips/nan-2008-4.d @@ -5,3 +5,4 @@ .*:.*file format.*mips.* private flags = [0-9a-f]*[4-7c-f]..: .*[[,]nan2008[],].* +#pass diff --git a/gas/testsuite/gas/mips/nan-legacy-1.d b/gas/testsuite/gas/mips/nan-legacy-1.d index 4dcb93c..a2f6d0c 100644 --- a/gas/testsuite/gas/mips/nan-legacy-1.d +++ b/gas/testsuite/gas/mips/nan-legacy-1.d @@ -5,3 +5,17 @@ .*:.*file format.*mips.* #failif private flags = [0-9a-f]*[4-7c-f]..: .*[[]nan2008[]].* + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Hard float \(double precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 + diff --git a/gas/testsuite/gas/mips/nan-legacy-2.d b/gas/testsuite/gas/mips/nan-legacy-2.d index 6ad4dce..83c559f 100644 --- a/gas/testsuite/gas/mips/nan-legacy-2.d +++ b/gas/testsuite/gas/mips/nan-legacy-2.d @@ -6,3 +6,17 @@ .*:.*file format.*mips.* #failif private flags = [0-9a-f]*[4-7c-f]..: .*[[]nan2008[]].* + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Hard float \(double precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 + diff --git a/gas/testsuite/gas/mips/nan-legacy-3.d b/gas/testsuite/gas/mips/nan-legacy-3.d index 649f0ee..f19d1aa 100644 --- a/gas/testsuite/gas/mips/nan-legacy-3.d +++ b/gas/testsuite/gas/mips/nan-legacy-3.d @@ -5,3 +5,17 @@ .*:.*file format.*mips.* #failif private flags = [0-9a-f]*[4-7c-f]..: .*[[]nan2008[]].* + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Hard float \(double precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 + diff --git a/gas/testsuite/gas/mips/nan-legacy-4.d b/gas/testsuite/gas/mips/nan-legacy-4.d index 3dc00cb..c70d1d1 100644 --- a/gas/testsuite/gas/mips/nan-legacy-4.d +++ b/gas/testsuite/gas/mips/nan-legacy-4.d @@ -6,3 +6,17 @@ .*:.*file format.*mips.* #failif private flags = [0-9a-f]*[4-7c-f]..: .*[[]nan2008[]].* + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Hard float \(double precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 + diff --git a/gas/testsuite/gas/mips/nan-legacy-5.d b/gas/testsuite/gas/mips/nan-legacy-5.d index db3a954..d3b2480 100644 --- a/gas/testsuite/gas/mips/nan-legacy-5.d +++ b/gas/testsuite/gas/mips/nan-legacy-5.d @@ -5,3 +5,17 @@ .*:.*file format.*mips.* #failif private flags = [0-9a-f]*[4-7c-f]..: .*[[]nan2008[]].* + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Hard float \(double precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 00000000 +FLAGS 2: 00000000 + diff --git a/gas/testsuite/gas/mips/no-odd-spreg.d b/gas/testsuite/gas/mips/no-odd-spreg.d new file mode 100644 index 0000000..f33e3a6 --- /dev/null +++ b/gas/testsuite/gas/mips/no-odd-spreg.d @@ -0,0 +1,22 @@ +#PROG: readelf +#source: empty.s +#as: -32 -mno-odd-spreg +#readelf: -A +#name: -mno-odd-spreg test + +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: .* + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: .* +ISA Extension: .* +ASEs: +#... +FLAGS 1: 00000000 +FLAGS 2: 00000000 diff --git a/gas/testsuite/gas/mips/odd-spreg.d b/gas/testsuite/gas/mips/odd-spreg.d new file mode 100644 index 0000000..7f80c2c --- /dev/null +++ b/gas/testsuite/gas/mips/odd-spreg.d @@ -0,0 +1,22 @@ +#PROG: readelf +#source: empty.s +#as: -32 -modd-spreg +#readelf: -A +#name: -modd-spreg test + +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: .* + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: .* +ISA Extension: .* +ASEs: +#... +FLAGS 1: 00000001 +FLAGS 2: 00000000 diff --git a/gas/testsuite/gas/mips/tmips16-e.d b/gas/testsuite/gas/mips/tmips16-e.d index ddd6aaa..708ff11 100644 --- a/gas/testsuite/gas/mips/tmips16-e.d +++ b/gas/testsuite/gas/mips/tmips16-e.d @@ -15,7 +15,9 @@ SYMBOL TABLE: 0+0000004 l \.text 0+0000000 0xf0 \.L1.1 0+0000000 l d foo 0+0000000 (|foo) 0+0000000 l d \.reginfo 0+0000000 (|\.reginfo) +0+0000000 l d \.MIPS\.abiflags 0+0000000 (|\.MIPS\.abiflags) 0+0000000 l d \.(mdebug|pdr) 0+0000000 (|\.mdebug|\.pdr) +0+0000000 l d \.gnu\.attributes 0+0000000 (|\.gnu\.attributes) 0+0000000 \*UND\* 0+0000000 g1 @@ -34,6 +36,11 @@ Contents of section \.text: Contents of section \.reginfo: 0000 00010000 00000000 00000000 00000000 .* 0010 00000000 00000000 .* +Contents of section .MIPS.abiflags: + .* + .* Contents of section foo: 0000 00000000 00000008 00000000 00000003 .* 0010 00000000 00000008 00000000 00000000 .* +Contents of section .gnu.attributes: + .* diff --git a/gas/testsuite/gas/mips/tmips16-f.d b/gas/testsuite/gas/mips/tmips16-f.d index f865d1d..057122c 100644 --- a/gas/testsuite/gas/mips/tmips16-f.d +++ b/gas/testsuite/gas/mips/tmips16-f.d @@ -14,7 +14,9 @@ SYMBOL TABLE: 0+0000002 l \.text 0+0000000 0xf0 l1 0+0000000 l d foo 0+0000000 (|foo) 0+0000000 l d \.reginfo 0+0000000 (|\.reginfo) +0+0000000 l d \.MIPS\.abiflags 0+0000000 (|\.MIPS\.abiflags) 0+0000000 l d \.(mdebug|pdr) 0+0000000 (|\.mdebug|\.pdr) +0+0000000 l d \.gnu\.attributes 0+0000000 (|\.gnu\.attributes) RELOCATION RECORDS FOR \[foo\]: @@ -27,5 +29,10 @@ Contents of section \.text: Contents of section \.reginfo: 0000 00010000 00000000 00000000 00000000 .* 0010 00000000 00000000 .* +Contents of section .MIPS.abiflags: + .* + .* Contents of section foo: 0000 00000003 00000000 00000000 00000000 .* +Contents of section .gnu.attributes: + .* diff --git a/gas/testsuite/gas/mips/tmipsel16-e.d b/gas/testsuite/gas/mips/tmipsel16-e.d index 0af3793..839446b 100644 --- a/gas/testsuite/gas/mips/tmipsel16-e.d +++ b/gas/testsuite/gas/mips/tmipsel16-e.d @@ -15,7 +15,9 @@ SYMBOL TABLE: 0+0000004 l \.text 0+0000000 0xf0 \.L1.1 0+0000000 l d foo 0+0000000 (|foo) 0+0000000 l d \.reginfo 0+0000000 (|\.reginfo) +0+0000000 l d \.MIPS\.abiflags 0+0000000 (|\.MIPS\.abiflags) 0+0000000 l d \.(mdebug|pdr) 0+0000000 (|\.mdebug|\.pdr) +0+0000000 l d \.gnu\.attributes 0+0000000 (|\.gnu\.attributes) 0+0000000 \*UND\* 0+0000000 g1 @@ -34,6 +36,11 @@ Contents of section \.text: Contents of section \.reginfo: 0000 00000100 00000000 00000000 00000000 .* 0010 00000000 00000000 .* +Contents of section .MIPS.abiflags: + .* + .* Contents of section foo: 0000 00000000 08000000 00000000 03000000 .* 0010 00000000 08000000 00000000 00000000 .* +Contents of section .gnu.attributes: + .* diff --git a/gas/testsuite/gas/mips/tmipsel16-f.d b/gas/testsuite/gas/mips/tmipsel16-f.d index 5daa593..edc6068 100644 --- a/gas/testsuite/gas/mips/tmipsel16-f.d +++ b/gas/testsuite/gas/mips/tmipsel16-f.d @@ -14,7 +14,9 @@ SYMBOL TABLE: 0+0000002 l \.text 0+0000000 0xf0 l1 0+0000000 l d foo 0+0000000 (|foo) 0+0000000 l d \.reginfo 0+0000000 (\.reginfo) +0+0000000 l d \.MIPS\.abiflags 0+0000000 (\.MIPS\.abiflags) 0+0000000 l d \.(mdebug|pdr) 0+0000000 (\.mdebug|\.pdr) +0+0000000 l d \.gnu\.attributes 0+0000000 (\.gnu\.attributes) RELOCATION RECORDS FOR \[foo\]: @@ -27,5 +29,10 @@ Contents of section \.text: Contents of section \.reginfo: 0000 00000100 00000000 00000000 00000000 .* 0010 00000000 00000000 .* +Contents of section .MIPS.abiflags: + .* + .* Contents of section foo: 0000 03000000 00000000 00000000 00000000 .* +Contents of section .gnu.attributes: + .* diff --git a/include/ChangeLog b/include/ChangeLog index 96ae31d..8a4d265 100644 --- a/include/ChangeLog +++ b/include/ChangeLog @@ -1,3 +1,25 @@ +2014-07-29 Matthew Fortune <matthew.fortune@imgtec.com> + + * elf/mips.h (PT_MIPS_ABIFLAGS, SHT_MIPS_ABIFLAGS): Define. + (Val_GNU_MIPS_ABI_FP_OLD_64): Rename from Val_GNU_MIPS_ABI_FP_64. + (Val_GNU_MIPS_ABI_FP_64): Redefine. + (Val_GNU_MIPS_ABI_FP_XX): Define. + (Elf_External_ABIFlags_v0, Elf_Internal_ABIFlags_v0): New structures. + (AFL_REG_NONE, AFL_REG_32, AFL_REG_64, AFL_REG_128): Define. + (AFL_ASE_DSP, AFL_ASE_DSPR2, AFL_ASE_EVA, AFL_ASE_MCU): Likewise. + (AFL_ASE_MDMX, AFL_ASE_MIPS3D, AFL_ASE_MT, AFL_ASE_SMARTMIPS): Likewise. + (AFL_ASE_VIRT, AFL_ASE_MSA, AFL_ASE_MIPS16): Likewise. + (AFL_ASE_MICROMIPS, AFL_ASE_XPA): Likewise. + (AFL_EXT_XLR, AFL_EXT_OCTEON2, AFL_EXT_OCTEONP): Likewise. + (AFL_EXT_LOONGSON_3A, AFL_EXT_OCTEON, AFL_EXT_5900): Likewise. + (AFL_EXT_4650, AFL_EXT_4010, AFL_EXT_4100, AFL_EXT_3900): Likewise. + (AFL_EXT_10000, AFL_EXT_SB1, AFL_EXT_4111, AFL_EXT_4120): Likewise. + (AFL_EXT_5400, AFL_EXT_5500, AFL_EXT_LOONGSON_2E): Likewise. + (AFL_EXT_LOONGSON_2F): Likewise. + (bfd_mips_elf_swap_abiflags_v0_in): Prototype. + (bfd_mips_elf_swap_abiflags_v0_out): Likewise. + (bfd_mips_isa_ext): Likewise. + 2014-06-13 Alan Modra <amodra@gmail.com> * bfdlink.h (struct bfd_link_hash_table): Add hash_table_free field. diff --git a/include/elf/mips.h b/include/elf/mips.h index 2949629..24c2380 100644 --- a/include/elf/mips.h +++ b/include/elf/mips.h @@ -428,6 +428,8 @@ END_RELOC_NUMBERS (R_MIPS_maxext) /* Runtime procedure descriptor table exception information (ucode) ??? */ #define SHT_MIPS_PDR_EXCEPTION 0x70000029 +/* ABI related flags section. */ +#define SHT_MIPS_ABIFLAGS 0x7000002a /* A section of type SHT_MIPS_LIBLIST contains an array of the following structure. The sh_link field is the section index of the @@ -593,6 +595,9 @@ extern void bfd_mips_elf32_swap_reginfo_out /* .MIPS.options section. */ #define PT_MIPS_OPTIONS 0x70000002 + +/* Records ABI related flags. */ +#define PT_MIPS_ABIFLAGS 0x70000003 /* Processor specific dynamic array tags. */ @@ -1048,6 +1053,58 @@ typedef struct bfd_vma ri_gp_value; } Elf64_Internal_RegInfo; +/* ABI Flags structure version 0. */ + +typedef struct +{ + /* Version of flags structure. */ + unsigned char version[2]; + /* The level of the ISA: 1-5, 32, 64. */ + unsigned char isa_level[1]; + /* The revision of ISA: 0 for MIPS V and below, 1-n otherwise. */ + unsigned char isa_rev[1]; + /* The size of general purpose registers. */ + unsigned char gpr_size[1]; + /* The size of co-processor 1 registers. */ + unsigned char cpr1_size[1]; + /* The size of co-processor 2 registers. */ + unsigned char cpr2_size[1]; + /* The floating-point ABI. */ + unsigned char fp_abi[1]; + /* Processor-specific extension. */ + unsigned char isa_ext[4]; + /* Mask of ASEs used. */ + unsigned char ases[4]; + /* Mask of general flags. */ + unsigned char flags1[4]; + unsigned char flags2[4]; +} Elf_External_ABIFlags_v0; + +typedef struct +{ + /* Version of flags structure. */ + unsigned short version; + /* The level of the ISA: 1-5, 32, 64. */ + unsigned char isa_level; + /* The revision of ISA: 0 for MIPS V and below, 1-n otherwise. */ + unsigned char isa_rev; + /* The size of general purpose registers. */ + unsigned char gpr_size; + /* The size of co-processor 1 registers. */ + unsigned char cpr1_size; + /* The size of co-processor 2 registers. */ + unsigned char cpr2_size; + /* The floating-point ABI. */ + unsigned char fp_abi; + /* Processor-specific extension. */ + unsigned long isa_ext; + /* Mask of ASEs used. */ + unsigned long ases; + /* Mask of general flags. */ + unsigned long flags1; + unsigned long flags2; +} Elf_Internal_ABIFlags_v0; + typedef struct { /* The hash value computed from the name of the corresponding @@ -1088,6 +1145,12 @@ extern void bfd_mips_elf64_swap_reginfo_in extern void bfd_mips_elf64_swap_reginfo_out (bfd *, const Elf64_Internal_RegInfo *, Elf64_External_RegInfo *); +/* MIPS ELF flags swapping routines. */ +extern void bfd_mips_elf_swap_abiflags_v0_in + (bfd *, const Elf_External_ABIFlags_v0 *, Elf_Internal_ABIFlags_v0 *); +extern void bfd_mips_elf_swap_abiflags_v0_out + (bfd *, const Elf_Internal_ABIFlags_v0 *, Elf_External_ABIFlags_v0 *); + /* Masks for the info work of an ODK_EXCEPTIONS descriptor. */ #define OEX_FPU_MIN 0x1f /* FPEs which must be enabled. */ #define OEX_FPU_MAX 0x1f00 /* FPEs which may be enabled. */ @@ -1125,6 +1188,55 @@ extern void bfd_mips_elf64_swap_reginfo_out /* Masks for the info word of an ODK_HWAND/ODK_HWOR descriptor. */ #define OHWA0_R4KEOP_CHECKED 0x00000001 #define OHWA0_R4KEOP_CLEAN 0x00000002 + +/* Values for the xxx_size bytes of an ABI flags structure. */ + +#define AFL_REG_NONE 0x00 /* No registers. */ +#define AFL_REG_32 0x01 /* 32-bit registers. */ +#define AFL_REG_64 0x02 /* 64-bit registers. */ +#define AFL_REG_128 0x03 /* 128-bit registers. */ + +/* Masks for the ases word of an ABI flags structure. */ + +#define AFL_ASE_DSP 0x00000001 /* DSP ASE. */ +#define AFL_ASE_DSPR2 0x00000002 /* DSP R2 ASE. */ +#define AFL_ASE_EVA 0x00000004 /* Enhanced VA Scheme. */ +#define AFL_ASE_MCU 0x00000008 /* MCU (MicroController) ASE. */ +#define AFL_ASE_MDMX 0x00000010 /* MDMX ASE. */ +#define AFL_ASE_MIPS3D 0x00000020 /* MIPS-3D ASE. */ +#define AFL_ASE_MT 0x00000040 /* MT ASE. */ +#define AFL_ASE_SMARTMIPS 0x00000080 /* SmartMIPS ASE. */ +#define AFL_ASE_VIRT 0x00000100 /* VZ ASE. */ +#define AFL_ASE_MSA 0x00000200 /* MSA ASE. */ +#define AFL_ASE_MIPS16 0x00000400 /* MIPS16 ASE. */ +#define AFL_ASE_MICROMIPS 0x00000800 /* MICROMIPS ASE. */ +#define AFL_ASE_XPA 0x00001000 /* XPA ASE. */ + +/* Values for the isa_ext word of an ABI flags structure. */ + +#define AFL_EXT_XLR 1 /* RMI Xlr instruction. */ +#define AFL_EXT_OCTEON2 2 /* Cavium Networks Octeon2. */ +#define AFL_EXT_OCTEONP 3 /* Cavium Networks OcteonP. */ +#define AFL_EXT_LOONGSON_3A 4 /* Loongson 3A. */ +#define AFL_EXT_OCTEON 5 /* Cavium Networks Octeon. */ +#define AFL_EXT_5900 6 /* MIPS R5900 instruction. */ +#define AFL_EXT_4650 7 /* MIPS R4650 instruction. */ +#define AFL_EXT_4010 8 /* LSI R4010 instruction. */ +#define AFL_EXT_4100 9 /* NEC VR4100 instruction. */ +#define AFL_EXT_3900 10 /* Toshiba R3900 instruction. */ +#define AFL_EXT_10000 11 /* MIPS R10000 instruction. */ +#define AFL_EXT_SB1 12 /* Broadcom SB-1 instruction. */ +#define AFL_EXT_4111 13 /* NEC VR4111/VR4181 instruction. */ +#define AFL_EXT_4120 14 /* NEC VR4120 instruction. */ +#define AFL_EXT_5400 15 /* NEC VR5400 instruction. */ +#define AFL_EXT_5500 16 /* NEC VR5500 instruction. */ +#define AFL_EXT_LOONGSON_2E 17 /* ST Microelectronics Loongson 2E. */ +#define AFL_EXT_LOONGSON_2F 18 /* ST Microelectronics Loongson 2F. */ + +/* Masks for the flags1 word of an ABI flags structure. */ +#define AFL_FLAGS1_ODDSPREG 1 /* Uses odd single-precision registers. */ + +extern unsigned int bfd_mips_isa_ext (bfd *); /* Object attribute tags. */ @@ -1157,7 +1269,16 @@ enum Val_GNU_MIPS_ABI_FP_SOFT = 3, /* Using -mips32r2 -mfp64. */ - Val_GNU_MIPS_ABI_FP_64 = 4, + Val_GNU_MIPS_ABI_FP_OLD_64 = 4, + + /* Using -mfpxx */ + Val_GNU_MIPS_ABI_FP_XX = 5, + + /* Using -mips32r2 -mfp64. */ + Val_GNU_MIPS_ABI_FP_64 = 6, + + /* Using -mips32r2 -mfp64 -mno-odd-spreg. */ + Val_GNU_MIPS_ABI_FP_64A = 7, /* Values defined for Tag_GNU_MIPS_ABI_MSA. */ diff --git a/ld/ChangeLog b/ld/ChangeLog index e6ed34c..0f6c57c 100644 --- a/ld/ChangeLog +++ b/ld/ChangeLog @@ -1,3 +1,9 @@ +2014-07-29 Matthew Fortune <matthew.fortune@imgtec.com> + + * emulparams/elf32bmip.sh: Add .MIPS.abiflags. + * emulparams/elf32bmipn32-defs.sh: Likewise. + * emulparams/elf64bmip-defs.sh: Likewise. + 2014-07-27 Anthony Green <green@moxielogic.com> * Makefile.am (ALL_EMULATION_SOURCES): Add moxiebox support. diff --git a/ld/emulparams/elf32bmip.sh b/ld/emulparams/elf32bmip.sh index 118d57a..8da0f8f 100644 --- a/ld/emulparams/elf32bmip.sh +++ b/ld/emulparams/elf32bmip.sh @@ -17,7 +17,8 @@ if test -z "${CREATE_SHLIB}"; then INITIAL_READONLY_SECTIONS=".interp ${RELOCATING-0} : { *(.interp) }" fi INITIAL_READONLY_SECTIONS="${INITIAL_READONLY_SECTIONS} - .reginfo ${RELOCATING-0} : { *(.reginfo) } + .MIPS.abiflags ${RELOCATING-0} : { *(.MIPS.abiflags) } + .reginfo ${RELOCATING-0} : { *(.reginfo) } " OTHER_TEXT_SECTIONS='*(.mips16.fn.*) *(.mips16.call.*)' # Unlike most targets, the MIPS backend puts all dynamic relocations diff --git a/ld/emulparams/elf32bmipn32-defs.sh b/ld/emulparams/elf32bmipn32-defs.sh index 514990b..723eac8 100644 --- a/ld/emulparams/elf32bmipn32-defs.sh +++ b/ld/emulparams/elf32bmipn32-defs.sh @@ -88,6 +88,7 @@ if test -z "${CREATE_SHLIB}"; then INITIAL_READONLY_SECTIONS=".interp ${RELOCATING-0} : { *(.interp) }" fi INITIAL_READONLY_SECTIONS="${INITIAL_READONLY_SECTIONS} + .MIPS.abiflags ${RELOCATING-0} : { *(.MIPS.abiflags) } .reginfo ${RELOCATING-0} : { *(.reginfo) }" # Discard any .MIPS.content* or .MIPS.events* sections. The linker # doesn't know how to adjust them. diff --git a/ld/emulparams/elf64bmip-defs.sh b/ld/emulparams/elf64bmip-defs.sh index 110f892..8a0522f 100644 --- a/ld/emulparams/elf64bmip-defs.sh +++ b/ld/emulparams/elf64bmip-defs.sh @@ -1,3 +1,6 @@ . ${srcdir}/emulparams/elf32bmipn32-defs.sh COMMONPAGESIZE="CONSTANT (COMMONPAGESIZE)" -INITIAL_READONLY_SECTIONS=".MIPS.options : { *(.MIPS.options) }" +INITIAL_READONLY_SECTIONS=" + .MIPS.abiflags ${RELOCATING-0} : { *(.MIPS.abiflags) } + .MIPS.options : { *(.MIPS.options) } +" diff --git a/ld/testsuite/ChangeLog b/ld/testsuite/ChangeLog index e940e1a..02f9dc4 100644 --- a/ld/testsuite/ChangeLog +++ b/ld/testsuite/ChangeLog @@ -1,3 +1,159 @@ +2014-07-29 Matthew Fortune <matthew.fortune@imgtec.com> + + * ld-mips-elf/abiflags-strip1-ph.d: New. + * ld-mips-elf/abiflags-strip2-ph.d: Likewise. + * ld-mips-elf/abiflags-strip3-ph.d: Likewise. + * ld-mips-elf/abiflags-strip4-ph.d: Likewise. + * ld-mips-elf/abiflags-strip5-ph.d: Likewise. + * ld-mips-elf/abiflags-strip6-ph.d: Likewise. + * ld-mips-elf/abiflags-strip7-ph.d: Likewise. + * ld-mips-elf/abiflags-strip8-ph.d: Likewise. + * ld-mips-elf/abiflags-strip9-ph.d: Likewise. + * ld-mips-elf/attr-gnu-4-0-n32-ph.d: Likewise. + * ld-mips-elf/attr-gnu-4-0-n64-ph.d: Likewise. + * ld-mips-elf/attr-gnu-4-0-ph.d: Likewise. + * ld-mips-elf/attr-gnu-4-06.d: Likewise. + * ld-mips-elf/attr-gnu-4-07.d: Likewise. + * ld-mips-elf/attr-gnu-4-08.d: Likewise. + * ld-mips-elf/attr-gnu-4-1-n32-ph.d: Likewise. + * ld-mips-elf/attr-gnu-4-1-n64-ph.d: Likewise. + * ld-mips-elf/attr-gnu-4-1-ph.d: Likewise. + * ld-mips-elf/attr-gnu-4-16.d: Likewise. + * ld-mips-elf/attr-gnu-4-17.d: Likewise. + * ld-mips-elf/attr-gnu-4-18.d: Likewise. + * ld-mips-elf/attr-gnu-4-2-n32-ph.d: Likewise. + * ld-mips-elf/attr-gnu-4-2-n64-ph.d: Likewise. + * ld-mips-elf/attr-gnu-4-2-ph.d: Likewise. + * ld-mips-elf/attr-gnu-4-26.d: Likewise. + * ld-mips-elf/attr-gnu-4-27.d: Likewise. + * ld-mips-elf/attr-gnu-4-28.d: Likewise. + * ld-mips-elf/attr-gnu-4-3-n32-ph.d: Likewise. + * ld-mips-elf/attr-gnu-4-3-n64-ph.d: Likewise. + * ld-mips-elf/attr-gnu-4-3-ph.d: Likewise. + * ld-mips-elf/attr-gnu-4-36.d: Likewise. + * ld-mips-elf/attr-gnu-4-37.d: Likewise. + * ld-mips-elf/attr-gnu-4-38.d: Likewise. + * ld-mips-elf/attr-gnu-4-4-ph.d: Likewise. + * ld-mips-elf/attr-gnu-4-46.d: Likewise. + * ld-mips-elf/attr-gnu-4-47.d: Likewise. + * ld-mips-elf/attr-gnu-4-48.d: Likewise. + * ld-mips-elf/attr-gnu-4-5-ph.d: Likewise. + * ld-mips-elf/attr-gnu-4-50.d: Likewise. + * ld-mips-elf/attr-gnu-4-52.d: Likewise. + * ld-mips-elf/attr-gnu-4-53.d: Likewise. + * ld-mips-elf/attr-gnu-4-54.d: Likewise. + * ld-mips-elf/attr-gnu-4-55.d: Likewise. + * ld-mips-elf/attr-gnu-4-56.d: Likewise. + * ld-mips-elf/attr-gnu-4-57.d: Likewise. + * ld-mips-elf/attr-gnu-4-58.d: Likewise. + * ld-mips-elf/attr-gnu-4-6-ph.d: Likewise. + * ld-mips-elf/attr-gnu-4-6.s: Likewise. + * ld-mips-elf/attr-gnu-4-60.d: Likewise. + * ld-mips-elf/attr-gnu-4-61.d: Likewise. + * ld-mips-elf/attr-gnu-4-62.d: Likewise. + * ld-mips-elf/attr-gnu-4-63.d: Likewise. + * ld-mips-elf/attr-gnu-4-64.d: Likewise. + * ld-mips-elf/attr-gnu-4-65.d: Likewise. + * ld-mips-elf/attr-gnu-4-66.d: Likewise. + * ld-mips-elf/attr-gnu-4-67.d: Likewise. + * ld-mips-elf/attr-gnu-4-68.d: Likewise. + * ld-mips-elf/attr-gnu-4-7-ph.d: Likewise. + * ld-mips-elf/attr-gnu-4-7.s: Likewise. + * ld-mips-elf/attr-gnu-4-70.d: Likewise. + * ld-mips-elf/attr-gnu-4-71.d: Likewise. + * ld-mips-elf/attr-gnu-4-72.d: Likewise. + * ld-mips-elf/attr-gnu-4-73.d: Likewise. + * ld-mips-elf/attr-gnu-4-74.d: Likewise. + * ld-mips-elf/attr-gnu-4-75.d: Likewise. + * ld-mips-elf/attr-gnu-4-76.d: Likewise. + * ld-mips-elf/attr-gnu-4-77.d: Likewise. + * ld-mips-elf/attr-gnu-4-78.d: Likewise. + * ld-mips-elf/attr-gnu-4-8.s: Likewise. + * ld-mips-elf/attr-gnu-4-81.d: Likewise. + * ld-mips-elf/empty.s: Likewise. + * ld-mips-elf/attr-gnu-4-00.d: Adjust expected output. + * ld-mips-elf/attr-gnu-4-01.d: Likewise. + * ld-mips-elf/attr-gnu-4-02.d: Likewise. + * ld-mips-elf/attr-gnu-4-03.d: Likewise. + * ld-mips-elf/attr-gnu-4-04.d: Likewise. + * ld-mips-elf/attr-gnu-4-05.d: Likewise. + * ld-mips-elf/attr-gnu-4-10.d: Likewise. + * ld-mips-elf/attr-gnu-4-11.d: Likewise. + * ld-mips-elf/attr-gnu-4-14.d: Likewise. + * ld-mips-elf/attr-gnu-4-15.d: Likewise. + * ld-mips-elf/attr-gnu-4-2.s: Likewise. + * ld-mips-elf/attr-gnu-4-20.d: Likewise. + * ld-mips-elf/attr-gnu-4-22.d: Likewise. + * ld-mips-elf/attr-gnu-4-24.d: Likewise. + * ld-mips-elf/attr-gnu-4-25.d: Likewise. + * ld-mips-elf/attr-gnu-4-3.s: Likewise. + * ld-mips-elf/attr-gnu-4-30.d: Likewise. + * ld-mips-elf/attr-gnu-4-33.d: Likewise. + * ld-mips-elf/attr-gnu-4-34.d: Likewise. + * ld-mips-elf/attr-gnu-4-35.d: Likewise. + * ld-mips-elf/attr-gnu-4-40.d: Likewise. + * ld-mips-elf/attr-gnu-4-41.d: Likewise. + * ld-mips-elf/attr-gnu-4-42.d: Likewise. + * ld-mips-elf/attr-gnu-4-43.d: Likewise. + * ld-mips-elf/attr-gnu-4-44.d: Likewise. + * ld-mips-elf/attr-gnu-4-45.d: Likewise. + * ld-mips-elf/attr-gnu-4-5.s: Likewise. + * ld-mips-elf/attr-gnu-4-51.d: Likewise. + * ld-mips-elf/attr-gnu-8-00.d: Likewise. + * ld-mips-elf/attr-gnu-8-01.d: Likewise. + * ld-mips-elf/attr-gnu-8-02.d: Likewise. + * ld-mips-elf/attr-gnu-8-10.d: Likewise. + * ld-mips-elf/attr-gnu-8-11.d: Likewise. + * ld-mips-elf/attr-gnu-8-20.d: Likewise. + * ld-mips-elf/attr-gnu-8-22.d: Likewise. + * ld-mips-elf/jalx-2.dd: Likewise. + * ld-mips-elf/mips16-pic-1.gd: Likewise. + * ld-mips-elf/mips16-pic-2.gd: Likewise. + * ld-mips-elf/mips16-pic-3.gd: Likewise. + * ld-mips-elf/mips16-pic-4a.gd: Likewise. + * ld-mips-elf/multi-got-no-shared.d: Likewise. + * ld-mips-elf/nan-2008.d: Likewise. + * ld-mips-elf/nan-legacy.d: Rework test. + * ld-mips-elf/pic-and-nonpic-3a.gd: Likewise. + * ld-mips-elf/pic-and-nonpic-3b.gd: Likewise. + * ld-mips-elf/pic-and-nonpic-5b.gd: Likewise. + * ld-mips-elf/pic-and-nonpic-6.ld: Likewise. + * ld-mips-elf/rel32-n32.d: Likewise. + * ld-mips-elf/rel32-o32.d: Likewise. + * ld-mips-elf/rel64.d: Likewise. + * ld-mips-elf/tls-multi-got-1.r: Likewise. + * ld-elf/group.ld: Discard .MIPS.abiflags and .gnu.attributes. + * ld-elf/orphan-region.ld: Likewise. + * ld-elf/orphan.ld: Likewise. + * ld-mips-elf/compressed-plt-1.ld: Likewise. + * ld-mips-elf/dyn-sec64.ld: Likewise. + * ld-mips-elf/got-dump-1.ld: Likewise. + * ld-mips-elf/got-dump-2.ld: Likewise. + * ld-mips-elf/got-page-1.ld: Likewise. + * ld-mips-elf/mips-dyn.ld: Likewise. + * ld-mips-elf/mips-lib.ld: Likewise. + * ld-mips-elf/pic-and-nonpic-3a.ld: Likewise. + * ld-mips-elf/pic-and-nonpic-3b.ld: Likewise. + * ld-mips-elf/pic-and-nonpic-4b.ld: Likewise. + * ld-mips-elf/pic-and-nonpic-5b.ld: Likewise. + * ld-mips-elf/region1.t: Likewise. + * ld-mips-elf/stub-dynsym-1.ld: Likewise. + * ld-mips-elf/tls-hidden3.ld: Likewise. + * ld-mips-elf/vxworks1.ld: Likewise. + * ld-scripts/overlay-size.t: Likewise. + * ld-mips-elf/elf-rel-got-n32-embed.d: Remove .MIPS.abiflags from + objects. + * ld-mips-elf/elf-rel-got-n32.d: Likewise. + * ld-mips-elf/elf-rel-got-n64-embed.d: Likewise. + * ld-mips-elf/elf-rel-got-n64-linux.d: Likewise. + * ld-mips-elf/elf-rel-got-n64.d: Likewise. + * ld-mips-elf/elf-rel-xgot-n32.d: Likewise. + * ld-mips-elf/elf-rel-xgot-n32-embed.d: Likewise. + * ld-mips-elf/elf-rel-xgot-n64.d: Likewise. + * ld-mips-elf/elf-rel-xgot-n64-linux.d: Likewise. + * ld-mips-elf/elf-rel-xgot-n64-embed.d: Likewise. + * ld-mips-elf/mips-elf.exp: Add new tests. + 2014-07-16 H.J. Lu <hongjiu.lu@intel.com> PR binutils/17154 diff --git a/ld/testsuite/ld-elf/group.ld b/ld/testsuite/ld-elf/group.ld index 123ab26..f8e50c3 100644 --- a/ld/testsuite/ld-elf/group.ld +++ b/ld/testsuite/ld-elf/group.ld @@ -2,5 +2,5 @@ SECTIONS { . = 0x1000; .text : { *(.text) *(.rodata.brlt) } - /DISCARD/ : { *(.dropme) *(.reginfo) } + /DISCARD/ : { *(.dropme) *(.reginfo) *(.MIPS.abiflags) } } diff --git a/ld/testsuite/ld-elf/orphan-region.ld b/ld/testsuite/ld-elf/orphan-region.ld index b7dfdba..2abf8bc 100644 --- a/ld/testsuite/ld-elf/orphan-region.ld +++ b/ld/testsuite/ld-elf/orphan-region.ld @@ -7,5 +7,5 @@ SECTIONS { .text : ALIGN (4) { *(.text) } > region .rodata : ALIGN (4) { *(.rodata) } > region - /DISCARD/ : { *(.reginfo) *(.trampolines) } + /DISCARD/ : { *(.reginfo) *(.MIPS.abiflags) *(.trampolines) } } diff --git a/ld/testsuite/ld-elf/orphan.ld b/ld/testsuite/ld-elf/orphan.ld index d23222b..44eb7eb 100644 --- a/ld/testsuite/ld-elf/orphan.ld +++ b/ld/testsuite/ld-elf/orphan.ld @@ -4,5 +4,5 @@ SECTIONS .data : { *(.data) } .bss : { *(.bss) *(COMMON) } .note : { *(.note) } - /DISCARD/ : { *(.reginfo) *(.trampolines) } + /DISCARD/ : { *(.reginfo) *(.MIPS.abiflags) *(.trampolines) } } diff --git a/ld/testsuite/ld-mips-elf/abiflags-strip1-ph.d b/ld/testsuite/ld-mips-elf/abiflags-strip1-ph.d new file mode 100644 index 0000000..3af3433 --- /dev/null +++ b/ld/testsuite/ld-mips-elf/abiflags-strip1-ph.d @@ -0,0 +1,13 @@ +#source: jr.s -mips32r2 -32 -mfp32 -EB RUN_OBJCOPY +#objcopy_objects: -R .MIPS.abiflags +#ld: -melf32btsmip -e 0 +#objdump: -p + +[^:]*: file format elf32-tradbigmips + +Program Header: +#... +!0x70000003.* +#... +private flags = 70001000: \[abi=O32\] \[mips32r2\] \[not 32bitmode\] + diff --git a/ld/testsuite/ld-mips-elf/abiflags-strip2-ph.d b/ld/testsuite/ld-mips-elf/abiflags-strip2-ph.d new file mode 100644 index 0000000..1da7840 --- /dev/null +++ b/ld/testsuite/ld-mips-elf/abiflags-strip2-ph.d @@ -0,0 +1,29 @@ +#source: jr.s -mips32r2 -32 -mfpxx -EB +#source: jr.s -march=octeon -32 -mfp64 -EB RUN_OBJCOPY +#ld: -melf32btsmip -e 0 +#objcopy_objects: -R .MIPS.abiflags +#objdump: -p + +[^:]*: file format elf32-tradbigmips + +Program Header: +0x70000003 off 0x000000.. vaddr 0x004000.. paddr 0x004000.. align 2\*\*3 + filesz 0x00000018 memsz 0x00000018 flags r-- +#... + LOAD off 0x00000000 vaddr 0x00400000 paddr 0x00400000 align 2\*\*16 + filesz 0x000000.. memsz 0x000000.. flags r-x +private flags = 808b1100: \[abi=O32\] \[mips64r2\] \[32bitmode\] + +MIPS ABI Flags Version: 0 + +ISA: MIPS64r2 +GPR size: 32 +CPR1 size: 64 +CPR2 size: 0 +FP ABI: Hard float \(32-bit CPU, 64-bit FPU\) +ISA Extension: Cavium Networks Octeon +ASEs: + None +FLAGS 1: 0000000. +FLAGS 2: 00000000 + diff --git a/ld/testsuite/ld-mips-elf/abiflags-strip3-ph.d b/ld/testsuite/ld-mips-elf/abiflags-strip3-ph.d new file mode 100644 index 0000000..df5640a --- /dev/null +++ b/ld/testsuite/ld-mips-elf/abiflags-strip3-ph.d @@ -0,0 +1,29 @@ +#source: jr.s -march=octeon -32 -mfp64 -EB RUN_OBJCOPY +#source: jr.s -mips32r2 -32 -mfpxx -EB +#ld: -melf32btsmip -e 0 +#objcopy_objects: -R .MIPS.abiflags +#objdump: -p + +[^:]*: file format elf32-tradbigmips + +Program Header: +0x70000003 off 0x000000.. vaddr 0x004000.. paddr 0x004000.. align 2\*\*3 + filesz 0x00000018 memsz 0x00000018 flags r-- +#... + LOAD off 0x00000000 vaddr 0x00400000 paddr 0x00400000 align 2\*\*16 + filesz 0x000000.. memsz 0x000000.. flags r-x +private flags = 808b1100: \[abi=O32\] \[mips64r2\] \[32bitmode\] + +MIPS ABI Flags Version: 0 + +ISA: MIPS64r2 +GPR size: 32 +CPR1 size: 64 +CPR2 size: 0 +FP ABI: Hard float \(32-bit CPU, 64-bit FPU\) +ISA Extension: Cavium Networks Octeon +ASEs: + None +FLAGS 1: 0000000. +FLAGS 2: 00000000 + diff --git a/ld/testsuite/ld-mips-elf/abiflags-strip4-ph.d b/ld/testsuite/ld-mips-elf/abiflags-strip4-ph.d new file mode 100644 index 0000000..09ceadf --- /dev/null +++ b/ld/testsuite/ld-mips-elf/abiflags-strip4-ph.d @@ -0,0 +1,33 @@ +#source: jr.s -march=octeon -32 -mfp64 -EB -mdmx RUN_OBJCOPY +#source: jr.s -mips32r2 -32 -mfpxx -EB +#source: jr.s -mips32r2 -32 -mfp64 -mno-odd-spreg -mmsa -EB +#source: jr.s -mips2 -32 -mfpxx -mips16 -EB RUN_OBJCOPY +#ld: -melf32btsmip -e 0 +#objcopy_objects: -R .MIPS.abiflags +#objdump: -p + +[^:]*: file format elf32-tradbigmips + +Program Header: +0x70000003 off 0x000000.. vaddr 0x004000.. paddr 0x004000.. align 2\*\*3 + filesz 0x00000018 memsz 0x00000018 flags r-- +#... + LOAD off 0x00000000 vaddr 0x00400000 paddr 0x00400000 align 2\*\*16 + filesz 0x00000... memsz 0x00000... flags r-x +private flags = 8c8b1100: \[abi=O32\] \[mips64r2\] \[mdmx\] \[mips16\] \[32bitmode\] + +MIPS ABI Flags Version: 0 + +ISA: MIPS64r2 +GPR size: 32 +CPR1 size: 128 +CPR2 size: 0 +FP ABI: Hard float \(32-bit CPU, 64-bit FPU\) +ISA Extension: Cavium Networks Octeon +ASEs: + MDMX ASE + MSA ASE + MIPS16 ASE +FLAGS 1: 0000000. +FLAGS 2: 00000000 + diff --git a/ld/testsuite/ld-mips-elf/abiflags-strip5-ph.d b/ld/testsuite/ld-mips-elf/abiflags-strip5-ph.d new file mode 100644 index 0000000..bde7096 --- /dev/null +++ b/ld/testsuite/ld-mips-elf/abiflags-strip5-ph.d @@ -0,0 +1,33 @@ +#source: jr.s -mips32r2 -32 -mfpxx -EB +#source: jr.s -mips32r2 -32 -mfp64 -mmsa -EB +#source: jr.s -march=octeon -32 -mfp64 -EB -mdmx RUN_OBJCOPY +#source: jr.s -mips2 -32 -mips16 -mfpxx -EB RUN_OBJCOPY +#ld: -melf32btsmip -e 0 +#objcopy_objects: -R .MIPS.abiflags +#objdump: -p + +[^:]*: file format elf32-tradbigmips + +Program Header: +0x70000003 off 0x000000.. vaddr 0x004000.. paddr 0x004000.. align 2\*\*3 + filesz 0x00000018 memsz 0x00000018 flags r-- +#... + LOAD off 0x00000000 vaddr 0x00400000 paddr 0x00400000 align 2\*\*16 + filesz 0x00000... memsz 0x00000... flags r-x +private flags = 8c8b1100: \[abi=O32\] \[mips64r2\] \[mdmx\] \[mips16\] \[32bitmode\] + +MIPS ABI Flags Version: 0 + +ISA: MIPS64r2 +GPR size: 32 +CPR1 size: 128 +CPR2 size: 0 +FP ABI: Hard float \(32-bit CPU, 64-bit FPU\) +ISA Extension: Cavium Networks Octeon +ASEs: + MDMX ASE + MSA ASE + MIPS16 ASE +FLAGS 1: 0000000. +FLAGS 2: 00000000 + diff --git a/ld/testsuite/ld-mips-elf/abiflags-strip6-ph.d b/ld/testsuite/ld-mips-elf/abiflags-strip6-ph.d new file mode 100644 index 0000000..3abb336 --- /dev/null +++ b/ld/testsuite/ld-mips-elf/abiflags-strip6-ph.d @@ -0,0 +1,29 @@ +#source: jr.s -mips32r3 -32 -EB RUN_OBJCOPY +#source: jr.s -mips32r2 -32 -EB +#ld: -melf32btsmip -e 0 +#objcopy_objects: -R .MIPS.abiflags +#objdump: -p + +[^:]*: file format elf32-tradbigmips + +Program Header: +0x70000003 off 0x000000.. vaddr 0x004000.. paddr 0x004000.. align 2\*\*3 + filesz 0x00000018 memsz 0x00000018 flags r-- +#... + LOAD off 0x00000000 vaddr 0x00400000 paddr 0x00400000 align 2\*\*16 + filesz 0x000000.. memsz 0x000000.. flags r-x +private flags = 70001000: \[abi=O32\] \[mips32r2\] \[not 32bitmode\] + +MIPS ABI Flags Version: 0 + +ISA: MIPS32r2 +GPR size: 32 +CPR1 size: 32 +CPR2 size: 0 +FP ABI: Hard float \(double precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 0000000. +FLAGS 2: 00000000 + diff --git a/ld/testsuite/ld-mips-elf/abiflags-strip7-ph.d b/ld/testsuite/ld-mips-elf/abiflags-strip7-ph.d new file mode 100644 index 0000000..d8f5dc5 --- /dev/null +++ b/ld/testsuite/ld-mips-elf/abiflags-strip7-ph.d @@ -0,0 +1,29 @@ +#source: jr.s -mips32r3 -32 -EB +#source: jr.s -mips32r2 -32 -EB RUN_OBJCOPY +#ld: -melf32btsmip -e 0 +#objcopy_objects: -R .MIPS.abiflags +#objdump: -p + +[^:]*: file format elf32-tradbigmips + +Program Header: +0x70000003 off 0x000000.. vaddr 0x004000.. paddr 0x004000.. align 2\*\*3 + filesz 0x00000018 memsz 0x00000018 flags r-- +#... + LOAD off 0x00000000 vaddr 0x00400000 paddr 0x00400000 align 2\*\*16 + filesz 0x000000.. memsz 0x000000.. flags r-x +private flags = 70001000: \[abi=O32\] \[mips32r2\] \[not 32bitmode\] + +MIPS ABI Flags Version: 0 + +ISA: MIPS32r3 +GPR size: 32 +CPR1 size: 32 +CPR2 size: 0 +FP ABI: Hard float \(double precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 0000000. +FLAGS 2: 00000000 + diff --git a/ld/testsuite/ld-mips-elf/abiflags-strip8-ph.d b/ld/testsuite/ld-mips-elf/abiflags-strip8-ph.d new file mode 100644 index 0000000..840dc59 --- /dev/null +++ b/ld/testsuite/ld-mips-elf/abiflags-strip8-ph.d @@ -0,0 +1,29 @@ +#source: jr.s -mips32r2 -32 -mfpxx -EB +#source: jr.s -mips32r2 -32 -mfp64 -EB RUN_OBJCOPY +#ld: -melf32btsmip -e 0 +#objcopy_objects: -R .gnu.attributes +#objdump: -p + +[^:]*: file format elf32-tradbigmips + +Program Header: +0x70000003 off 0x000000.. vaddr 0x004000.. paddr 0x004000.. align 2\*\*3 + filesz 0x00000018 memsz 0x00000018 flags r-- +#... + LOAD off 0x00000000 vaddr 0x00400000 paddr 0x00400000 align 2\*\*16 + filesz 0x000000.. memsz 0x000000.. flags r-x +private flags = 70001000: \[abi=O32\] \[mips32r2\] \[not 32bitmode\] + +MIPS ABI Flags Version: 0 + +ISA: MIPS32r2 +GPR size: 32 +CPR1 size: 64 +CPR2 size: 0 +FP ABI: Hard float \(32-bit CPU, 64-bit FPU\) +ISA Extension: None +ASEs: + None +FLAGS 1: 0000000. +FLAGS 2: 00000000 + diff --git a/ld/testsuite/ld-mips-elf/abiflags-strip9-ph.d b/ld/testsuite/ld-mips-elf/abiflags-strip9-ph.d new file mode 100644 index 0000000..f42961b --- /dev/null +++ b/ld/testsuite/ld-mips-elf/abiflags-strip9-ph.d @@ -0,0 +1,29 @@ +#source: jr.s -mips32r2 -32 -mfpxx -EB +#source: jr.s -mips32r2 -32 -mfp64 -mno-odd-spreg -EB RUN_OBJCOPY +#ld: -melf32btsmip -e 0 +#objcopy_objects: -R .gnu.attributes +#objdump: -p + +[^:]*: file format elf32-tradbigmips + +Program Header: +0x70000003 off 0x000000.. vaddr 0x004000.. paddr 0x004000.. align 2\*\*3 + filesz 0x00000018 memsz 0x00000018 flags r-- +#... + LOAD off 0x00000000 vaddr 0x00400000 paddr 0x00400000 align 2\*\*16 + filesz 0x000000.. memsz 0x000000.. flags r-x +private flags = 70001000: \[abi=O32\] \[mips32r2\] \[not 32bitmode\] + +MIPS ABI Flags Version: 0 + +ISA: MIPS32r2 +GPR size: 32 +CPR1 size: 64 +CPR2 size: 0 +FP ABI: Hard float compat \(32-bit CPU, 64-bit FPU\) +ISA Extension: None +ASEs: + None +FLAGS 1: 0000000. +FLAGS 2: 00000000 + diff --git a/ld/testsuite/ld-mips-elf/attr-gnu-4-0-n32-ph.d b/ld/testsuite/ld-mips-elf/attr-gnu-4-0-n32-ph.d new file mode 100644 index 0000000..0fb6988 --- /dev/null +++ b/ld/testsuite/ld-mips-elf/attr-gnu-4-0-n32-ph.d @@ -0,0 +1,26 @@ +#source: attr-gnu-4-0.s -mips3 -n32 -EB +#ld: -melf32btsmipn32 -e 0 +#objdump: -p + +[^:]*: file format elf32-ntradbigmips + +Program Header: +0x70000003 off 0x000000.. vaddr 0x100000.. paddr 0x100000.. align 2\*\*3 + filesz 0x00000018 memsz 0x00000018 flags r-- +#... + LOAD off 0x00000000 vaddr 0x10000000 paddr 0x10000000 align 2\*\*16 + filesz 0x000000.. memsz 0x000000.. flags r-- +private flags = 20000020: \[abi=N32\] \[mips3\] \[not 32bitmode\] + +MIPS ABI Flags Version: 0 + +ISA: MIPS3 +GPR size: 64 +CPR1 size: 64 +CPR2 size: 0 +FP ABI: Hard or soft float +ISA Extension: None +ASEs: + None +FLAGS 1: 0000000. +FLAGS 2: 00000000 diff --git a/ld/testsuite/ld-mips-elf/attr-gnu-4-0-n64-ph.d b/ld/testsuite/ld-mips-elf/attr-gnu-4-0-n64-ph.d new file mode 100644 index 0000000..f276025 --- /dev/null +++ b/ld/testsuite/ld-mips-elf/attr-gnu-4-0-n64-ph.d @@ -0,0 +1,25 @@ +#source: attr-gnu-4-0.s -mips3 -64 -EB +#ld: -melf64btsmip -e 0 +#objdump: -p + +[^:]*: file format elf64-tradbigmips + +Program Header: +0x70000003 off 0x00000000000000b0 vaddr 0x00000001200000b0 paddr 0x00000001200000b0 align 2\*\*3 + filesz 0x0000000000000018 memsz 0x0000000000000018 flags r-- + LOAD off 0x0000000000000000 vaddr 0x0000000120000000 paddr 0x0000000120000000 align 2\*\*16 + filesz 0x00000000000000.. memsz 0x00000000000000.. flags r-- +private flags = 20000000: \[abi=64\] \[mips3\] \[not 32bitmode\] + +MIPS ABI Flags Version: 0 + +ISA: MIPS3 +GPR size: 64 +CPR1 size: 64 +CPR2 size: 0 +FP ABI: Hard or soft float +ISA Extension: None +ASEs: + None +FLAGS 1: 0000000. +FLAGS 2: 00000000 diff --git a/ld/testsuite/ld-mips-elf/attr-gnu-4-0-ph.d b/ld/testsuite/ld-mips-elf/attr-gnu-4-0-ph.d new file mode 100644 index 0000000..eb33a70 --- /dev/null +++ b/ld/testsuite/ld-mips-elf/attr-gnu-4-0-ph.d @@ -0,0 +1,26 @@ +#source: attr-gnu-4-0.s -mips32r2 -32 -EB +#ld: -melf32btsmip -e 0 +#objdump: -p + +[^:]*: file format elf32-tradbigmips + +Program Header: +0x70000003 off 0x000000.. vaddr 0x004000.. paddr 0x004000.. align 2\*\*3 + filesz 0x00000018 memsz 0x00000018 flags r-- +#... + LOAD off 0x00000000 vaddr 0x00400000 paddr 0x00400000 align 2\*\*16 + filesz 0x000000.. memsz 0x000000.. flags r-- +private flags = 70001000: \[abi=O32\] \[mips32r2\] \[not 32bitmode\] + +MIPS ABI Flags Version: 0 + +ISA: .* +GPR size: 32 +CPR1 size: 32 +CPR2 size: 0 +FP ABI: Hard or soft float +ISA Extension: None +ASEs: + None +FLAGS 1: 0000000. +FLAGS 2: 00000000 diff --git a/ld/testsuite/ld-mips-elf/attr-gnu-4-00.d b/ld/testsuite/ld-mips-elf/attr-gnu-4-00.d index 32bc319..d86eda4 100644 --- a/ld/testsuite/ld-mips-elf/attr-gnu-4-00.d +++ b/ld/testsuite/ld-mips-elf/attr-gnu-4-00.d @@ -2,5 +2,16 @@ #source: attr-gnu-4-0.s #ld: -r #readelf: -A -#target: mips*-*-* +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Hard or soft float +ISA Extension: None +ASEs: + None +FLAGS 1: 0000000. +FLAGS 2: 00000000 diff --git a/ld/testsuite/ld-mips-elf/attr-gnu-4-01.d b/ld/testsuite/ld-mips-elf/attr-gnu-4-01.d index 7a5c7a1..ffc16c3 100644 --- a/ld/testsuite/ld-mips-elf/attr-gnu-4-01.d +++ b/ld/testsuite/ld-mips-elf/attr-gnu-4-01.d @@ -2,8 +2,20 @@ #source: attr-gnu-4-1.s #ld: -r #readelf: -A -#target: mips*-*-* Attribute Section: gnu File Attributes Tag_GNU_MIPS_ABI_FP: Hard float \(double precision\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Hard float \(double precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 0000000. +FLAGS 2: 00000000 diff --git a/ld/testsuite/ld-mips-elf/attr-gnu-4-02.d b/ld/testsuite/ld-mips-elf/attr-gnu-4-02.d index f29d5d5..3d1a2eb 100644 --- a/ld/testsuite/ld-mips-elf/attr-gnu-4-02.d +++ b/ld/testsuite/ld-mips-elf/attr-gnu-4-02.d @@ -2,8 +2,20 @@ #source: attr-gnu-4-2.s #ld: -r #readelf: -A -#target: mips*-*-* Attribute Section: gnu File Attributes Tag_GNU_MIPS_ABI_FP: Hard float \(single precision\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Hard float \(single precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 0000000. +FLAGS 2: 00000000 diff --git a/ld/testsuite/ld-mips-elf/attr-gnu-4-03.d b/ld/testsuite/ld-mips-elf/attr-gnu-4-03.d index e571e13..116b6f1 100644 --- a/ld/testsuite/ld-mips-elf/attr-gnu-4-03.d +++ b/ld/testsuite/ld-mips-elf/attr-gnu-4-03.d @@ -1,9 +1,22 @@ #source: attr-gnu-4-0.s +#as: -msoft-float #source: attr-gnu-4-3.s #ld: -r #readelf: -A -#target: mips*-*-* Attribute Section: gnu File Attributes Tag_GNU_MIPS_ABI_FP: Soft float + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Soft float +ISA Extension: None +ASEs: + None +FLAGS 1: 0000000. +FLAGS 2: 00000000 diff --git a/ld/testsuite/ld-mips-elf/attr-gnu-4-04.d b/ld/testsuite/ld-mips-elf/attr-gnu-4-04.d index f8dee5c..628daee 100644 --- a/ld/testsuite/ld-mips-elf/attr-gnu-4-04.d +++ b/ld/testsuite/ld-mips-elf/attr-gnu-4-04.d @@ -1,9 +1,5 @@ #source: attr-gnu-4-0.s -#source: attr-gnu-4-4.s +#source: attr-gnu-4-4.s -W #ld: -r -#readelf: -A -#target: mips*-*-* - -Attribute Section: gnu -File Attributes - Tag_GNU_MIPS_ABI_FP: Hard float \(MIPS32r2 64-bit FPU\) +#error: \A[^\n]*: [^\n]* linking -mfp64 module with previous -mfp32 modules\n +#error: [^\n]*: failed to merge target specific data of file [^\n]*\.o\Z diff --git a/ld/testsuite/ld-mips-elf/attr-gnu-4-05.d b/ld/testsuite/ld-mips-elf/attr-gnu-4-05.d index 6856df0..46b94805 100644 --- a/ld/testsuite/ld-mips-elf/attr-gnu-4-05.d +++ b/ld/testsuite/ld-mips-elf/attr-gnu-4-05.d @@ -1,9 +1,21 @@ -#source: attr-gnu-4-0.s -#source: attr-gnu-4-5.s -#ld: -r +#source: attr-gnu-4-0.s -32 -EB +#source: attr-gnu-4-5.s -32 -EB +#ld: -r -melf32btsmip #readelf: -A -#target: mips*-*-* Attribute Section: gnu File Attributes - Tag_GNU_MIPS_ABI_FP: \?\?\? \(5\) + Tag_GNU_MIPS_ABI_FP: Hard float \(32-bit CPU, Any FPU\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: 32 +CPR1 size: 32 +CPR2 size: 0 +FP ABI: Hard float \(32-bit CPU, Any FPU\) +ISA Extension: None +ASEs: + None +FLAGS 1: 0000000. +FLAGS 2: 00000000 diff --git a/ld/testsuite/ld-mips-elf/attr-gnu-4-06.d b/ld/testsuite/ld-mips-elf/attr-gnu-4-06.d new file mode 100644 index 0000000..c23c0dc --- /dev/null +++ b/ld/testsuite/ld-mips-elf/attr-gnu-4-06.d @@ -0,0 +1,21 @@ +#source: attr-gnu-4-0.s -32 -EB +#source: attr-gnu-4-6.s -32 -EB +#ld: -r -melf32btsmip +#readelf: -A + +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float \(32-bit CPU, 64-bit FPU\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: 32 +CPR1 size: .* +CPR2 size: 0 +FP ABI: Hard float \(32-bit CPU, 64-bit FPU\) +ISA Extension: None +ASEs: + None +FLAGS 1: 0000000. +FLAGS 2: 00000000 diff --git a/ld/testsuite/ld-mips-elf/attr-gnu-4-07.d b/ld/testsuite/ld-mips-elf/attr-gnu-4-07.d new file mode 100644 index 0000000..040c06f --- /dev/null +++ b/ld/testsuite/ld-mips-elf/attr-gnu-4-07.d @@ -0,0 +1,21 @@ +#source: attr-gnu-4-0.s -32 -EB +#source: attr-gnu-4-7.s -32 -EB +#ld: -r -melf32btsmip +#readelf: -A + +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float compat \(32-bit CPU, 64-bit FPU\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: 32 +CPR1 size: .* +CPR2 size: 0 +FP ABI: Hard float compat \(32-bit CPU, 64-bit FPU\) +ISA Extension: None +ASEs: + None +FLAGS 1: 0000000. +FLAGS 2: 00000000 diff --git a/ld/testsuite/ld-mips-elf/attr-gnu-4-08.d b/ld/testsuite/ld-mips-elf/attr-gnu-4-08.d new file mode 100644 index 0000000..3ce25cd --- /dev/null +++ b/ld/testsuite/ld-mips-elf/attr-gnu-4-08.d @@ -0,0 +1,21 @@ +#source: attr-gnu-4-0.s +#source: attr-gnu-4-8.s -W +#ld: -r +#readelf: -A + +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: \?\?\? \(8\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: \?\?\? \(8\) +ISA Extension: None +ASEs: + None +FLAGS 1: 0000000. +FLAGS 2: 00000000 diff --git a/ld/testsuite/ld-mips-elf/attr-gnu-4-1-n32-ph.d b/ld/testsuite/ld-mips-elf/attr-gnu-4-1-n32-ph.d new file mode 100644 index 0000000..d83c859 --- /dev/null +++ b/ld/testsuite/ld-mips-elf/attr-gnu-4-1-n32-ph.d @@ -0,0 +1,26 @@ +#source: empty.s -mips3 -n32 -EB +#ld: -melf32btsmipn32 -e 0 +#objdump: -p + +[^:]*: file format elf32-ntradbigmips + +Program Header: +0x70000003 off 0x000000.. vaddr 0x100000.. paddr 0x100000.. align 2\*\*3 + filesz 0x00000018 memsz 0x00000018 flags r-- +#... + LOAD off 0x00000000 vaddr 0x10000000 paddr 0x10000000 align 2\*\*16 + filesz 0x000000.. memsz 0x000000.. flags r-- +private flags = 20000020: \[abi=N32\] \[mips3\] \[not 32bitmode\] + +MIPS ABI Flags Version: 0 + +ISA: MIPS3 +GPR size: 64 +CPR1 size: 64 +CPR2 size: 0 +FP ABI: Hard float \(double precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 0000000. +FLAGS 2: 00000000 diff --git a/ld/testsuite/ld-mips-elf/attr-gnu-4-1-n64-ph.d b/ld/testsuite/ld-mips-elf/attr-gnu-4-1-n64-ph.d new file mode 100644 index 0000000..157f3e6 --- /dev/null +++ b/ld/testsuite/ld-mips-elf/attr-gnu-4-1-n64-ph.d @@ -0,0 +1,25 @@ +#source: empty.s -mips3 -64 -EB +#ld: -melf64btsmip -e 0 +#objdump: -p + +[^:]*: file format elf64-tradbigmips + +Program Header: +0x70000003 off 0x00000000000000b0 vaddr 0x00000001200000b0 paddr 0x00000001200000b0 align 2\*\*3 + filesz 0x0000000000000018 memsz 0x0000000000000018 flags r-- + LOAD off 0x0000000000000000 vaddr 0x0000000120000000 paddr 0x0000000120000000 align 2\*\*16 + filesz 0x00000000000000.. memsz 0x00000000000000.. flags r-- +private flags = 20000000: \[abi=64\] \[mips3\] \[not 32bitmode\] + +MIPS ABI Flags Version: 0 + +ISA: MIPS3 +GPR size: 64 +CPR1 size: 64 +CPR2 size: 0 +FP ABI: Hard float \(double precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 0000000. +FLAGS 2: 00000000 diff --git a/ld/testsuite/ld-mips-elf/attr-gnu-4-1-ph.d b/ld/testsuite/ld-mips-elf/attr-gnu-4-1-ph.d new file mode 100644 index 0000000..7aacd65 --- /dev/null +++ b/ld/testsuite/ld-mips-elf/attr-gnu-4-1-ph.d @@ -0,0 +1,26 @@ +#source: empty.s -mips32r2 -32 -mfp32 -EB +#ld: -melf32btsmip -e 0 +#objdump: -p + +[^:]*: file format elf32-tradbigmips + +Program Header: +0x70000003 off 0x000000.. vaddr 0x004000.. paddr 0x004000.. align 2\*\*3 + filesz 0x00000018 memsz 0x00000018 flags r-- +#... + LOAD off 0x00000000 vaddr 0x00400000 paddr 0x00400000 align 2\*\*16 + filesz 0x000000.. memsz 0x000000.. flags r-- +private flags = 70001000: \[abi=O32\] \[mips32r2\] \[not 32bitmode\] + +MIPS ABI Flags Version: 0 + +ISA: MIPS32r2 +GPR size: 32 +CPR1 size: 32 +CPR2 size: 0 +FP ABI: Hard float \(double precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 0000000. +FLAGS 2: 00000000 diff --git a/ld/testsuite/ld-mips-elf/attr-gnu-4-10.d b/ld/testsuite/ld-mips-elf/attr-gnu-4-10.d index 7661963..0abd9d1 100644 --- a/ld/testsuite/ld-mips-elf/attr-gnu-4-10.d +++ b/ld/testsuite/ld-mips-elf/attr-gnu-4-10.d @@ -1,9 +1,42 @@ -#source: attr-gnu-4-1.s -#source: attr-gnu-4-0.s -#ld: -r -#readelf: -A -#target: mips*-*-* +#source: attr-gnu-4-1.s -EB -32 +#source: attr-gnu-4-0.s -EB -32 +#ld: -r -melf32btsmip +#readelf: -hA + +ELF Header: + Magic: 7f 45 4c 46 01 02 01 00 00 00 00 00 00 00 00 00.* + Class: ELF32 + Data: 2's complement, big endian + Version: 1 \(current\) + OS/ABI: UNIX - System V + ABI Version: 0 + Type: REL \(Relocatable file\) + Machine: MIPS R3000 + Version: 0x1 + Entry point address: 0x0 + Start of program headers: 0 \(bytes into file\) + Start of section headers: ... \(bytes into file\) + Flags: .* + Size of this header: 52 \(bytes\) + Size of program headers: 0 \(bytes\) + Number of program headers: 0 + Size of section headers: 40 \(bytes\) + Number of section headers: 11 + Section header string table index: 8 Attribute Section: gnu File Attributes Tag_GNU_MIPS_ABI_FP: Hard float \(double precision\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Hard float \(double precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 0000000. +FLAGS 2: 00000000 diff --git a/ld/testsuite/ld-mips-elf/attr-gnu-4-11.d b/ld/testsuite/ld-mips-elf/attr-gnu-4-11.d index f70306b..f456096 100644 --- a/ld/testsuite/ld-mips-elf/attr-gnu-4-11.d +++ b/ld/testsuite/ld-mips-elf/attr-gnu-4-11.d @@ -2,8 +2,20 @@ #source: attr-gnu-4-1.s #ld: -r #readelf: -A -#target: mips*-*-* Attribute Section: gnu File Attributes Tag_GNU_MIPS_ABI_FP: Hard float \(double precision\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Hard float \(double precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 0000000. +FLAGS 2: 00000000 diff --git a/ld/testsuite/ld-mips-elf/attr-gnu-4-12.d b/ld/testsuite/ld-mips-elf/attr-gnu-4-12.d index c0eace6..b1b0760 100644 --- a/ld/testsuite/ld-mips-elf/attr-gnu-4-12.d +++ b/ld/testsuite/ld-mips-elf/attr-gnu-4-12.d @@ -2,4 +2,3 @@ #source: attr-gnu-4-2.s #ld: -r #warning: Warning: .* uses -mdouble-float \(set by .*\), .* uses -msingle-float -#target: mips*-*-* diff --git a/ld/testsuite/ld-mips-elf/attr-gnu-4-13.d b/ld/testsuite/ld-mips-elf/attr-gnu-4-13.d index cb30f7a..c9bf544 100644 --- a/ld/testsuite/ld-mips-elf/attr-gnu-4-13.d +++ b/ld/testsuite/ld-mips-elf/attr-gnu-4-13.d @@ -2,4 +2,3 @@ #source: attr-gnu-4-3.s #ld: -r #warning: Warning: .* uses -mhard-float \(set by .*\), .* uses -msoft-float -#target: mips*-*-* diff --git a/ld/testsuite/ld-mips-elf/attr-gnu-4-14.d b/ld/testsuite/ld-mips-elf/attr-gnu-4-14.d index bde387b..58cfd24 100644 --- a/ld/testsuite/ld-mips-elf/attr-gnu-4-14.d +++ b/ld/testsuite/ld-mips-elf/attr-gnu-4-14.d @@ -1,5 +1,6 @@ #source: attr-gnu-4-1.s -#source: attr-gnu-4-4.s +#source: attr-gnu-4-4.s -W #ld: -r -#warning: Warning: .* uses -mdouble-float \(set by .*\), .* uses -mips32r2 -mfp64 -#target: mips*-*-* +#error: \A[^\n]*: Warning: .* uses -mdouble-float \(set by .*\), .* uses -mips32r2 -mfp64 \(12 callee-saved\)\n +#error: [^\n]*: [^\n]* linking -mfp64 module with previous -mfp32 modules\n +#error: [^\n]*: failed to merge target specific data of file [^\n]*\.o\Z diff --git a/ld/testsuite/ld-mips-elf/attr-gnu-4-15.d b/ld/testsuite/ld-mips-elf/attr-gnu-4-15.d index b19645f..29d2eb9 100644 --- a/ld/testsuite/ld-mips-elf/attr-gnu-4-15.d +++ b/ld/testsuite/ld-mips-elf/attr-gnu-4-15.d @@ -1,10 +1,21 @@ -#source: attr-gnu-4-1.s -#source: attr-gnu-4-5.s -#ld: -r +#source: attr-gnu-4-1.s -32 -EB +#source: attr-gnu-4-5.s -32 -EB +#ld: -r -melf32btsmip #readelf: -A -#warning: Warning: .* uses -mdouble-float \(set by .*\), .* uses unknown floating point ABI 5 -#target: mips*-*-* Attribute Section: gnu File Attributes Tag_GNU_MIPS_ABI_FP: Hard float \(double precision\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: 32 +CPR1 size: 32 +CPR2 size: 0 +FP ABI: Hard float \(double precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 0000000. +FLAGS 2: 00000000 diff --git a/ld/testsuite/ld-mips-elf/attr-gnu-4-16.d b/ld/testsuite/ld-mips-elf/attr-gnu-4-16.d new file mode 100644 index 0000000..1e55b05 --- /dev/null +++ b/ld/testsuite/ld-mips-elf/attr-gnu-4-16.d @@ -0,0 +1,22 @@ +#source: attr-gnu-4-1.s -32 -EB +#source: attr-gnu-4-6.s -32 -EB +#ld: -r -melf32btsmip +#readelf: -A +#warning: Warning: .* uses -mdouble-float \(set by .*\), .* uses -mgp32 -mfp64 + +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float \(double precision\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Hard float \(double precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 0000000. +FLAGS 2: 00000000 diff --git a/ld/testsuite/ld-mips-elf/attr-gnu-4-17.d b/ld/testsuite/ld-mips-elf/attr-gnu-4-17.d new file mode 100644 index 0000000..f72eb0b --- /dev/null +++ b/ld/testsuite/ld-mips-elf/attr-gnu-4-17.d @@ -0,0 +1,22 @@ +#source: attr-gnu-4-1.s -32 -EB +#source: attr-gnu-4-7.s -32 -EB +#ld: -r -melf32btsmip +#readelf: -A +#warning: Warning: .* uses -mdouble-float \(set by .*\), .* uses -mgp32 -mfp64 -mno-odd-spreg + +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float \(double precision\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Hard float \(double precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 0000000. +FLAGS 2: 00000000 diff --git a/ld/testsuite/ld-mips-elf/attr-gnu-4-18.d b/ld/testsuite/ld-mips-elf/attr-gnu-4-18.d new file mode 100644 index 0000000..f911f56 --- /dev/null +++ b/ld/testsuite/ld-mips-elf/attr-gnu-4-18.d @@ -0,0 +1,22 @@ +#source: attr-gnu-4-1.s +#source: attr-gnu-4-8.s -W +#ld: -r +#readelf: -A +#warning: Warning: .* uses -mdouble-float \(set by .*\), .* uses unknown floating point ABI 8 + +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float \(double precision\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Hard float \(double precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 0000000. +FLAGS 2: 00000000 diff --git a/ld/testsuite/ld-mips-elf/attr-gnu-4-2-n32-ph.d b/ld/testsuite/ld-mips-elf/attr-gnu-4-2-n32-ph.d new file mode 100644 index 0000000..5a04804 --- /dev/null +++ b/ld/testsuite/ld-mips-elf/attr-gnu-4-2-n32-ph.d @@ -0,0 +1,26 @@ +#source: empty.s -mips3 -n32 -msingle-float -EB +#ld: -melf32btsmipn32 -e 0 +#objdump: -p + +[^:]*: file format elf32-ntradbigmips + +Program Header: +0x70000003 off 0x000000.. vaddr 0x100000.. paddr 0x100000.. align 2\*\*3 + filesz 0x00000018 memsz 0x00000018 flags r-- +#... + LOAD off 0x00000000 vaddr 0x10000000 paddr 0x10000000 align 2\*\*16 + filesz 0x000000.. memsz 0x000000.. flags r-- +private flags = 20000020: \[abi=N32\] \[mips3\] \[not 32bitmode\] + +MIPS ABI Flags Version: 0 + +ISA: MIPS3 +GPR size: 64 +CPR1 size: 64 +CPR2 size: 0 +FP ABI: Hard float \(single precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 0000000. +FLAGS 2: 00000000 diff --git a/ld/testsuite/ld-mips-elf/attr-gnu-4-2-n64-ph.d b/ld/testsuite/ld-mips-elf/attr-gnu-4-2-n64-ph.d new file mode 100644 index 0000000..88b4ff9 --- /dev/null +++ b/ld/testsuite/ld-mips-elf/attr-gnu-4-2-n64-ph.d @@ -0,0 +1,25 @@ +#source: empty.s -mips3 -64 -msingle-float -EB +#ld: -melf64btsmip -e 0 +#objdump: -p + +[^:]*: file format elf64-tradbigmips + +Program Header: +0x70000003 off 0x00000000000000b0 vaddr 0x00000001200000b0 paddr 0x00000001200000b0 align 2\*\*3 + filesz 0x0000000000000018 memsz 0x0000000000000018 flags r-- + LOAD off 0x0000000000000000 vaddr 0x0000000120000000 paddr 0x0000000120000000 align 2\*\*16 + filesz 0x00000000000000.. memsz 0x00000000000000.. flags r-- +private flags = 20000000: \[abi=64\] \[mips3\] \[not 32bitmode\] + +MIPS ABI Flags Version: 0 + +ISA: MIPS3 +GPR size: 64 +CPR1 size: 64 +CPR2 size: 0 +FP ABI: Hard float \(single precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 0000000. +FLAGS 2: 00000000 diff --git a/ld/testsuite/ld-mips-elf/attr-gnu-4-2-ph.d b/ld/testsuite/ld-mips-elf/attr-gnu-4-2-ph.d new file mode 100644 index 0000000..509834c --- /dev/null +++ b/ld/testsuite/ld-mips-elf/attr-gnu-4-2-ph.d @@ -0,0 +1,26 @@ +#source: empty.s -mips32r2 -32 -msingle-float -EB +#ld: -melf32btsmip -e 0 +#objdump: -p + +[^:]*: file format elf32-tradbigmips + +Program Header: +0x70000003 off 0x000000.. vaddr 0x004000.. paddr 0x004000.. align 2\*\*3 + filesz 0x00000018 memsz 0x00000018 flags r-- +#... + LOAD off 0x00000000 vaddr 0x00400000 paddr 0x00400000 align 2\*\*16 + filesz 0x000000.. memsz 0x000000.. flags r-- +private flags = 70001000: \[abi=O32\] \[mips32r2\] \[not 32bitmode\] + +MIPS ABI Flags Version: 0 + +ISA: MIPS32r2 +GPR size: 32 +CPR1 size: 32 +CPR2 size: 0 +FP ABI: Hard float \(single precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 0000000. +FLAGS 2: 00000000 diff --git a/ld/testsuite/ld-mips-elf/attr-gnu-4-2.s b/ld/testsuite/ld-mips-elf/attr-gnu-4-2.s index 54ebf4e..4021bed 100644 --- a/ld/testsuite/ld-mips-elf/attr-gnu-4-2.s +++ b/ld/testsuite/ld-mips-elf/attr-gnu-4-2.s @@ -1 +1,2 @@ +.module singlefloat .gnu_attribute 4,2 diff --git a/ld/testsuite/ld-mips-elf/attr-gnu-4-20.d b/ld/testsuite/ld-mips-elf/attr-gnu-4-20.d index 3620069..1cedafa 100644 --- a/ld/testsuite/ld-mips-elf/attr-gnu-4-20.d +++ b/ld/testsuite/ld-mips-elf/attr-gnu-4-20.d @@ -2,8 +2,20 @@ #source: attr-gnu-4-0.s #ld: -r #readelf: -A -#target: mips*-*-* Attribute Section: gnu File Attributes Tag_GNU_MIPS_ABI_FP: Hard float \(single precision\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Hard float \(single precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 0000000. +FLAGS 2: 00000000 diff --git a/ld/testsuite/ld-mips-elf/attr-gnu-4-21.d b/ld/testsuite/ld-mips-elf/attr-gnu-4-21.d index 68a006f..0081c72 100644 --- a/ld/testsuite/ld-mips-elf/attr-gnu-4-21.d +++ b/ld/testsuite/ld-mips-elf/attr-gnu-4-21.d @@ -2,4 +2,3 @@ #source: attr-gnu-4-1.s #ld: -r #warning: Warning: .* uses -msingle-float \(set by .*\), .* uses -mdouble-float -#target: mips*-*-* diff --git a/ld/testsuite/ld-mips-elf/attr-gnu-4-22.d b/ld/testsuite/ld-mips-elf/attr-gnu-4-22.d index 63edea9..4478fd2 100644 --- a/ld/testsuite/ld-mips-elf/attr-gnu-4-22.d +++ b/ld/testsuite/ld-mips-elf/attr-gnu-4-22.d @@ -2,8 +2,20 @@ #source: attr-gnu-4-2.s #ld: -r #readelf: -A -#target: mips*-*-* Attribute Section: gnu File Attributes Tag_GNU_MIPS_ABI_FP: Hard float \(single precision\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Hard float \(single precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 0000000. +FLAGS 2: 00000000 diff --git a/ld/testsuite/ld-mips-elf/attr-gnu-4-23.d b/ld/testsuite/ld-mips-elf/attr-gnu-4-23.d index e16226f..0b8a6fc 100644 --- a/ld/testsuite/ld-mips-elf/attr-gnu-4-23.d +++ b/ld/testsuite/ld-mips-elf/attr-gnu-4-23.d @@ -2,4 +2,3 @@ #source: attr-gnu-4-3.s #ld: -r #warning: Warning: .* uses -mhard-float \(set by .*\), .* uses -msoft-float -#target: mips*-*-* diff --git a/ld/testsuite/ld-mips-elf/attr-gnu-4-24.d b/ld/testsuite/ld-mips-elf/attr-gnu-4-24.d index c31bb64..e48e5bb 100644 --- a/ld/testsuite/ld-mips-elf/attr-gnu-4-24.d +++ b/ld/testsuite/ld-mips-elf/attr-gnu-4-24.d @@ -1,5 +1,6 @@ #source: attr-gnu-4-2.s -#source: attr-gnu-4-4.s +#source: attr-gnu-4-4.s -W #ld: -r -#warning: Warning: .* uses -msingle-float \(set by .*\), .* uses -mips32r2 -mfp64 -#target: mips*-*-* +#error: \A[^\n]*: Warning: .* uses -msingle-float \(set by .*\), .* uses -mips32r2 -mfp64 \(12 callee-saved\)\n +#error: [^\n]*: [^\n]* linking -mfp64 module with previous -mfp32 modules\n +#error: [^\n]*: failed to merge target specific data of file [^\n]*\.o\Z diff --git a/ld/testsuite/ld-mips-elf/attr-gnu-4-25.d b/ld/testsuite/ld-mips-elf/attr-gnu-4-25.d index b5456ab..711eb10 100644 --- a/ld/testsuite/ld-mips-elf/attr-gnu-4-25.d +++ b/ld/testsuite/ld-mips-elf/attr-gnu-4-25.d @@ -1,10 +1,22 @@ -#source: attr-gnu-4-2.s -#source: attr-gnu-4-5.s -#ld: -r +#source: attr-gnu-4-2.s -32 -EB +#source: attr-gnu-4-5.s -32 -EB +#ld: -r -melf32btsmip #readelf: -A -#warning: Warning: .* uses -msingle-float \(set by .*\), .* uses unknown floating point ABI 5 -#target: mips*-*-* +#warning: Warning: .* uses -msingle-float \(set by .*\), .* uses -mfpxx Attribute Section: gnu File Attributes Tag_GNU_MIPS_ABI_FP: Hard float \(single precision\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Hard float \(single precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 0000000. +FLAGS 2: 00000000 diff --git a/ld/testsuite/ld-mips-elf/attr-gnu-4-26.d b/ld/testsuite/ld-mips-elf/attr-gnu-4-26.d new file mode 100644 index 0000000..2c72a57 --- /dev/null +++ b/ld/testsuite/ld-mips-elf/attr-gnu-4-26.d @@ -0,0 +1,22 @@ +#source: attr-gnu-4-2.s -32 -EB +#source: attr-gnu-4-6.s -32 -EB +#ld: -r -melf32btsmip +#readelf: -A +#warning: Warning: .* uses -msingle-float \(set by .*\), .* uses -mgp32 -mfp64 + +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float \(single precision\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Hard float \(single precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 0000000. +FLAGS 2: 00000000 diff --git a/ld/testsuite/ld-mips-elf/attr-gnu-4-27.d b/ld/testsuite/ld-mips-elf/attr-gnu-4-27.d new file mode 100644 index 0000000..e7aeb1a --- /dev/null +++ b/ld/testsuite/ld-mips-elf/attr-gnu-4-27.d @@ -0,0 +1,22 @@ +#source: attr-gnu-4-2.s -32 -EB +#source: attr-gnu-4-7.s -32 -EB +#ld: -r -melf32btsmip +#readelf: -A +#warning: Warning: .* uses -msingle-float \(set by .*\), .* uses -mgp32 -mfp64 -mno-odd-spreg + +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float \(single precision\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Hard float \(single precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 0000000. +FLAGS 2: 00000000 diff --git a/ld/testsuite/ld-mips-elf/attr-gnu-4-28.d b/ld/testsuite/ld-mips-elf/attr-gnu-4-28.d new file mode 100644 index 0000000..f6e1ea4 --- /dev/null +++ b/ld/testsuite/ld-mips-elf/attr-gnu-4-28.d @@ -0,0 +1,22 @@ +#source: attr-gnu-4-2.s +#source: attr-gnu-4-8.s -W +#ld: -r +#readelf: -A +#warning: Warning: .* uses -msingle-float \(set by .*\), .* uses unknown floating point ABI 8 + +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float \(single precision\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Hard float \(single precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 0000000. +FLAGS 2: 00000000 diff --git a/ld/testsuite/ld-mips-elf/attr-gnu-4-3-n32-ph.d b/ld/testsuite/ld-mips-elf/attr-gnu-4-3-n32-ph.d new file mode 100644 index 0000000..5a04804 --- /dev/null +++ b/ld/testsuite/ld-mips-elf/attr-gnu-4-3-n32-ph.d @@ -0,0 +1,26 @@ +#source: empty.s -mips3 -n32 -msingle-float -EB +#ld: -melf32btsmipn32 -e 0 +#objdump: -p + +[^:]*: file format elf32-ntradbigmips + +Program Header: +0x70000003 off 0x000000.. vaddr 0x100000.. paddr 0x100000.. align 2\*\*3 + filesz 0x00000018 memsz 0x00000018 flags r-- +#... + LOAD off 0x00000000 vaddr 0x10000000 paddr 0x10000000 align 2\*\*16 + filesz 0x000000.. memsz 0x000000.. flags r-- +private flags = 20000020: \[abi=N32\] \[mips3\] \[not 32bitmode\] + +MIPS ABI Flags Version: 0 + +ISA: MIPS3 +GPR size: 64 +CPR1 size: 64 +CPR2 size: 0 +FP ABI: Hard float \(single precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 0000000. +FLAGS 2: 00000000 diff --git a/ld/testsuite/ld-mips-elf/attr-gnu-4-3-n64-ph.d b/ld/testsuite/ld-mips-elf/attr-gnu-4-3-n64-ph.d new file mode 100644 index 0000000..3731dc4 --- /dev/null +++ b/ld/testsuite/ld-mips-elf/attr-gnu-4-3-n64-ph.d @@ -0,0 +1,25 @@ +#source: empty.s -mips3 -64 -msoft-float -EB +#ld: -melf64btsmip -e 0 +#objdump: -p + +[^:]*: file format elf64-tradbigmips + +Program Header: +0x70000003 off 0x00000000000000b0 vaddr 0x00000001200000b0 paddr 0x00000001200000b0 align 2\*\*3 + filesz 0x0000000000000018 memsz 0x0000000000000018 flags r-- + LOAD off 0x0000000000000000 vaddr 0x0000000120000000 paddr 0x0000000120000000 align 2\*\*16 + filesz 0x00000000000000.. memsz 0x00000000000000.. flags r-- +private flags = 20000000: \[abi=64\] \[mips3\] \[not 32bitmode\] + +MIPS ABI Flags Version: 0 + +ISA: MIPS3 +GPR size: 64 +CPR1 size: 0 +CPR2 size: 0 +FP ABI: Soft float +ISA Extension: None +ASEs: + None +FLAGS 1: 0000000. +FLAGS 2: 00000000 diff --git a/ld/testsuite/ld-mips-elf/attr-gnu-4-3-ph.d b/ld/testsuite/ld-mips-elf/attr-gnu-4-3-ph.d new file mode 100644 index 0000000..edeb6b1 --- /dev/null +++ b/ld/testsuite/ld-mips-elf/attr-gnu-4-3-ph.d @@ -0,0 +1,26 @@ +#source: empty.s -mips32r2 -32 -msoft-float -EB +#ld: -melf32btsmip -e 0 +#objdump: -p + +[^:]*: file format elf32-tradbigmips + +Program Header: +0x70000003 off 0x000000.. vaddr 0x004000.. paddr 0x004000.. align 2\*\*3 + filesz 0x00000018 memsz 0x00000018 flags r-- +#... + LOAD off 0x00000000 vaddr 0x00400000 paddr 0x00400000 align 2\*\*16 + filesz 0x000000.. memsz 0x000000.. flags r-- +private flags = 70001000: \[abi=O32\] \[mips32r2\] \[not 32bitmode\] + +MIPS ABI Flags Version: 0 + +ISA: MIPS32r2 +GPR size: 32 +CPR1 size: 0 +CPR2 size: 0 +FP ABI: Soft float +ISA Extension: None +ASEs: + None +FLAGS 1: 0000000. +FLAGS 2: 00000000 diff --git a/ld/testsuite/ld-mips-elf/attr-gnu-4-3.s b/ld/testsuite/ld-mips-elf/attr-gnu-4-3.s index 32e5f5d..0ba0b80 100644 --- a/ld/testsuite/ld-mips-elf/attr-gnu-4-3.s +++ b/ld/testsuite/ld-mips-elf/attr-gnu-4-3.s @@ -1 +1,2 @@ +.module softfloat .gnu_attribute 4,3 diff --git a/ld/testsuite/ld-mips-elf/attr-gnu-4-30.d b/ld/testsuite/ld-mips-elf/attr-gnu-4-30.d index cdc108e..5dedc07 100644 --- a/ld/testsuite/ld-mips-elf/attr-gnu-4-30.d +++ b/ld/testsuite/ld-mips-elf/attr-gnu-4-30.d @@ -2,8 +2,20 @@ #source: attr-gnu-4-0.s #ld: -r #readelf: -A -#target: mips*-*-* Attribute Section: gnu File Attributes Tag_GNU_MIPS_ABI_FP: Soft float + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Soft float +ISA Extension: None +ASEs: + None +FLAGS 1: 0000000. +FLAGS 2: 00000000 diff --git a/ld/testsuite/ld-mips-elf/attr-gnu-4-31.d b/ld/testsuite/ld-mips-elf/attr-gnu-4-31.d index b749e82..4fcf76f 100644 --- a/ld/testsuite/ld-mips-elf/attr-gnu-4-31.d +++ b/ld/testsuite/ld-mips-elf/attr-gnu-4-31.d @@ -2,4 +2,3 @@ #source: attr-gnu-4-1.s #ld: -r #warning: Warning: .* uses -msoft-float \(set by .*\), .* uses -mhard-float -#target: mips*-*-* diff --git a/ld/testsuite/ld-mips-elf/attr-gnu-4-32.d b/ld/testsuite/ld-mips-elf/attr-gnu-4-32.d index d0fd7bc..0d663c2 100644 --- a/ld/testsuite/ld-mips-elf/attr-gnu-4-32.d +++ b/ld/testsuite/ld-mips-elf/attr-gnu-4-32.d @@ -2,4 +2,3 @@ #source: attr-gnu-4-2.s #ld: -r #warning: Warning: .* uses -msoft-float \(set by .*\), .* uses -mhard-float -#target: mips*-*-* diff --git a/ld/testsuite/ld-mips-elf/attr-gnu-4-33.d b/ld/testsuite/ld-mips-elf/attr-gnu-4-33.d index 39eebb3..2dcd25b 100644 --- a/ld/testsuite/ld-mips-elf/attr-gnu-4-33.d +++ b/ld/testsuite/ld-mips-elf/attr-gnu-4-33.d @@ -2,8 +2,20 @@ #source: attr-gnu-4-3.s #ld: -r #readelf: -A -#target: mips*-*-* Attribute Section: gnu File Attributes Tag_GNU_MIPS_ABI_FP: Soft float + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Soft float +ISA Extension: None +ASEs: + None +FLAGS 1: 0000000. +FLAGS 2: 00000000 diff --git a/ld/testsuite/ld-mips-elf/attr-gnu-4-34.d b/ld/testsuite/ld-mips-elf/attr-gnu-4-34.d index be24523..314515a 100644 --- a/ld/testsuite/ld-mips-elf/attr-gnu-4-34.d +++ b/ld/testsuite/ld-mips-elf/attr-gnu-4-34.d @@ -1,5 +1,6 @@ #source: attr-gnu-4-3.s -#source: attr-gnu-4-4.s +#source: attr-gnu-4-4.s -W #ld: -r -#warning: Warning: .* uses -msoft-float \(set by .*\), .* uses -mhard-float -#target: mips*-*-* +#error: \A[^\n]*: Warning: .* uses -msoft-float \(set by .*\), .* uses -mhard-float\n +#error: [^\n]*: [^\n]* linking -mfp64 module with previous -mfp32 modules\n +#error: [^\n]*: failed to merge target specific data of file [^\n]*\.o\Z diff --git a/ld/testsuite/ld-mips-elf/attr-gnu-4-35.d b/ld/testsuite/ld-mips-elf/attr-gnu-4-35.d index bcb1e02..19fbce4 100644 --- a/ld/testsuite/ld-mips-elf/attr-gnu-4-35.d +++ b/ld/testsuite/ld-mips-elf/attr-gnu-4-35.d @@ -1,10 +1,22 @@ -#source: attr-gnu-4-3.s -#source: attr-gnu-4-5.s -#ld: -r +#source: attr-gnu-4-3.s -32 -EB +#source: attr-gnu-4-5.s -32 -EB +#ld: -r -melf32btsmip #readelf: -A -#warning: Warning: .* uses -msoft-float \(set by .*\), .* uses unknown floating point ABI 5 -#target: mips*-*-* +#warning: Warning: .* uses -msoft-float \(set by .*\), .* uses -mhard-float Attribute Section: gnu File Attributes Tag_GNU_MIPS_ABI_FP: Soft float + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Soft float +ISA Extension: None +ASEs: + None +FLAGS 1: 0000000. +FLAGS 2: 00000000 diff --git a/ld/testsuite/ld-mips-elf/attr-gnu-4-36.d b/ld/testsuite/ld-mips-elf/attr-gnu-4-36.d new file mode 100644 index 0000000..de7393b --- /dev/null +++ b/ld/testsuite/ld-mips-elf/attr-gnu-4-36.d @@ -0,0 +1,22 @@ +#source: attr-gnu-4-3.s -32 -EB +#source: attr-gnu-4-6.s -32 -EB +#ld: -r -melf32btsmip +#readelf: -A +#warning: Warning: .* uses -msoft-float \(set by .*\), .* uses -mhard-float + +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Soft float + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Soft float +ISA Extension: None +ASEs: + None +FLAGS 1: 0000000. +FLAGS 2: 00000000 diff --git a/ld/testsuite/ld-mips-elf/attr-gnu-4-37.d b/ld/testsuite/ld-mips-elf/attr-gnu-4-37.d new file mode 100644 index 0000000..0702cb5 --- /dev/null +++ b/ld/testsuite/ld-mips-elf/attr-gnu-4-37.d @@ -0,0 +1,22 @@ +#source: attr-gnu-4-3.s -32 -EB +#source: attr-gnu-4-7.s -32 -EB +#ld: -r -melf32btsmip +#readelf: -A +#warning: Warning: .* uses -msoft-float \(set by .*\), .* uses -mhard-float + +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Soft float + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Soft float +ISA Extension: None +ASEs: + None +FLAGS 1: 0000000. +FLAGS 2: 00000000 diff --git a/ld/testsuite/ld-mips-elf/attr-gnu-4-38.d b/ld/testsuite/ld-mips-elf/attr-gnu-4-38.d new file mode 100644 index 0000000..014c52d --- /dev/null +++ b/ld/testsuite/ld-mips-elf/attr-gnu-4-38.d @@ -0,0 +1,22 @@ +#source: attr-gnu-4-3.s +#source: attr-gnu-4-8.s -W +#ld: -r +#readelf: -A +#warning: Warning: .* uses -msoft-float \(set by .*\), .* uses unknown floating point ABI 8 + +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Soft float + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Soft float +ISA Extension: None +ASEs: + None +FLAGS 1: 0000000. +FLAGS 2: 00000000 diff --git a/ld/testsuite/ld-mips-elf/attr-gnu-4-4-ph.d b/ld/testsuite/ld-mips-elf/attr-gnu-4-4-ph.d new file mode 100644 index 0000000..13f5267 --- /dev/null +++ b/ld/testsuite/ld-mips-elf/attr-gnu-4-4-ph.d @@ -0,0 +1,26 @@ +#source: attr-gnu-4-4.s -mips32r2 -32 -EB -W +#ld: -melf32btsmip -e 0 +#objdump: -p + +[^:]*: file format elf32-tradbigmips + +Program Header: +0x70000003 off 0x000000.. vaddr 0x004000.. paddr 0x004000.. align 2\*\*3 + filesz 0x00000018 memsz 0x00000018 flags r-- +#... + LOAD off 0x00000000 vaddr 0x00400000 paddr 0x00400000 align 2\*\*16 + filesz 0x000000.. memsz 0x000000.. flags r-- +private flags = 70001200: \[abi=O32\] \[mips32r2\] \[old fp64\] \[not 32bitmode\] + +MIPS ABI Flags Version: 0 + +ISA: MIPS32r2 +GPR size: 32 +CPR1 size: 32 +CPR2 size: 0 +FP ABI: Hard float \(MIPS32r2 64-bit FPU 12 callee-saved\) +ISA Extension: None +ASEs: + None +FLAGS 1: 0000000. +FLAGS 2: 00000000 diff --git a/ld/testsuite/ld-mips-elf/attr-gnu-4-40.d b/ld/testsuite/ld-mips-elf/attr-gnu-4-40.d index 27d4571..6aa22b9 100644 --- a/ld/testsuite/ld-mips-elf/attr-gnu-4-40.d +++ b/ld/testsuite/ld-mips-elf/attr-gnu-4-40.d @@ -1,9 +1,5 @@ -#source: attr-gnu-4-4.s +#source: attr-gnu-4-4.s -W #source: attr-gnu-4-0.s #ld: -r -#readelf: -A -#target: mips*-*-* - -Attribute Section: gnu -File Attributes - Tag_GNU_MIPS_ABI_FP: Hard float \(MIPS32r2 64-bit FPU\) +#error: \A[^\n]*: [^\n]* linking -mfp32 module with previous -mfp64 modules\n +#error: [^\n]*: failed to merge target specific data of file [^\n]*\.o\Z diff --git a/ld/testsuite/ld-mips-elf/attr-gnu-4-41.d b/ld/testsuite/ld-mips-elf/attr-gnu-4-41.d index b652983..7c61365 100644 --- a/ld/testsuite/ld-mips-elf/attr-gnu-4-41.d +++ b/ld/testsuite/ld-mips-elf/attr-gnu-4-41.d @@ -1,5 +1,6 @@ -#source: attr-gnu-4-4.s +#source: attr-gnu-4-4.s -W #source: attr-gnu-4-1.s #ld: -r -#warning: Warning: .* uses -mips32r2 -mfp64 \(set by .*\), .* uses -mdouble-float -#target: mips*-*-* +#error: \A[^\n]*: Warning: .* uses -mips32r2 -mfp64 \(12 callee-saved\) \(set by .*\), .* uses -mdouble-float\n +#error: [^\n]*: [^\n]* linking -mfp32 module with previous -mfp64 modules\n +#error: [^\n]*: failed to merge target specific data of file [^\n]*\.o\Z diff --git a/ld/testsuite/ld-mips-elf/attr-gnu-4-42.d b/ld/testsuite/ld-mips-elf/attr-gnu-4-42.d index a1b79ea..dad0421 100644 --- a/ld/testsuite/ld-mips-elf/attr-gnu-4-42.d +++ b/ld/testsuite/ld-mips-elf/attr-gnu-4-42.d @@ -1,5 +1,6 @@ -#source: attr-gnu-4-4.s +#source: attr-gnu-4-4.s -W #source: attr-gnu-4-2.s #ld: -r -#warning: Warning: .* uses -mips32r2 -mfp64 \(set by .*\), .* uses -msingle-float -#target: mips*-*-* +#error: \A[^\n]*: Warning: .* uses -mips32r2 -mfp64 \(12 callee-saved\) \(set by .*\), .* uses -msingle-float\n +#error: [^\n]*: [^\n]* linking -mfp32 module with previous -mfp64 modules\n +#error: [^\n]*: failed to merge target specific data of file [^\n]*\.o\Z diff --git a/ld/testsuite/ld-mips-elf/attr-gnu-4-43.d b/ld/testsuite/ld-mips-elf/attr-gnu-4-43.d index 23f40c6..f30c18e 100644 --- a/ld/testsuite/ld-mips-elf/attr-gnu-4-43.d +++ b/ld/testsuite/ld-mips-elf/attr-gnu-4-43.d @@ -1,5 +1,6 @@ -#source: attr-gnu-4-4.s +#source: attr-gnu-4-4.s -W #source: attr-gnu-4-3.s #ld: -r -#warning: Warning: .* uses -mhard-float \(set by .*\), .* uses -msoft-float -#target: mips*-*-* +#error: \A[^\n]*: Warning: .* uses -mhard-float \(set by .*\), .* uses -msoft-float\n +#error: [^\n]*: [^\n]* linking -mfp32 module with previous -mfp64 modules\n +#error: [^\n]*: failed to merge target specific data of file [^\n]*\.o\Z diff --git a/ld/testsuite/ld-mips-elf/attr-gnu-4-44.d b/ld/testsuite/ld-mips-elf/attr-gnu-4-44.d index 68b03a0..2599a90 100644 --- a/ld/testsuite/ld-mips-elf/attr-gnu-4-44.d +++ b/ld/testsuite/ld-mips-elf/attr-gnu-4-44.d @@ -1,9 +1,21 @@ -#source: attr-gnu-4-4.s -#source: attr-gnu-4-4.s +#source: attr-gnu-4-4.s -W +#source: attr-gnu-4-4.s -W #ld: -r #readelf: -A -#target: mips*-*-* Attribute Section: gnu File Attributes - Tag_GNU_MIPS_ABI_FP: Hard float \(MIPS32r2 64-bit FPU\) + Tag_GNU_MIPS_ABI_FP: Hard float \(MIPS32r2 64-bit FPU 12 callee-saved\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Hard float \(MIPS32r2 64-bit FPU 12 callee-saved\) +ISA Extension: None +ASEs: + None +FLAGS 1: 0000000. +FLAGS 2: 00000000 diff --git a/ld/testsuite/ld-mips-elf/attr-gnu-4-45.d b/ld/testsuite/ld-mips-elf/attr-gnu-4-45.d index 0d1b079..d21e66f 100644 --- a/ld/testsuite/ld-mips-elf/attr-gnu-4-45.d +++ b/ld/testsuite/ld-mips-elf/attr-gnu-4-45.d @@ -1,10 +1,6 @@ -#source: attr-gnu-4-4.s -#source: attr-gnu-4-5.s -#ld: -r -#readelf: -A -#warning: Warning: .* uses -mips32r2 -mfp64 \(set by .*\), .* uses unknown floating point ABI 5 -#target: mips*-*-* - -Attribute Section: gnu -File Attributes - Tag_GNU_MIPS_ABI_FP: Hard float \(MIPS32r2 64-bit FPU\) +#source: attr-gnu-4-4.s -W -32 -EB +#source: attr-gnu-4-5.s -32 -EB +#ld: -r -melf32btsmip +#error: \A[^\n]*: Warning: .* uses -mips32r2 -mfp64 \(12 callee-saved\) \(set by .*\), .* uses -mfpxx\n +#error: [^\n]*: [^\n]* linking -mfp32 module with previous -mfp64 modules\n +#error: [^\n]*: failed to merge target specific data of file [^\n]*\.o\Z diff --git a/ld/testsuite/ld-mips-elf/attr-gnu-4-46.d b/ld/testsuite/ld-mips-elf/attr-gnu-4-46.d new file mode 100644 index 0000000..fb8baf8 --- /dev/null +++ b/ld/testsuite/ld-mips-elf/attr-gnu-4-46.d @@ -0,0 +1,6 @@ +#source: attr-gnu-4-4.s -W -32 -EB +#source: attr-gnu-4-6.s -32 -EB +#ld: -r -melf32btsmip +#error: \A[^\n]*: Warning: .* uses -mips32r2 -mfp64 \(12 callee-saved\) \(set by .*\), .* uses -mgp32 -mfp64\n +#error: [^\n]*: [^\n]* linking -mfp32 module with previous -mfp64 modules\n +#error: [^\n]*: failed to merge target specific data of file [^\n]*\.o\Z diff --git a/ld/testsuite/ld-mips-elf/attr-gnu-4-47.d b/ld/testsuite/ld-mips-elf/attr-gnu-4-47.d new file mode 100644 index 0000000..889e0e1 --- /dev/null +++ b/ld/testsuite/ld-mips-elf/attr-gnu-4-47.d @@ -0,0 +1,6 @@ +#source: attr-gnu-4-4.s -W -32 -EB +#source: attr-gnu-4-7.s -32 -EB +#ld: -r -melf32btsmip +#error: \A[^\n]*: Warning: .* uses -mips32r2 -mfp64 \(12 callee-saved\) \(set by .*\), .* uses -mgp32 -mfp64 -mno-odd-spreg\n +#error: [^\n]*: [^\n]* linking -mfp32 module with previous -mfp64 modules\n +#error: [^\n]*: failed to merge target specific data of file [^\n]*\.o\Z diff --git a/ld/testsuite/ld-mips-elf/attr-gnu-4-48.d b/ld/testsuite/ld-mips-elf/attr-gnu-4-48.d new file mode 100644 index 0000000..cb4dcb6 --- /dev/null +++ b/ld/testsuite/ld-mips-elf/attr-gnu-4-48.d @@ -0,0 +1,6 @@ +#source: attr-gnu-4-4.s -W +#source: attr-gnu-4-8.s -W +#ld: -r +#error: \A[^\n]*: Warning: .* uses -mips32r2 -mfp64 \(12 callee-saved\) \(set by .*\), .* uses unknown floating point ABI 8\n +#error: [^\n]*: [^\n]* linking -mfp32 module with previous -mfp64 modules\n +#error: [^\n]*: failed to merge target specific data of file [^\n]*\.o\Z diff --git a/ld/testsuite/ld-mips-elf/attr-gnu-4-5-ph.d b/ld/testsuite/ld-mips-elf/attr-gnu-4-5-ph.d new file mode 100644 index 0000000..b68bbf3 --- /dev/null +++ b/ld/testsuite/ld-mips-elf/attr-gnu-4-5-ph.d @@ -0,0 +1,26 @@ +#source: empty.s -mips32r2 -32 -mfpxx -EB +#ld: -melf32btsmip -e 0 +#objdump: -p + +[^:]*: file format elf32-tradbigmips + +Program Header: +0x70000003 off 0x000000.. vaddr 0x004000.. paddr 0x004000.. align 2\*\*3 + filesz 0x00000018 memsz 0x00000018 flags r-- +#... + LOAD off 0x00000000 vaddr 0x00400000 paddr 0x00400000 align 2\*\*16 + filesz 0x000000.. memsz 0x000000.. flags r-- +private flags = 70001000: \[abi=O32\] \[mips32r2\] \[not 32bitmode\] + +MIPS ABI Flags Version: 0 + +ISA: MIPS32r2 +GPR size: 32 +CPR1 size: 32 +CPR2 size: 0 +FP ABI: Hard float \(32-bit CPU, Any FPU\) +ISA Extension: None +ASEs: + None +FLAGS 1: 0000000. +FLAGS 2: 00000000 diff --git a/ld/testsuite/ld-mips-elf/attr-gnu-4-5.s b/ld/testsuite/ld-mips-elf/attr-gnu-4-5.s index b21ec3b..06f6c6f 100644 --- a/ld/testsuite/ld-mips-elf/attr-gnu-4-5.s +++ b/ld/testsuite/ld-mips-elf/attr-gnu-4-5.s @@ -1 +1,3 @@ +.module mips32r2 +.module fp=xx .gnu_attribute 4,5 diff --git a/ld/testsuite/ld-mips-elf/attr-gnu-4-50.d b/ld/testsuite/ld-mips-elf/attr-gnu-4-50.d new file mode 100644 index 0000000..ac848ed --- /dev/null +++ b/ld/testsuite/ld-mips-elf/attr-gnu-4-50.d @@ -0,0 +1,41 @@ +#source: attr-gnu-4-5.s -32 -EB +#source: attr-gnu-4-0.s -32 -EB +#ld: -r -melf32btsmip +#readelf: -hA + +ELF Header: + Magic: 7f 45 4c 46 01 02 01 00 00 00 00 00 00 00 00 00.* + Class: ELF32 + Data: 2's complement, big endian + Version: 1 \(current\) + OS/ABI: UNIX - System V + ABI Version: 0 + Type: REL \(Relocatable file\) + Machine: MIPS R3000 + Version: 0x1 + Entry point address: 0x0 + Start of program headers: 0 \(bytes into file\) + Start of section headers: ... \(bytes into file\) + Flags: 0x70001000, o32, mips32r2 + Size of this header: 52 \(bytes\) + Size of program headers: 0 \(bytes\) + Number of program headers: 0 + Size of section headers: 40 \(bytes\) + Number of section headers: 11 + Section header string table index: 8 +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float \(32-bit CPU, Any FPU\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Hard float \(32-bit CPU, Any FPU\) +ISA Extension: None +ASEs: + None +FLAGS 1: 0000000. +FLAGS 2: 00000000 diff --git a/ld/testsuite/ld-mips-elf/attr-gnu-4-51.d b/ld/testsuite/ld-mips-elf/attr-gnu-4-51.d index e183d54..72ad878 100644 --- a/ld/testsuite/ld-mips-elf/attr-gnu-4-51.d +++ b/ld/testsuite/ld-mips-elf/attr-gnu-4-51.d @@ -1,5 +1,21 @@ -#source: attr-gnu-4-5.s -#source: attr-gnu-4-1.s -#ld: -r -#warning: Warning: .* uses unknown floating point ABI 5 \(set by .*\), .* uses -mdouble-float -#target: mips*-*-* +#source: attr-gnu-4-5.s -32 -EB +#source: attr-gnu-4-1.s -32 -EB +#ld: -r -melf32btsmip +#readelf: -A + +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float \(double precision\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Hard float \(double precision\) +ISA Extension: None +ASEs: + None +FLAGS 1: 0000000. +FLAGS 2: 00000000 diff --git a/ld/testsuite/ld-mips-elf/attr-gnu-4-52.d b/ld/testsuite/ld-mips-elf/attr-gnu-4-52.d new file mode 100644 index 0000000..b36547d --- /dev/null +++ b/ld/testsuite/ld-mips-elf/attr-gnu-4-52.d @@ -0,0 +1,4 @@ +#source: attr-gnu-4-5.s -32 -EB +#source: attr-gnu-4-2.s -32 -EB +#ld: -r -melf32btsmip +#warning: Warning: .* uses -mfpxx \(set by .*\), .* uses -msingle-float diff --git a/ld/testsuite/ld-mips-elf/attr-gnu-4-53.d b/ld/testsuite/ld-mips-elf/attr-gnu-4-53.d new file mode 100644 index 0000000..7312d17 --- /dev/null +++ b/ld/testsuite/ld-mips-elf/attr-gnu-4-53.d @@ -0,0 +1,4 @@ +#source: attr-gnu-4-5.s -32 -EB +#source: attr-gnu-4-3.s -32 -EB +#ld: -r -melf32btsmip +#warning: Warning: .* uses -mhard-float \(set by .*\), .* uses -msoft-float diff --git a/ld/testsuite/ld-mips-elf/attr-gnu-4-54.d b/ld/testsuite/ld-mips-elf/attr-gnu-4-54.d new file mode 100644 index 0000000..a5beaf1 --- /dev/null +++ b/ld/testsuite/ld-mips-elf/attr-gnu-4-54.d @@ -0,0 +1,6 @@ +#source: attr-gnu-4-5.s -32 -EB +#source: attr-gnu-4-4.s -W -32 -EB +#ld: -r -melf32btsmip +#error: \A[^\n]*: Warning: .* uses -mfpxx \(set by .*\), .* uses -mips32r2 -mfp64 \(12 callee-saved\)\n +#error: [^\n]*: [^\n]* linking -mfp64 module with previous -mfp32 modules\n +#error: [^\n]*: failed to merge target specific data of file [^\n]*\.o\Z diff --git a/ld/testsuite/ld-mips-elf/attr-gnu-4-55.d b/ld/testsuite/ld-mips-elf/attr-gnu-4-55.d new file mode 100644 index 0000000..d4569ad --- /dev/null +++ b/ld/testsuite/ld-mips-elf/attr-gnu-4-55.d @@ -0,0 +1,21 @@ +#source: attr-gnu-4-5.s -32 -EB +#source: attr-gnu-4-5.s -32 -EB +#ld: -r -melf32btsmip +#readelf: -A + +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float \(32-bit CPU, Any FPU\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Hard float \(32-bit CPU, Any FPU\) +ISA Extension: None +ASEs: + None +FLAGS 1: 0000000. +FLAGS 2: 00000000 diff --git a/ld/testsuite/ld-mips-elf/attr-gnu-4-56.d b/ld/testsuite/ld-mips-elf/attr-gnu-4-56.d new file mode 100644 index 0000000..d63150d --- /dev/null +++ b/ld/testsuite/ld-mips-elf/attr-gnu-4-56.d @@ -0,0 +1,21 @@ +#source: attr-gnu-4-5.s -32 -EB +#source: attr-gnu-4-6.s -32 -EB +#ld: -r -melf32btsmip +#readelf: -A + +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float \(32-bit CPU, 64-bit FPU\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Hard float \(32-bit CPU, 64-bit FPU\) +ISA Extension: None +ASEs: + None +FLAGS 1: 0000000. +FLAGS 2: 00000000 diff --git a/ld/testsuite/ld-mips-elf/attr-gnu-4-57.d b/ld/testsuite/ld-mips-elf/attr-gnu-4-57.d new file mode 100644 index 0000000..5de1678 --- /dev/null +++ b/ld/testsuite/ld-mips-elf/attr-gnu-4-57.d @@ -0,0 +1,21 @@ +#source: attr-gnu-4-5.s -32 -EB +#source: attr-gnu-4-7.s -32 -EB +#ld: -r -melf32btsmip +#readelf: -A + +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float compat \(32-bit CPU, 64-bit FPU\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Hard float compat \(32-bit CPU, 64-bit FPU\) +ISA Extension: None +ASEs: + None +FLAGS 1: 0000000. +FLAGS 2: 00000000 diff --git a/ld/testsuite/ld-mips-elf/attr-gnu-4-58.d b/ld/testsuite/ld-mips-elf/attr-gnu-4-58.d new file mode 100644 index 0000000..83d6747 --- /dev/null +++ b/ld/testsuite/ld-mips-elf/attr-gnu-4-58.d @@ -0,0 +1,4 @@ +#source: attr-gnu-4-5.s -32 -EB +#source: attr-gnu-4-8.s -W -32 -EB +#ld: -r -melf32btsmip +#warning: Warning: .* uses -mfpxx \(set by .*\), .* uses unknown floating point ABI 8 diff --git a/ld/testsuite/ld-mips-elf/attr-gnu-4-6-ph.d b/ld/testsuite/ld-mips-elf/attr-gnu-4-6-ph.d new file mode 100644 index 0000000..9628991 --- /dev/null +++ b/ld/testsuite/ld-mips-elf/attr-gnu-4-6-ph.d @@ -0,0 +1,26 @@ +#source: empty.s -mips32r2 -32 -mfp64 -EB +#ld: -melf32btsmip -e 0 +#objdump: -p + +[^:]*: file format elf32-tradbigmips + +Program Header: +0x70000003 off 0x000000.. vaddr 0x004000.. paddr 0x004000.. align 2\*\*3 + filesz 0x00000018 memsz 0x00000018 flags r-- +#... + LOAD off 0x00000000 vaddr 0x00400000 paddr 0x00400000 align 2\*\*16 + filesz 0x000000.. memsz 0x000000.. flags r-- +private flags = 70001000: \[abi=O32\] \[mips32r2\] \[not 32bitmode\] + +MIPS ABI Flags Version: 0 + +ISA: MIPS32r2 +GPR size: 32 +CPR1 size: 64 +CPR2 size: 0 +FP ABI: Hard float \(32-bit CPU, 64-bit FPU\) +ISA Extension: None +ASEs: + None +FLAGS 1: 0000000. +FLAGS 2: 00000000 diff --git a/ld/testsuite/ld-mips-elf/attr-gnu-4-6.s b/ld/testsuite/ld-mips-elf/attr-gnu-4-6.s new file mode 100644 index 0000000..adcff8a --- /dev/null +++ b/ld/testsuite/ld-mips-elf/attr-gnu-4-6.s @@ -0,0 +1,4 @@ +.module mips32r2 +.module gp=32 +.module fp=64 +.gnu_attribute 4,6 diff --git a/ld/testsuite/ld-mips-elf/attr-gnu-4-60.d b/ld/testsuite/ld-mips-elf/attr-gnu-4-60.d new file mode 100644 index 0000000..62e6a2c --- /dev/null +++ b/ld/testsuite/ld-mips-elf/attr-gnu-4-60.d @@ -0,0 +1,41 @@ +#source: attr-gnu-4-6.s -32 -EB +#source: attr-gnu-4-0.s -32 -EB +#ld: -r -melf32btsmip +#readelf: -hA + +ELF Header: + Magic: 7f 45 4c 46 01 02 01 00 03 00 00 00 00 00 00 00.* + Class: ELF32 + Data: 2's complement, big endian + Version: 1 \(current\) + OS/ABI: UNIX - System V + ABI Version: 3 + Type: REL \(Relocatable file\) + Machine: MIPS R3000 + Version: 0x1 + Entry point address: 0x0 + Start of program headers: 0 \(bytes into file\) + Start of section headers: ... \(bytes into file\) + Flags: 0x70001000, o32, mips32r2 + Size of this header: 52 \(bytes\) + Size of program headers: 0 \(bytes\) + Number of program headers: 0 + Size of section headers: 40 \(bytes\) + Number of section headers: 11 + Section header string table index: 8 +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float \(32-bit CPU, 64-bit FPU\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Hard float \(32-bit CPU, 64-bit FPU\) +ISA Extension: None +ASEs: + None +FLAGS 1: 0000000. +FLAGS 2: 00000000 diff --git a/ld/testsuite/ld-mips-elf/attr-gnu-4-61.d b/ld/testsuite/ld-mips-elf/attr-gnu-4-61.d new file mode 100644 index 0000000..6e9040c --- /dev/null +++ b/ld/testsuite/ld-mips-elf/attr-gnu-4-61.d @@ -0,0 +1,4 @@ +#source: attr-gnu-4-6.s -32 -EB +#source: attr-gnu-4-1.s -32 -EB +#ld: -r -melf32btsmip +#warning: Warning: .* uses -mgp32 -mfp64 \(set by .*\), .* uses -mdouble-float diff --git a/ld/testsuite/ld-mips-elf/attr-gnu-4-62.d b/ld/testsuite/ld-mips-elf/attr-gnu-4-62.d new file mode 100644 index 0000000..5eec884 --- /dev/null +++ b/ld/testsuite/ld-mips-elf/attr-gnu-4-62.d @@ -0,0 +1,4 @@ +#source: attr-gnu-4-6.s -32 -EB +#source: attr-gnu-4-2.s -32 -EB +#ld: -r -melf32btsmip +#warning: Warning: .* uses -mgp32 -mfp64 \(set by .*\), .* uses -msingle-float diff --git a/ld/testsuite/ld-mips-elf/attr-gnu-4-63.d b/ld/testsuite/ld-mips-elf/attr-gnu-4-63.d new file mode 100644 index 0000000..eb750f3 --- /dev/null +++ b/ld/testsuite/ld-mips-elf/attr-gnu-4-63.d @@ -0,0 +1,4 @@ +#source: attr-gnu-4-6.s -32 -EB +#source: attr-gnu-4-3.s -32 -EB +#ld: -r -melf32btsmip +#warning: Warning: .* uses -mhard-float \(set by .*\), .* uses -msoft-float diff --git a/ld/testsuite/ld-mips-elf/attr-gnu-4-64.d b/ld/testsuite/ld-mips-elf/attr-gnu-4-64.d new file mode 100644 index 0000000..a5dcb7e --- /dev/null +++ b/ld/testsuite/ld-mips-elf/attr-gnu-4-64.d @@ -0,0 +1,6 @@ +#source: attr-gnu-4-6.s -32 -EB +#source: attr-gnu-4-4.s -W -32 -EB +#ld: -r -melf32btsmip +#error: \A[^\n]*: Warning: .* uses -mgp32 -mfp64 \(set by .*\), .* uses -mips32r2 -mfp64 \(12 callee-saved\)\n +#error: [^\n]*: [^\n]* linking -mfp64 module with previous -mfp32 modules\n +#error: [^\n]*: failed to merge target specific data of file [^\n]*\.o\Z diff --git a/ld/testsuite/ld-mips-elf/attr-gnu-4-65.d b/ld/testsuite/ld-mips-elf/attr-gnu-4-65.d new file mode 100644 index 0000000..ccf19b8 --- /dev/null +++ b/ld/testsuite/ld-mips-elf/attr-gnu-4-65.d @@ -0,0 +1,21 @@ +#source: attr-gnu-4-6.s -32 -EB +#source: attr-gnu-4-5.s -32 -EB +#ld: -r -melf32btsmip +#readelf: -A + +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float \(32-bit CPU, 64-bit FPU\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Hard float \(32-bit CPU, 64-bit FPU\) +ISA Extension: None +ASEs: + None +FLAGS 1: 0000000. +FLAGS 2: 00000000 diff --git a/ld/testsuite/ld-mips-elf/attr-gnu-4-66.d b/ld/testsuite/ld-mips-elf/attr-gnu-4-66.d new file mode 100644 index 0000000..552e6d2 --- /dev/null +++ b/ld/testsuite/ld-mips-elf/attr-gnu-4-66.d @@ -0,0 +1,21 @@ +#source: attr-gnu-4-6.s -32 -EB +#source: attr-gnu-4-6.s -32 -EB +#ld: -r -melf32btsmip +#readelf: -A + +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float \(32-bit CPU, 64-bit FPU\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Hard float \(32-bit CPU, 64-bit FPU\) +ISA Extension: None +ASEs: + None +FLAGS 1: 0000000. +FLAGS 2: 00000000 diff --git a/ld/testsuite/ld-mips-elf/attr-gnu-4-67.d b/ld/testsuite/ld-mips-elf/attr-gnu-4-67.d new file mode 100644 index 0000000..171af5b --- /dev/null +++ b/ld/testsuite/ld-mips-elf/attr-gnu-4-67.d @@ -0,0 +1,21 @@ +#source: attr-gnu-4-6.s -32 -EB +#source: attr-gnu-4-7.s -32 -EB +#ld: -r -melf32btsmip +#readelf: -A + +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float \(32-bit CPU, 64-bit FPU\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Hard float \(32-bit CPU, 64-bit FPU\) +ISA Extension: None +ASEs: + None +FLAGS 1: 0000000. +FLAGS 2: 00000000 diff --git a/ld/testsuite/ld-mips-elf/attr-gnu-4-68.d b/ld/testsuite/ld-mips-elf/attr-gnu-4-68.d new file mode 100644 index 0000000..e850b03 --- /dev/null +++ b/ld/testsuite/ld-mips-elf/attr-gnu-4-68.d @@ -0,0 +1,4 @@ +#source: attr-gnu-4-6.s -32 -EB +#source: attr-gnu-4-8.s -W -32 -EB +#ld: -r -melf32btsmip +#warning: Warning: .* uses -mgp32 -mfp64 \(set by .*\), .* uses unknown floating point ABI 8 diff --git a/ld/testsuite/ld-mips-elf/attr-gnu-4-7-ph.d b/ld/testsuite/ld-mips-elf/attr-gnu-4-7-ph.d new file mode 100644 index 0000000..b0245b6 --- /dev/null +++ b/ld/testsuite/ld-mips-elf/attr-gnu-4-7-ph.d @@ -0,0 +1,26 @@ +#source: empty.s -mips32r2 -32 -mfp64 -mno-odd-spreg -EB +#ld: -melf32btsmip -e 0 +#objdump: -p + +[^:]*: file format elf32-tradbigmips + +Program Header: +0x70000003 off 0x000000.. vaddr 0x004000.. paddr 0x004000.. align 2\*\*3 + filesz 0x00000018 memsz 0x00000018 flags r-- +#... + LOAD off 0x00000000 vaddr 0x00400000 paddr 0x00400000 align 2\*\*16 + filesz 0x000000.. memsz 0x000000.. flags r-- +private flags = 70001000: \[abi=O32\] \[mips32r2\] \[not 32bitmode\] + +MIPS ABI Flags Version: 0 + +ISA: MIPS32r2 +GPR size: 32 +CPR1 size: 64 +CPR2 size: 0 +FP ABI: Hard float compat \(32-bit CPU, 64-bit FPU\) +ISA Extension: None +ASEs: + None +FLAGS 1: 0000000. +FLAGS 2: 00000000 diff --git a/ld/testsuite/ld-mips-elf/attr-gnu-4-7.s b/ld/testsuite/ld-mips-elf/attr-gnu-4-7.s new file mode 100644 index 0000000..e79d50b --- /dev/null +++ b/ld/testsuite/ld-mips-elf/attr-gnu-4-7.s @@ -0,0 +1,5 @@ +.module mips32r2 +.module gp=32 +.module fp=64 +.module nooddspreg +.gnu_attribute 4,7 diff --git a/ld/testsuite/ld-mips-elf/attr-gnu-4-70.d b/ld/testsuite/ld-mips-elf/attr-gnu-4-70.d new file mode 100644 index 0000000..784401e --- /dev/null +++ b/ld/testsuite/ld-mips-elf/attr-gnu-4-70.d @@ -0,0 +1,41 @@ +#source: attr-gnu-4-7.s -32 -EB +#source: attr-gnu-4-0.s -32 -EB +#ld: -r -melf32btsmip +#readelf: -hA + +ELF Header: + Magic: 7f 45 4c 46 01 02 01 00 03 00 00 00 00 00 00 00.* + Class: ELF32 + Data: 2's complement, big endian + Version: 1 \(current\) + OS/ABI: UNIX - System V + ABI Version: 3 + Type: REL \(Relocatable file\) + Machine: MIPS R3000 + Version: 0x1 + Entry point address: 0x0 + Start of program headers: 0 \(bytes into file\) + Start of section headers: ... \(bytes into file\) + Flags: 0x70001000, o32, mips32r2 + Size of this header: 52 \(bytes\) + Size of program headers: 0 \(bytes\) + Number of program headers: 0 + Size of section headers: 40 \(bytes\) + Number of section headers: 11 + Section header string table index: 8 +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float compat \(32-bit CPU, 64-bit FPU\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Hard float compat \(32-bit CPU, 64-bit FPU\) +ISA Extension: None +ASEs: + None +FLAGS 1: 0000000. +FLAGS 2: 00000000 diff --git a/ld/testsuite/ld-mips-elf/attr-gnu-4-71.d b/ld/testsuite/ld-mips-elf/attr-gnu-4-71.d new file mode 100644 index 0000000..b61b6c5 --- /dev/null +++ b/ld/testsuite/ld-mips-elf/attr-gnu-4-71.d @@ -0,0 +1,4 @@ +#source: attr-gnu-4-7.s -32 -EB +#source: attr-gnu-4-1.s -32 -EB +#ld: -r -melf32btsmip +#warning: Warning: .* uses -mgp32 -mfp64 -mno-odd-spreg \(set by .*\), .* uses -mdouble-float diff --git a/ld/testsuite/ld-mips-elf/attr-gnu-4-72.d b/ld/testsuite/ld-mips-elf/attr-gnu-4-72.d new file mode 100644 index 0000000..1d7dec5 --- /dev/null +++ b/ld/testsuite/ld-mips-elf/attr-gnu-4-72.d @@ -0,0 +1,4 @@ +#source: attr-gnu-4-7.s -32 -EB +#source: attr-gnu-4-2.s -32 -EB +#ld: -r -melf32btsmip +#warning: Warning: .* uses -mgp32 -mfp64 -mno-odd-spreg \(set by .*\), .* uses -msingle-float diff --git a/ld/testsuite/ld-mips-elf/attr-gnu-4-73.d b/ld/testsuite/ld-mips-elf/attr-gnu-4-73.d new file mode 100644 index 0000000..41c0fdc --- /dev/null +++ b/ld/testsuite/ld-mips-elf/attr-gnu-4-73.d @@ -0,0 +1,4 @@ +#source: attr-gnu-4-7.s -32 -EB +#source: attr-gnu-4-3.s -32 -EB +#ld: -r -melf32btsmip +#warning: Warning: .* uses -mhard-float \(set by .*\), .* uses -msoft-float diff --git a/ld/testsuite/ld-mips-elf/attr-gnu-4-74.d b/ld/testsuite/ld-mips-elf/attr-gnu-4-74.d new file mode 100644 index 0000000..cc9279b --- /dev/null +++ b/ld/testsuite/ld-mips-elf/attr-gnu-4-74.d @@ -0,0 +1,6 @@ +#source: attr-gnu-4-7.s -32 -EB +#source: attr-gnu-4-4.s -W -32 -EB +#ld: -r -melf32btsmip +#error: \A[^\n]*: Warning: .* uses -mgp32 -mfp64 -mno-odd-spreg \(set by .*\), .* uses -mips32r2 -mfp64 \(12 callee-saved\)\n +#error: [^\n]*: [^\n]* linking -mfp64 module with previous -mfp32 modules\n +#error: [^\n]*: failed to merge target specific data of file [^\n]*\.o\Z diff --git a/ld/testsuite/ld-mips-elf/attr-gnu-4-75.d b/ld/testsuite/ld-mips-elf/attr-gnu-4-75.d new file mode 100644 index 0000000..9b0e587 --- /dev/null +++ b/ld/testsuite/ld-mips-elf/attr-gnu-4-75.d @@ -0,0 +1,21 @@ +#source: attr-gnu-4-7.s -32 -EB +#source: attr-gnu-4-5.s -32 -EB +#ld: -r -melf32btsmip +#readelf: -A + +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float compat \(32-bit CPU, 64-bit FPU\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Hard float compat \(32-bit CPU, 64-bit FPU\) +ISA Extension: None +ASEs: + None +FLAGS 1: 0000000. +FLAGS 2: 00000000 diff --git a/ld/testsuite/ld-mips-elf/attr-gnu-4-76.d b/ld/testsuite/ld-mips-elf/attr-gnu-4-76.d new file mode 100644 index 0000000..d8f666b --- /dev/null +++ b/ld/testsuite/ld-mips-elf/attr-gnu-4-76.d @@ -0,0 +1,21 @@ +#source: attr-gnu-4-7.s -32 -EB +#source: attr-gnu-4-6.s -32 -EB +#ld: -r -melf32btsmip +#readelf: -A + +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float \(32-bit CPU, 64-bit FPU\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Hard float \(32-bit CPU, 64-bit FPU\) +ISA Extension: None +ASEs: + None +FLAGS 1: 0000000. +FLAGS 2: 00000000 diff --git a/ld/testsuite/ld-mips-elf/attr-gnu-4-77.d b/ld/testsuite/ld-mips-elf/attr-gnu-4-77.d new file mode 100644 index 0000000..50d0236 --- /dev/null +++ b/ld/testsuite/ld-mips-elf/attr-gnu-4-77.d @@ -0,0 +1,21 @@ +#source: attr-gnu-4-7.s -32 -EB +#source: attr-gnu-4-7.s -32 -EB +#ld: -r -melf32btsmip +#readelf: -A + +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float compat \(32-bit CPU, 64-bit FPU\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Hard float compat \(32-bit CPU, 64-bit FPU\) +ISA Extension: None +ASEs: + None +FLAGS 1: 0000000. +FLAGS 2: 00000000 diff --git a/ld/testsuite/ld-mips-elf/attr-gnu-4-78.d b/ld/testsuite/ld-mips-elf/attr-gnu-4-78.d new file mode 100644 index 0000000..b04ad22 --- /dev/null +++ b/ld/testsuite/ld-mips-elf/attr-gnu-4-78.d @@ -0,0 +1,4 @@ +#source: attr-gnu-4-7.s -32 -EB +#source: attr-gnu-4-8.s -W -32 -EB +#ld: -r -melf32btsmip +#warning: Warning: .* uses -mgp32 -mfp64 -mno-odd-spreg \(set by .*\), .* uses unknown floating point ABI 8 diff --git a/ld/testsuite/ld-mips-elf/attr-gnu-4-8.s b/ld/testsuite/ld-mips-elf/attr-gnu-4-8.s new file mode 100644 index 0000000..79f64f9 --- /dev/null +++ b/ld/testsuite/ld-mips-elf/attr-gnu-4-8.s @@ -0,0 +1 @@ +.gnu_attribute 4,8 diff --git a/ld/testsuite/ld-mips-elf/attr-gnu-4-81.d b/ld/testsuite/ld-mips-elf/attr-gnu-4-81.d new file mode 100644 index 0000000..fd44915 --- /dev/null +++ b/ld/testsuite/ld-mips-elf/attr-gnu-4-81.d @@ -0,0 +1,4 @@ +#source: attr-gnu-4-8.s -W +#source: attr-gnu-4-1.s +#ld: -r +#warning: Warning: .* uses unknown floating point ABI 8 \(set by .*\), .* uses -mdouble-float diff --git a/ld/testsuite/ld-mips-elf/attr-gnu-8-00.d b/ld/testsuite/ld-mips-elf/attr-gnu-8-00.d index 5ee34a1..2f8e5f0 100644 --- a/ld/testsuite/ld-mips-elf/attr-gnu-8-00.d +++ b/ld/testsuite/ld-mips-elf/attr-gnu-8-00.d @@ -2,5 +2,8 @@ #source: attr-gnu-8-0.s #ld: -r #readelf: -A -#target: mips*-*-* +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float \(double precision\) +#pass diff --git a/ld/testsuite/ld-mips-elf/attr-gnu-8-01.d b/ld/testsuite/ld-mips-elf/attr-gnu-8-01.d index 2d44dfe..e2cda33 100644 --- a/ld/testsuite/ld-mips-elf/attr-gnu-8-01.d +++ b/ld/testsuite/ld-mips-elf/attr-gnu-8-01.d @@ -2,8 +2,9 @@ #source: attr-gnu-8-1.s #ld: -r #readelf: -A -#target: mips*-*-* Attribute Section: gnu File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float \(double precision\) Tag_GNU_MIPS_ABI_MSA: 128-bit MSA +#pass diff --git a/ld/testsuite/ld-mips-elf/attr-gnu-8-02.d b/ld/testsuite/ld-mips-elf/attr-gnu-8-02.d index e873d44..54b196f 100644 --- a/ld/testsuite/ld-mips-elf/attr-gnu-8-02.d +++ b/ld/testsuite/ld-mips-elf/attr-gnu-8-02.d @@ -2,8 +2,9 @@ #source: attr-gnu-8-2.s #ld: -r #readelf: -A -#target: mips*-*-* Attribute Section: gnu File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float \(double precision\) Tag_GNU_MIPS_ABI_MSA: \?\?\? \(2\) +#pass diff --git a/ld/testsuite/ld-mips-elf/attr-gnu-8-10.d b/ld/testsuite/ld-mips-elf/attr-gnu-8-10.d index f0e9125..f7c512b 100644 --- a/ld/testsuite/ld-mips-elf/attr-gnu-8-10.d +++ b/ld/testsuite/ld-mips-elf/attr-gnu-8-10.d @@ -2,8 +2,9 @@ #source: attr-gnu-8-0.s #ld: -r #readelf: -A -#target: mips*-*-* Attribute Section: gnu File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float \(double precision\) Tag_GNU_MIPS_ABI_MSA: 128-bit MSA +#pass diff --git a/ld/testsuite/ld-mips-elf/attr-gnu-8-11.d b/ld/testsuite/ld-mips-elf/attr-gnu-8-11.d index 50d518f..be87af4 100644 --- a/ld/testsuite/ld-mips-elf/attr-gnu-8-11.d +++ b/ld/testsuite/ld-mips-elf/attr-gnu-8-11.d @@ -2,8 +2,9 @@ #source: attr-gnu-8-1.s #ld: -r #readelf: -A -#target: mips*-*-* Attribute Section: gnu File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float \(double precision\) Tag_GNU_MIPS_ABI_MSA: 128-bit MSA +#pass diff --git a/ld/testsuite/ld-mips-elf/attr-gnu-8-12.d b/ld/testsuite/ld-mips-elf/attr-gnu-8-12.d index b5392f3..10249d0 100644 --- a/ld/testsuite/ld-mips-elf/attr-gnu-8-12.d +++ b/ld/testsuite/ld-mips-elf/attr-gnu-8-12.d @@ -2,4 +2,3 @@ #source: attr-gnu-8-2.s #ld: -r #warning: Warning: .* uses -mmsa \(set by .*\), .* uses unknown MSA ABI 2 -#target: mips*-*-* diff --git a/ld/testsuite/ld-mips-elf/attr-gnu-8-20.d b/ld/testsuite/ld-mips-elf/attr-gnu-8-20.d index 268d670..05f4da0 100644 --- a/ld/testsuite/ld-mips-elf/attr-gnu-8-20.d +++ b/ld/testsuite/ld-mips-elf/attr-gnu-8-20.d @@ -2,8 +2,9 @@ #source: attr-gnu-8-0.s #ld: -r #readelf: -A -#target: mips*-*-* Attribute Section: gnu File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float \(double precision\) Tag_GNU_MIPS_ABI_MSA: \?\?\? \(2\) +#pass diff --git a/ld/testsuite/ld-mips-elf/attr-gnu-8-21.d b/ld/testsuite/ld-mips-elf/attr-gnu-8-21.d index 0222f03..b8f0e7c 100644 --- a/ld/testsuite/ld-mips-elf/attr-gnu-8-21.d +++ b/ld/testsuite/ld-mips-elf/attr-gnu-8-21.d @@ -2,4 +2,3 @@ #source: attr-gnu-8-1.s #ld: -r #warning: Warning: .* uses unknown MSA ABI 2 \(set by .*\), .* uses -mmsa -#target: mips*-*-* diff --git a/ld/testsuite/ld-mips-elf/attr-gnu-8-22.d b/ld/testsuite/ld-mips-elf/attr-gnu-8-22.d index b781150..908ce4f 100644 --- a/ld/testsuite/ld-mips-elf/attr-gnu-8-22.d +++ b/ld/testsuite/ld-mips-elf/attr-gnu-8-22.d @@ -2,8 +2,9 @@ #source: attr-gnu-8-2.s #ld: -r #readelf: -A -#target: mips*-*-* Attribute Section: gnu File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float \(double precision\) Tag_GNU_MIPS_ABI_MSA: \?\?\? \(2\) +#pass diff --git a/ld/testsuite/ld-mips-elf/compressed-plt-1.ld b/ld/testsuite/ld-mips-elf/compressed-plt-1.ld index 9f15af9..0108d0f 100644 --- a/ld/testsuite/ld-mips-elf/compressed-plt-1.ld +++ b/ld/testsuite/ld-mips-elf/compressed-plt-1.ld @@ -35,4 +35,6 @@ SECTIONS .got : { *(.got) } . = ALIGN(0x1000); .rld_map : { *(.rld_map) } + + /DISCARD/ : { *(.MIPS.abiflags) *(.gnu.attributes) } } diff --git a/ld/testsuite/ld-mips-elf/dyn-sec64.ld b/ld/testsuite/ld-mips-elf/dyn-sec64.ld index 4c6353a..c7af3f4 100644 --- a/ld/testsuite/ld-mips-elf/dyn-sec64.ld +++ b/ld/testsuite/ld-mips-elf/dyn-sec64.ld @@ -20,4 +20,6 @@ SECTIONS HIDDEN (_gp = ALIGN (16) + 0x7ff0); .got : { *(.got) } .data : { *(.data) } + + /DISCARD/ : { *(.MIPS.abiflags) *(.gnu.attributes) } } diff --git a/ld/testsuite/ld-mips-elf/elf-rel-got-n32-embed.d b/ld/testsuite/ld-mips-elf/elf-rel-got-n32-embed.d index d492998..58f23ed 100644 --- a/ld/testsuite/ld-mips-elf/elf-rel-got-n32-embed.d +++ b/ld/testsuite/ld-mips-elf/elf-rel-got-n32-embed.d @@ -1,6 +1,7 @@ #name: MIPS ELF got reloc n32 #as: -march=from-abi -EB -n32 -KPIC -#source: ../../../gas/testsuite/gas/mips/elf-rel-got-n32.s +#objcopy_objects: -R .MIPS.abiflags +#source: ../../../gas/testsuite/gas/mips/elf-rel-got-n32.s RUN_OBJCOPY #ld: #objdump: -D --show-raw-insn diff --git a/ld/testsuite/ld-mips-elf/elf-rel-got-n32.d b/ld/testsuite/ld-mips-elf/elf-rel-got-n32.d index 535a538..174153d 100644 --- a/ld/testsuite/ld-mips-elf/elf-rel-got-n32.d +++ b/ld/testsuite/ld-mips-elf/elf-rel-got-n32.d @@ -1,6 +1,7 @@ #name: MIPS ELF got reloc n32 #as: -march=from-abi -EB -n32 -KPIC -#source: ../../../gas/testsuite/gas/mips/elf-rel-got-n32.s +#objcopy_objects: -R .MIPS.abiflags -K __start +#source: ../../../gas/testsuite/gas/mips/elf-rel-got-n32.s RUN_OBJCOPY #ld: #objdump: -D --show-raw-insn diff --git a/ld/testsuite/ld-mips-elf/elf-rel-got-n64-embed.d b/ld/testsuite/ld-mips-elf/elf-rel-got-n64-embed.d index f2719f0..c55900f 100644 --- a/ld/testsuite/ld-mips-elf/elf-rel-got-n64-embed.d +++ b/ld/testsuite/ld-mips-elf/elf-rel-got-n64-embed.d @@ -1,6 +1,7 @@ #name: MIPS ELF got reloc n64 #as: -march=from-abi -EB -64 -KPIC -#source: ../../../gas/testsuite/gas/mips/elf-rel-got-n64.s +#objcopy_objects: -R .MIPS.abiflags +#source: ../../../gas/testsuite/gas/mips/elf-rel-got-n64.s RUN_OBJCOPY #ld: #objdump: -D --show-raw-insn diff --git a/ld/testsuite/ld-mips-elf/elf-rel-got-n64-linux.d b/ld/testsuite/ld-mips-elf/elf-rel-got-n64-linux.d index c1c3326..8e2822d 100644 --- a/ld/testsuite/ld-mips-elf/elf-rel-got-n64-linux.d +++ b/ld/testsuite/ld-mips-elf/elf-rel-got-n64-linux.d @@ -1,6 +1,7 @@ #name: MIPS ELF got reloc n64 #as: -march=from-abi -EB -64 -KPIC -#source: ../../../gas/testsuite/gas/mips/elf-rel-got-n64.s +#objcopy_objects: -R .MIPS.abiflags +#source: ../../../gas/testsuite/gas/mips/elf-rel-got-n64.s RUN_OBJCOPY #ld: #objdump: -D --show-raw-insn diff --git a/ld/testsuite/ld-mips-elf/elf-rel-got-n64.d b/ld/testsuite/ld-mips-elf/elf-rel-got-n64.d index 55dd7ae..492f76e 100644 --- a/ld/testsuite/ld-mips-elf/elf-rel-got-n64.d +++ b/ld/testsuite/ld-mips-elf/elf-rel-got-n64.d @@ -1,6 +1,7 @@ #name: MIPS ELF got reloc n64 #as: -march=from-abi -EB -64 -KPIC -#source: ../../../gas/testsuite/gas/mips/elf-rel-got-n64.s +#objcopy_objects: -R .MIPS.abiflags +#source: ../../../gas/testsuite/gas/mips/elf-rel-got-n64.s RUN_OBJCOPY #ld: #objdump: -D --show-raw-insn diff --git a/ld/testsuite/ld-mips-elf/elf-rel-xgot-n32-embed.d b/ld/testsuite/ld-mips-elf/elf-rel-xgot-n32-embed.d index a0bef16..d6c2e85 100644 --- a/ld/testsuite/ld-mips-elf/elf-rel-xgot-n32-embed.d +++ b/ld/testsuite/ld-mips-elf/elf-rel-xgot-n32-embed.d @@ -1,6 +1,7 @@ #name: MIPS ELF xgot reloc n32 #as: -march=from-abi -EB -n32 -KPIC -xgot -#source: ../../../gas/testsuite/gas/mips/elf-rel-got-n32.s +#objcopy_objects: -R .MIPS.abiflags -K __start +#source: ../../../gas/testsuite/gas/mips/elf-rel-got-n32.s RUN_OBJCOPY #ld: #objdump: -D --show-raw-insn diff --git a/ld/testsuite/ld-mips-elf/elf-rel-xgot-n32.d b/ld/testsuite/ld-mips-elf/elf-rel-xgot-n32.d index a909aa9..b202e92 100644 --- a/ld/testsuite/ld-mips-elf/elf-rel-xgot-n32.d +++ b/ld/testsuite/ld-mips-elf/elf-rel-xgot-n32.d @@ -1,6 +1,7 @@ #name: MIPS ELF xgot reloc n32 #as: -march=from-abi -EB -n32 -KPIC -xgot -#source: ../../../gas/testsuite/gas/mips/elf-rel-got-n32.s +#objcopy_objects: -R .MIPS.abiflags -K __start +#source: ../../../gas/testsuite/gas/mips/elf-rel-got-n32.s RUN_OBJCOPY #ld: #objdump: -D --show-raw-insn diff --git a/ld/testsuite/ld-mips-elf/elf-rel-xgot-n64-embed.d b/ld/testsuite/ld-mips-elf/elf-rel-xgot-n64-embed.d index 271257f..bdacf78 100644 --- a/ld/testsuite/ld-mips-elf/elf-rel-xgot-n64-embed.d +++ b/ld/testsuite/ld-mips-elf/elf-rel-xgot-n64-embed.d @@ -1,6 +1,7 @@ #name: MIPS ELF xgot reloc n64 #as: -march=from-abi -EB -64 -KPIC -xgot -#source: ../../../gas/testsuite/gas/mips/elf-rel-got-n64.s +#objcopy_objects: -R .MIPS.abiflags -K __start +#source: ../../../gas/testsuite/gas/mips/elf-rel-got-n64.s RUN_OBJCOPY #ld: #objdump: -D --show-raw-insn diff --git a/ld/testsuite/ld-mips-elf/elf-rel-xgot-n64-linux.d b/ld/testsuite/ld-mips-elf/elf-rel-xgot-n64-linux.d index 4579700..fd21487 100644 --- a/ld/testsuite/ld-mips-elf/elf-rel-xgot-n64-linux.d +++ b/ld/testsuite/ld-mips-elf/elf-rel-xgot-n64-linux.d @@ -1,6 +1,7 @@ #name: MIPS ELF xgot reloc n64 #as: -march=from-abi -EB -64 -KPIC -xgot -#source: ../../../gas/testsuite/gas/mips/elf-rel-got-n64.s +#objcopy_objects: -R .MIPS.abiflags -K __start +#source: ../../../gas/testsuite/gas/mips/elf-rel-got-n64.s RUN_OBJCOPY #ld: #objdump: -D --show-raw-insn diff --git a/ld/testsuite/ld-mips-elf/elf-rel-xgot-n64.d b/ld/testsuite/ld-mips-elf/elf-rel-xgot-n64.d index 72ac666..348b718 100644 --- a/ld/testsuite/ld-mips-elf/elf-rel-xgot-n64.d +++ b/ld/testsuite/ld-mips-elf/elf-rel-xgot-n64.d @@ -1,6 +1,7 @@ #name: MIPS ELF xgot reloc n64 #as: -march=from-abi -EB -64 -KPIC -xgot -#source: ../../../gas/testsuite/gas/mips/elf-rel-got-n64.s +#objcopy_objects: -R .MIPS.abiflags -K __start +#source: ../../../gas/testsuite/gas/mips/elf-rel-got-n64.s RUN_OBJCOPY #ld: #objdump: -D --show-raw-insn diff --git a/ld/testsuite/ld-mips-elf/empty.s b/ld/testsuite/ld-mips-elf/empty.s new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/ld/testsuite/ld-mips-elf/empty.s diff --git a/ld/testsuite/ld-mips-elf/got-dump-1.ld b/ld/testsuite/ld-mips-elf/got-dump-1.ld index ba228f5..e8a40f1 100644 --- a/ld/testsuite/ld-mips-elf/got-dump-1.ld +++ b/ld/testsuite/ld-mips-elf/got-dump-1.ld @@ -16,4 +16,6 @@ SECTIONS .data : { *(.data) } HIDDEN (_gp = ALIGN (16) + 0x7ff0); .got : { *(.got) } + + /DISCARD/ : { *(.MIPS.abiflags) *(.gnu.attributes) } } diff --git a/ld/testsuite/ld-mips-elf/got-dump-2.ld b/ld/testsuite/ld-mips-elf/got-dump-2.ld index 0e237de..d7ba691 100644 --- a/ld/testsuite/ld-mips-elf/got-dump-2.ld +++ b/ld/testsuite/ld-mips-elf/got-dump-2.ld @@ -15,4 +15,6 @@ SECTIONS .data : { *(.data) } HIDDEN (_gp = ALIGN (16) + 0x7ff0); .got : { *(.got) } + + /DISCARD/ : { *(.MIPS.abiflags) *(.gnu.attributes) } } diff --git a/ld/testsuite/ld-mips-elf/got-page-1.ld b/ld/testsuite/ld-mips-elf/got-page-1.ld index 3197c9b..cfe7c1f 100644 --- a/ld/testsuite/ld-mips-elf/got-page-1.ld +++ b/ld/testsuite/ld-mips-elf/got-page-1.ld @@ -22,7 +22,7 @@ SECTIONS . = ALIGN (0x400); .bss : { *(.bss .bss.*) } - /DISCARD/ : { *(.reginfo) } + /DISCARD/ : { *(.reginfo) *(.MIPS.abiflags) } } VERSION diff --git a/ld/testsuite/ld-mips-elf/jalx-2.dd b/ld/testsuite/ld-mips-elf/jalx-2.dd index 50ebdb8..69985f6 100644 --- a/ld/testsuite/ld-mips-elf/jalx-2.dd +++ b/ld/testsuite/ld-mips-elf/jalx-2.dd @@ -28,7 +28,7 @@ Disassembly of section \.text: 4400034: f89e 0020 sw a0,32\(s8\) 4400038: f8be 0024 sw a1,36\(s8\) 440003c: 41a2 0440 lui v0,0x440 - 4400040: 3082 0260 addiu a0,v0,608 + 4400040: 3082 0280 addiu a0,v0,640 4400044: f620 004c jal 4400098 <printf@micromipsplt> 4400048: 0000 0000 nop 440004c: f620 0010 jal 4400020 <internal_function> diff --git a/ld/testsuite/ld-mips-elf/mips-dyn.ld b/ld/testsuite/ld-mips-elf/mips-dyn.ld index b931e1b..bd2802fc 100644 --- a/ld/testsuite/ld-mips-elf/mips-dyn.ld +++ b/ld/testsuite/ld-mips-elf/mips-dyn.ld @@ -219,5 +219,5 @@ SECTIONS .debug_varnames 0 : { *(.debug_varnames) } .gptab.sdata : { *(.gptab.data) *(.gptab.sdata) } .gptab.sbss : { *(.gptab.bss) *(.gptab.sbss) } - /DISCARD/ : { *(.note.GNU-stack) } + /DISCARD/ : { *(.note.GNU-stack) *(.MIPS.abiflags) } } diff --git a/ld/testsuite/ld-mips-elf/mips-elf.exp b/ld/testsuite/ld-mips-elf/mips-elf.exp index a2632b2..64bb8e5 100644 --- a/ld/testsuite/ld-mips-elf/mips-elf.exp +++ b/ld/testsuite/ld-mips-elf/mips-elf.exp @@ -634,37 +634,49 @@ run_ld_link_tests $mips16_intermix_test run_dump_test "mips16-local-stubs-1" -run_dump_test "attr-gnu-4-00" -run_dump_test "attr-gnu-4-01" -run_dump_test "attr-gnu-4-02" -run_dump_test "attr-gnu-4-03" -run_dump_test "attr-gnu-4-04" -run_dump_test "attr-gnu-4-05" -run_dump_test "attr-gnu-4-10" -run_dump_test "attr-gnu-4-11" -run_dump_test "attr-gnu-4-12" -run_dump_test "attr-gnu-4-13" -run_dump_test "attr-gnu-4-14" -run_dump_test "attr-gnu-4-15" -run_dump_test "attr-gnu-4-20" -run_dump_test "attr-gnu-4-21" -run_dump_test "attr-gnu-4-22" -run_dump_test "attr-gnu-4-23" -run_dump_test "attr-gnu-4-24" -run_dump_test "attr-gnu-4-25" -run_dump_test "attr-gnu-4-30" -run_dump_test "attr-gnu-4-31" -run_dump_test "attr-gnu-4-32" -run_dump_test "attr-gnu-4-33" -run_dump_test "attr-gnu-4-34" -run_dump_test "attr-gnu-4-35" -run_dump_test "attr-gnu-4-40" -run_dump_test "attr-gnu-4-41" -run_dump_test "attr-gnu-4-42" -run_dump_test "attr-gnu-4-43" -run_dump_test "attr-gnu-4-44" -run_dump_test "attr-gnu-4-45" -run_dump_test "attr-gnu-4-51" +foreach firstfpabi [list 0 1 2 3 4 5 6 7 ] { + foreach secondfpabi [list 0 1 2 3 4 5 6 7 8] { + run_dump_test "attr-gnu-4-${firstfpabi}${secondfpabi}" + } +} +run_dump_test "attr-gnu-4-81" + +run_dump_test "attr-gnu-8-00" +run_dump_test "attr-gnu-8-01" +run_dump_test "attr-gnu-8-02" +run_dump_test "attr-gnu-8-10" +run_dump_test "attr-gnu-8-11" +run_dump_test "attr-gnu-8-12" +run_dump_test "attr-gnu-8-20" +run_dump_test "attr-gnu-8-21" +run_dump_test "attr-gnu-8-22" + +run_dump_test "attr-gnu-4-0-ph" +run_dump_test "attr-gnu-4-1-ph" +run_dump_test "attr-gnu-4-2-ph" +run_dump_test "attr-gnu-4-3-ph" +run_dump_test "attr-gnu-4-4-ph" +run_dump_test "attr-gnu-4-5-ph" +run_dump_test "attr-gnu-4-6-ph" +run_dump_test "attr-gnu-4-7-ph" +run_dump_test "attr-gnu-4-0-n32-ph" +run_dump_test "attr-gnu-4-1-n32-ph" +run_dump_test "attr-gnu-4-2-n32-ph" +run_dump_test "attr-gnu-4-3-n32-ph" +run_dump_test "attr-gnu-4-0-n64-ph" +run_dump_test "attr-gnu-4-1-n64-ph" +run_dump_test "attr-gnu-4-2-n64-ph" +run_dump_test "attr-gnu-4-3-n64-ph" + +run_dump_test "abiflags-strip1-ph" +run_dump_test "abiflags-strip2-ph" +run_dump_test "abiflags-strip3-ph" +run_dump_test "abiflags-strip4-ph" +run_dump_test "abiflags-strip5-ph" +run_dump_test "abiflags-strip6-ph" +run_dump_test "abiflags-strip7-ph" +run_dump_test "abiflags-strip8-ph" +run_dump_test "abiflags-strip9-ph" run_dump_test "nan-legacy" run_dump_test "nan-2008" @@ -828,13 +840,3 @@ if { $linux_gnu } { n32 -1 1 umips } } - -run_dump_test "attr-gnu-8-00" -run_dump_test "attr-gnu-8-01" -run_dump_test "attr-gnu-8-02" -run_dump_test "attr-gnu-8-10" -run_dump_test "attr-gnu-8-11" -run_dump_test "attr-gnu-8-12" -run_dump_test "attr-gnu-8-20" -run_dump_test "attr-gnu-8-21" -run_dump_test "attr-gnu-8-22" diff --git a/ld/testsuite/ld-mips-elf/mips-lib.ld b/ld/testsuite/ld-mips-elf/mips-lib.ld index 1d66c62..b3a2c97 100644 --- a/ld/testsuite/ld-mips-elf/mips-lib.ld +++ b/ld/testsuite/ld-mips-elf/mips-lib.ld @@ -214,5 +214,5 @@ SECTIONS .debug_varnames 0 : { *(.debug_varnames) } .gptab.sdata : { *(.gptab.data) *(.gptab.sdata) } .gptab.sbss : { *(.gptab.bss) *(.gptab.sbss) } - /DISCARD/ : { *(.note.GNU-stack) } + /DISCARD/ : { *(.note.GNU-stack) *(.MIPS.abiflags) } } diff --git a/ld/testsuite/ld-mips-elf/mips16-pic-1.gd b/ld/testsuite/ld-mips-elf/mips16-pic-1.gd index b8d8b34..cca758e 100644 --- a/ld/testsuite/ld-mips-elf/mips16-pic-1.gd +++ b/ld/testsuite/ld-mips-elf/mips16-pic-1.gd @@ -1,4 +1,21 @@ +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float \(double precision\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Hard float \(double precision\) +ISA Extension: .* +ASEs: + MIPS16 ASE +FLAGS 1: 00000000 +FLAGS 2: 00000000 + Primary GOT: Canonical gp value: 00057ff0 diff --git a/ld/testsuite/ld-mips-elf/mips16-pic-2.gd b/ld/testsuite/ld-mips-elf/mips16-pic-2.gd index c291bc8..269ae38 100644 --- a/ld/testsuite/ld-mips-elf/mips16-pic-2.gd +++ b/ld/testsuite/ld-mips-elf/mips16-pic-2.gd @@ -1,4 +1,21 @@ +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float \(double precision\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Hard float \(double precision\) +ISA Extension: .* +ASEs: + MIPS16 ASE +FLAGS 1: 00000000 +FLAGS 2: 00000000 + Primary GOT: Canonical gp value: 00057ff0 @@ -16,8 +33,8 @@ Primary GOT: Global entries: Address Access Initial Sym\.Val\. Type Ndx Name - 00050018 -32728\(gp\) 00040574 00040574 FUNC 6 used6 - 0005001c -32724\(gp\) 00040598 00040598 FUNC 6 used7 - 00050020 -32720\(gp\) 00040550 00040550 FUNC 6 used5 - 00050024 -32716\(gp\) 0004052c 0004052c FUNC 6 used4 + 00050018 -32728\(gp\) 00040574 00040574 FUNC 7 used6 + 0005001c -32724\(gp\) 00040598 00040598 FUNC 7 used7 + 00050020 -32720\(gp\) 00040550 00040550 FUNC 7 used5 + 00050024 -32716\(gp\) 0004052c 0004052c FUNC 7 used4 diff --git a/ld/testsuite/ld-mips-elf/mips16-pic-3.gd b/ld/testsuite/ld-mips-elf/mips16-pic-3.gd index 9297fe6..141c4e6 100644 --- a/ld/testsuite/ld-mips-elf/mips16-pic-3.gd +++ b/ld/testsuite/ld-mips-elf/mips16-pic-3.gd @@ -1,4 +1,21 @@ +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float \(double precision\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Hard float \(double precision\) +ISA Extension: .* +ASEs: + MIPS16 ASE +FLAGS 1: 00000000 +FLAGS 2: 00000000 + Primary GOT: Canonical gp value: 00057ff0 diff --git a/ld/testsuite/ld-mips-elf/mips16-pic-4a.gd b/ld/testsuite/ld-mips-elf/mips16-pic-4a.gd index 1ab835e..55c8e1c 100644 --- a/ld/testsuite/ld-mips-elf/mips16-pic-4a.gd +++ b/ld/testsuite/ld-mips-elf/mips16-pic-4a.gd @@ -1,4 +1,21 @@ +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float \(double precision\) + +MIPS ABI Flags Version: 0 + +ISA: MIPS.* +GPR size: .* +CPR1 size: .* +CPR2 size: 0 +FP ABI: Hard float \(double precision\) +ISA Extension: .* +ASEs: + MIPS16 ASE +FLAGS 1: 00000000 +FLAGS 2: 00000000 + Primary GOT: Canonical gp value: 00057ff0 diff --git a/ld/testsuite/ld-mips-elf/multi-got-no-shared.d b/ld/testsuite/ld-mips-elf/multi-got-no-shared.d index 25af107..a3e1bb2 100644 --- a/ld/testsuite/ld-mips-elf/multi-got-no-shared.d +++ b/ld/testsuite/ld-mips-elf/multi-got-no-shared.d @@ -8,11 +8,11 @@ .*: +file format.* Disassembly of section \.text: -004000b0 <[^>]*> 3c1c0043 lui gp,0x43 -004000b4 <[^>]*> 279c9ff0 addiu gp,gp,-24592 -004000b8 <[^>]*> afbc0008 sw gp,8\(sp\) +004000f0 <[^>]*> 3c1c0043 lui gp,0x43 +004000f4 <[^>]*> 279c9ff0 addiu gp,gp,-24592 +004000f8 <[^>]*> afbc0008 sw gp,8\(sp\) #... -00408d60 <[^>]*> 3c1c0043 lui gp,0x43 -00408d64 <[^>]*> 279c2c98 addiu gp,gp,11416 -00408d68 <[^>]*> afbc0008 sw gp,8\(sp\) +00408da0 <[^>]*> 3c1c0043 lui gp,0x43 +00408da4 <[^>]*> 279c2c98 addiu gp,gp,11416 +00408da8 <[^>]*> afbc0008 sw gp,8\(sp\) #pass diff --git a/ld/testsuite/ld-mips-elf/nan-2008.d b/ld/testsuite/ld-mips-elf/nan-2008.d index aa20049..30ea837 100644 --- a/ld/testsuite/ld-mips-elf/nan-2008.d +++ b/ld/testsuite/ld-mips-elf/nan-2008.d @@ -5,3 +5,4 @@ .*:.*file format.*mips.* private flags = [0-9a-f]*[4-7c-f]..: .*[[,]nan2008[],].* +#pass diff --git a/ld/testsuite/ld-mips-elf/nan-legacy.d b/ld/testsuite/ld-mips-elf/nan-legacy.d index 081abcf..8dacc06 100644 --- a/ld/testsuite/ld-mips-elf/nan-legacy.d +++ b/ld/testsuite/ld-mips-elf/nan-legacy.d @@ -4,5 +4,5 @@ #objdump: -p .*:.*file format.*mips.* -#failif -private flags = [0-9a-f]*[4-7c-f]..: .*[[]nan2008[]].* +!private flags = [0-9a-f]*[4-7c-f]..: .*[[]nan2008[]].* +#pass diff --git a/ld/testsuite/ld-mips-elf/pic-and-nonpic-3a.gd b/ld/testsuite/ld-mips-elf/pic-and-nonpic-3a.gd index aa9579b..b0f7b1e 100644 --- a/ld/testsuite/ld-mips-elf/pic-and-nonpic-3a.gd +++ b/ld/testsuite/ld-mips-elf/pic-and-nonpic-3a.gd @@ -1,4 +1,8 @@ +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float \(double precision\) + Primary GOT: Canonical gp value: 000183f0 diff --git a/ld/testsuite/ld-mips-elf/pic-and-nonpic-3a.ld b/ld/testsuite/ld-mips-elf/pic-and-nonpic-3a.ld index 81d0d8a..f2db79a 100644 --- a/ld/testsuite/ld-mips-elf/pic-and-nonpic-3a.ld +++ b/ld/testsuite/ld-mips-elf/pic-and-nonpic-3a.ld @@ -20,4 +20,6 @@ SECTIONS . = ALIGN (0x400); HIDDEN (_gp = . + 0x7ff0); .got : { *(.got) } + + /DISCARD/ : { *(.MIPS.abiflags) } } diff --git a/ld/testsuite/ld-mips-elf/pic-and-nonpic-3b.gd b/ld/testsuite/ld-mips-elf/pic-and-nonpic-3b.gd index 6d3d677..e96e87f 100644 --- a/ld/testsuite/ld-mips-elf/pic-and-nonpic-3b.gd +++ b/ld/testsuite/ld-mips-elf/pic-and-nonpic-3b.gd @@ -1,4 +1,8 @@ +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float \(double precision\) + Primary GOT: Canonical gp value: 000a7ff0 diff --git a/ld/testsuite/ld-mips-elf/pic-and-nonpic-3b.ld b/ld/testsuite/ld-mips-elf/pic-and-nonpic-3b.ld index 693bbdd..ab64ea6 100644 --- a/ld/testsuite/ld-mips-elf/pic-and-nonpic-3b.ld +++ b/ld/testsuite/ld-mips-elf/pic-and-nonpic-3b.ld @@ -32,4 +32,6 @@ SECTIONS . = 0xa1000; .data : { *(.data) } + + /DISCARD/ : { *(.MIPS.abiflags) } } diff --git a/ld/testsuite/ld-mips-elf/pic-and-nonpic-4b.ld b/ld/testsuite/ld-mips-elf/pic-and-nonpic-4b.ld index bae9fd8..102c851 100644 --- a/ld/testsuite/ld-mips-elf/pic-and-nonpic-4b.ld +++ b/ld/testsuite/ld-mips-elf/pic-and-nonpic-4b.ld @@ -30,4 +30,6 @@ SECTIONS . = 0xa2000; .bss : { *(.dynbss) } + + /DISCARD/ : { *(.MIPS.abiflags) } } diff --git a/ld/testsuite/ld-mips-elf/pic-and-nonpic-5b.gd b/ld/testsuite/ld-mips-elf/pic-and-nonpic-5b.gd index 6919a69..6d46b4f 100644 --- a/ld/testsuite/ld-mips-elf/pic-and-nonpic-5b.gd +++ b/ld/testsuite/ld-mips-elf/pic-and-nonpic-5b.gd @@ -1,4 +1,8 @@ +Attribute Section: gnu +File Attributes + Tag_GNU_MIPS_ABI_FP: Hard float \(double precision\) + Primary GOT: Canonical gp value: 000a7ff0 diff --git a/ld/testsuite/ld-mips-elf/pic-and-nonpic-5b.ld b/ld/testsuite/ld-mips-elf/pic-and-nonpic-5b.ld index b3ae77d..b76ceff 100644 --- a/ld/testsuite/ld-mips-elf/pic-and-nonpic-5b.ld +++ b/ld/testsuite/ld-mips-elf/pic-and-nonpic-5b.ld @@ -35,4 +35,6 @@ SECTIONS . = 0xa2000; .bss : { *(.dynbss) } + + /DISCARD/ : { *(.MIPS.abiflags) } } diff --git a/ld/testsuite/ld-mips-elf/pic-and-nonpic-6.ld b/ld/testsuite/ld-mips-elf/pic-and-nonpic-6.ld index d9f276b..c819816 100644 --- a/ld/testsuite/ld-mips-elf/pic-and-nonpic-6.ld +++ b/ld/testsuite/ld-mips-elf/pic-and-nonpic-6.ld @@ -37,4 +37,6 @@ SECTIONS . = 0xa2000; .bss : { *(.dynbss) } + + /DISCARD/ : { *(.MIPS.abiflags) *(.gnu.attributes) } } diff --git a/ld/testsuite/ld-mips-elf/region1.t b/ld/testsuite/ld-mips-elf/region1.t index 13077ab..1f20e56 100644 --- a/ld/testsuite/ld-mips-elf/region1.t +++ b/ld/testsuite/ld-mips-elf/region1.t @@ -9,4 +9,6 @@ SECTIONS .text : { *(.text) } > TEXTMEM .data : { *(.data) } > DATAMEM .bss : { *(.bss) } > DATAMEM + + /DISCARD/ : { *(.MIPS.abiflags) *(.gnu.attributes) } } diff --git a/ld/testsuite/ld-mips-elf/rel32-n32.d b/ld/testsuite/ld-mips-elf/rel32-n32.d index 43c2632..9951615 100644 --- a/ld/testsuite/ld-mips-elf/rel32-n32.d +++ b/ld/testsuite/ld-mips-elf/rel32-n32.d @@ -10,6 +10,6 @@ Relocation section '.rel.dyn' at offset .* contains 2 entries: [0-9a-f ]+R_MIPS_REL32 Hex dump of section '.text': - 0x000002a0 00000000 00000000 00000000 00000000 ................ - 0x000002b0 000002b0 00000000 00000000 00000000 ................ - 0x000002c0 00000000 00000000 00000000 00000000 ................ + 0x000002e0 00000000 00000000 00000000 00000000 ................ + 0x000002f0 000002f0 00000000 00000000 00000000 ................ + 0x00000300 00000000 00000000 00000000 00000000 ................ diff --git a/ld/testsuite/ld-mips-elf/rel32-o32.d b/ld/testsuite/ld-mips-elf/rel32-o32.d index 0103d79..742cdaa 100644 --- a/ld/testsuite/ld-mips-elf/rel32-o32.d +++ b/ld/testsuite/ld-mips-elf/rel32-o32.d @@ -10,6 +10,6 @@ Relocation section '.rel.dyn' at offset .* contains 2 entries: [0-9a-f ]+R_MIPS_REL32 Hex dump of section '.text': - 0x000002a0 00000000 00000000 00000000 00000000 ................ - 0x000002b0 000002b0 00000000 00000000 00000000 ................ - 0x000002c0 00000000 00000000 00000000 00000000 ................ + 0x000002e0 00000000 00000000 00000000 00000000 ................ + 0x000002f0 000002f0 00000000 00000000 00000000 ................ + 0x00000300 00000000 00000000 00000000 00000000 ................ diff --git a/ld/testsuite/ld-mips-elf/rel64.d b/ld/testsuite/ld-mips-elf/rel64.d index 89df314..01bffa3 100644 --- a/ld/testsuite/ld-mips-elf/rel64.d +++ b/ld/testsuite/ld-mips-elf/rel64.d @@ -14,6 +14,6 @@ Relocation section '.rel.dyn' at offset .* contains 2 entries: +Type3: R_MIPS_NONE Hex dump of section '.text': - 0x00000400 00000000 00000000 00000000 00000000 ................ - 0x00000410 00000000 00000410 00000000 00000000 ................ - 0x00000420 00000000 00000000 00000000 00000000 ................ + 0x00000450 00000000 00000000 00000000 00000000 ................ + 0x00000460 00000000 00000460 00000000 00000000 ................ + 0x00000470 00000000 00000000 00000000 00000000 ................ diff --git a/ld/testsuite/ld-mips-elf/stub-dynsym-1.ld b/ld/testsuite/ld-mips-elf/stub-dynsym-1.ld index 0a58e6f..dec5ca1 100644 --- a/ld/testsuite/ld-mips-elf/stub-dynsym-1.ld +++ b/ld/testsuite/ld-mips-elf/stub-dynsym-1.ld @@ -13,5 +13,5 @@ SECTIONS HIDDEN (_gp = . + 0x7ff0); .got : { *(.got) } - /DISCARD/ : { *(.reginfo) } + /DISCARD/ : { *(.reginfo) *(.MIPS.abiflags) } } diff --git a/ld/testsuite/ld-mips-elf/tls-hidden3.ld b/ld/testsuite/ld-mips-elf/tls-hidden3.ld index 8e0d0aa..5609a4b 100644 --- a/ld/testsuite/ld-mips-elf/tls-hidden3.ld +++ b/ld/testsuite/ld-mips-elf/tls-hidden3.ld @@ -19,7 +19,7 @@ SECTIONS . = ALIGN (0x400); .tdata : { *(.tdata) } - /DISCARD/ : { *(.reginfo) } + /DISCARD/ : { *(.reginfo) *(.MIPS.abiflags) } } VERSION diff --git a/ld/testsuite/ld-mips-elf/tls-multi-got-1.r b/ld/testsuite/ld-mips-elf/tls-multi-got-1.r index aea3d2de..45bd791 100644 --- a/ld/testsuite/ld-mips-elf/tls-multi-got-1.r +++ b/ld/testsuite/ld-mips-elf/tls-multi-got-1.r @@ -15,7 +15,7 @@ Dynamic section at offset .* contains 18 entries: 0x70000006 \(MIPS_BASE_ADDRESS\) 0x0 0x7000000a \(MIPS_LOCAL_GOTNO\) 2 0x70000011 \(MIPS_SYMTABNO\) 20011 - 0x70000012 \(MIPS_UNREFEXTNO\) 10 + 0x70000012 \(MIPS_UNREFEXTNO\) 11 0x70000013 \(MIPS_GOTSYM\) 0xb 0x0000001e \(FLAGS\) STATIC_TLS 0x00000000 \(NULL\) 0x0 diff --git a/ld/testsuite/ld-mips-elf/vxworks1.ld b/ld/testsuite/ld-mips-elf/vxworks1.ld index 8fe3c48..d9f8621 100644 --- a/ld/testsuite/ld-mips-elf/vxworks1.ld +++ b/ld/testsuite/ld-mips-elf/vxworks1.ld @@ -28,5 +28,5 @@ SECTIONS . = ALIGN (0x400); .bss : { *(.bss) *(.dynbss) } - /DISCARD/ : { *(.reginfo) } + /DISCARD/ : { *(.reginfo) *(.MIPS.abiflags) } } diff --git a/ld/testsuite/ld-scripts/overlay-size.t b/ld/testsuite/ld-scripts/overlay-size.t index 0d9af35..68c0986 100644 --- a/ld/testsuite/ld-scripts/overlay-size.t +++ b/ld/testsuite/ld-scripts/overlay-size.t @@ -60,5 +60,5 @@ SECTIONS end_of_data_overlays = . ; . = 0x8000; - /DISCARD/ : { *(.reginfo) } + /DISCARD/ : { *(.reginfo) *(.MIPS.abiflags) } } diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 4c4a0b4..50876fc 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,11 @@ +2014-07-29 Matthew Fortune <matthew.fortune@imgtec.com> + + * micromips-opc.c (COD, LCD) New macros. + (cfc1, ctc1): Remove FP_S attribute. + (dmfc1, mfc1, mfhc1): Add LCD attribute. + (dmtc1, mtc1, mthc1): Add COD attribute. + * mips-opc.c (cfc1, cftc1, ctc, cttc1): Remove FP_S attribute. + 2014-07-22 Sergey Guriev <sergey.s.guriev@intel.com> Alexander Ivchenko <alexander.ivchenko@intel.com> Maxim Kuznetsov <maxim.kuznetsov@intel.com> diff --git a/opcodes/micromips-opc.c b/opcodes/micromips-opc.c index af7cbf6..4b1cdd7 100644 --- a/opcodes/micromips-opc.c +++ b/opcodes/micromips-opc.c @@ -202,6 +202,8 @@ decode_micromips_operand (const char *p) #define TRAP INSN_NO_DELAY_SLOT #define LM INSN_LOAD_MEMORY #define SM INSN_STORE_MEMORY +#define COD INSN_COPROC_MOVE_DELAY +#define LCD INSN_LOAD_COPROC_DELAY #define BD16 INSN2_BRANCH_DELAY_16BIT /* Used in pinfo2. */ #define BD32 INSN2_BRANCH_DELAY_32BIT /* Used in pinfo2. */ @@ -540,14 +542,14 @@ const struct mips_opcode micromips_opcodes[] = {"ceil.l.s", "T,S", 0x5400133b, 0xfc00ffff, WR_1|RD_2|FP_S|FP_D, 0, I1, 0, 0 }, {"ceil.w.d", "T,S", 0x54005b3b, 0xfc00ffff, WR_1|RD_2|FP_S|FP_D, 0, I1, 0, 0 }, {"ceil.w.s", "T,S", 0x54001b3b, 0xfc00ffff, WR_1|RD_2|FP_S, 0, I1, 0, 0 }, -{"cfc1", "t,G", 0x5400103b, 0xfc00ffff, WR_1|RD_C1|FP_S, 0, I1, 0, 0 }, -{"cfc1", "t,S", 0x5400103b, 0xfc00ffff, WR_1|RD_C1|FP_S, 0, I1, 0, 0 }, +{"cfc1", "t,G", 0x5400103b, 0xfc00ffff, WR_1|RD_C1, 0, I1, 0, 0 }, +{"cfc1", "t,S", 0x5400103b, 0xfc00ffff, WR_1|RD_C1, 0, I1, 0, 0 }, {"cfc2", "t,G", 0x0000cd3c, 0xfc00ffff, WR_1|RD_C2, 0, I1, 0, 0 }, {"clo", "t,s", 0x00004b3c, 0xfc00ffff, WR_1|RD_2, 0, I1, 0, 0 }, {"clz", "t,s", 0x00005b3c, 0xfc00ffff, WR_1|RD_2, 0, I1, 0, 0 }, {"cop2", "C", 0x00000002, 0xfc000007, CP, 0, I1, 0, 0 }, -{"ctc1", "t,G", 0x5400183b, 0xfc00ffff, RD_1|WR_CC|FP_S, 0, I1, 0, 0 }, -{"ctc1", "t,S", 0x5400183b, 0xfc00ffff, RD_1|WR_CC|FP_S, 0, I1, 0, 0 }, +{"ctc1", "t,G", 0x5400183b, 0xfc00ffff, RD_1|WR_CC, 0, I1, 0, 0 }, +{"ctc1", "t,S", 0x5400183b, 0xfc00ffff, RD_1|WR_CC, 0, I1, 0, 0 }, {"ctc2", "t,G", 0x0000dd3c, 0xfc00ffff, RD_1|WR_C2|WR_CC, 0, I1, 0, 0 }, {"cvt.d.l", "T,S", 0x5400537b, 0xfc00ffff, WR_1|RD_2|FP_D, 0, I1, 0, 0 }, {"cvt.d.s", "T,S", 0x5400137b, 0xfc00ffff, WR_1|RD_2|FP_S|FP_D, 0, I1, 0, 0 }, @@ -623,10 +625,10 @@ const struct mips_opcode micromips_opcodes[] = {"dmtc0", "t,G,H", 0x580002fc, 0xfc00c7ff, RD_1|WR_C0|WR_CC, 0, I3, 0, 0 }, {"dmtgc0", "t,G", 0x580006fc, 0xfc00ffff, RD_1|WR_C0|WR_CC, 0, 0, IVIRT64, 0 }, {"dmtgc0", "t,G,H", 0x580006fc, 0xfc00c7ff, RD_1|WR_C0|WR_CC, 0, 0, IVIRT64, 0 }, -{"dmfc1", "t,S", 0x5400243b, 0xfc00ffff, WR_1|RD_2|FP_S, 0, I3, 0, 0 }, -{"dmfc1", "t,G", 0x5400243b, 0xfc00ffff, WR_1|RD_2|FP_S, 0, I3, 0, 0 }, -{"dmtc1", "t,G", 0x54002c3b, 0xfc00ffff, RD_1|WR_2|FP_S, 0, I3, 0, 0 }, -{"dmtc1", "t,S", 0x54002c3b, 0xfc00ffff, RD_1|WR_2|FP_S, 0, I3, 0, 0 }, +{"dmfc1", "t,S", 0x5400243b, 0xfc00ffff, WR_1|RD_2|FP_S|LCD, 0, I3, 0, 0 }, +{"dmfc1", "t,G", 0x5400243b, 0xfc00ffff, WR_1|RD_2|FP_S|LCD, 0, I3, 0, 0 }, +{"dmtc1", "t,G", 0x54002c3b, 0xfc00ffff, RD_1|WR_2|FP_S|COD, 0, I3, 0, 0 }, +{"dmtc1", "t,S", 0x54002c3b, 0xfc00ffff, RD_1|WR_2|FP_S|COD, 0, I3, 0, 0 }, {"dmfc2", "t,G", 0x00006d3c, 0xfc00ffff, WR_1|RD_C2, 0, I3, 0, 0 }, /*{"dmfc2", "t,G,H", 0x58000283, 0xfc001fff, WR_1|RD_C2, 0, I3, 0, 0 },*/ {"dmtc2", "t,G", 0x00007d3c, 0xfc00ffff, RD_1|WR_C2|WR_CC, 0, I3, 0, 0 }, @@ -823,13 +825,13 @@ const struct mips_opcode micromips_opcodes[] = {"maddu", "7,s,t", 0x00001abc, 0xfc003fff, RD_2|RD_3|MOD_a, 0, 0, D32, 0 }, {"mfc0", "t,G", 0x000000fc, 0xfc00ffff, WR_1|RD_C0, 0, I1, 0, 0 }, {"mfc0", "t,G,H", 0x000000fc, 0xfc00c7ff, WR_1|RD_C0, 0, I1, 0, 0 }, -{"mfc1", "t,S", 0x5400203b, 0xfc00ffff, WR_1|RD_2|FP_S, 0, I1, 0, 0 }, -{"mfc1", "t,G", 0x5400203b, 0xfc00ffff, WR_1|RD_2|FP_S, 0, I1, 0, 0 }, +{"mfc1", "t,S", 0x5400203b, 0xfc00ffff, WR_1|RD_2|FP_S|LCD, 0, I1, 0, 0 }, +{"mfc1", "t,G", 0x5400203b, 0xfc00ffff, WR_1|RD_2|FP_S|LCD, 0, I1, 0, 0 }, {"mfc2", "t,G", 0x00004d3c, 0xfc00ffff, WR_1|RD_C2, 0, I1, 0, 0 }, {"mfgc0", "t,G", 0x000004fc, 0xfc00ffff, WR_1|RD_C0, 0, 0, IVIRT, 0 }, {"mfgc0", "t,G,H", 0x000004fc, 0xfc00c7ff, WR_1|RD_C0, 0, 0, IVIRT, 0 }, -{"mfhc1", "t,S", 0x5400303b, 0xfc00ffff, WR_1|RD_2|FP_D, 0, I1, 0, 0 }, -{"mfhc1", "t,G", 0x5400303b, 0xfc00ffff, WR_1|RD_2|FP_D, 0, I1, 0, 0 }, +{"mfhc1", "t,S", 0x5400303b, 0xfc00ffff, WR_1|RD_2|FP_D|LCD, 0, I1, 0, 0 }, +{"mfhc1", "t,G", 0x5400303b, 0xfc00ffff, WR_1|RD_2|FP_D|LCD, 0, I1, 0, 0 }, {"mfhc2", "t,G", 0x00008d3c, 0xfc00ffff, WR_1|RD_C2, 0, I1, 0, 0 }, {"mfhi", "mj", 0x4600, 0xffe0, WR_1|RD_HI, 0, I1, 0, 0 }, {"mfhi", "s", 0x00000d7c, 0xffe0ffff, WR_1|RD_HI, 0, I1, 0, 0 }, @@ -869,13 +871,13 @@ const struct mips_opcode micromips_opcodes[] = {"msubu", "7,s,t", 0x00003abc, 0xfc003fff, RD_2|RD_3|MOD_a, 0, 0, D32, 0 }, {"mtc0", "t,G", 0x000002fc, 0xfc00ffff, RD_1|WR_C0|WR_CC, 0, I1, 0, 0 }, {"mtc0", "t,G,H", 0x000002fc, 0xfc00c7ff, RD_1|WR_C0|WR_CC, 0, I1, 0, 0 }, -{"mtc1", "t,S", 0x5400283b, 0xfc00ffff, RD_1|WR_2|FP_S, 0, I1, 0, 0 }, -{"mtc1", "t,G", 0x5400283b, 0xfc00ffff, RD_1|WR_2|FP_S, 0, I1, 0, 0 }, +{"mtc1", "t,S", 0x5400283b, 0xfc00ffff, RD_1|WR_2|FP_S|COD, 0, I1, 0, 0 }, +{"mtc1", "t,G", 0x5400283b, 0xfc00ffff, RD_1|WR_2|FP_S|COD, 0, I1, 0, 0 }, {"mtc2", "t,G", 0x00005d3c, 0xfc00ffff, RD_1|WR_C2|WR_CC, 0, I1, 0, 0 }, {"mtgc0", "t,G", 0x000006fc, 0xfc00ffff, RD_1|WR_C0|WR_CC, 0, 0, IVIRT, 0 }, {"mtgc0", "t,G,H", 0x000006fc, 0xfc00c7ff, RD_1|WR_C0|WR_CC, 0, 0, IVIRT, 0 }, -{"mthc1", "t,S", 0x5400383b, 0xfc00ffff, RD_1|WR_2|FP_D, 0, I1, 0, 0 }, -{"mthc1", "t,G", 0x5400383b, 0xfc00ffff, RD_1|WR_2|FP_D, 0, I1, 0, 0 }, +{"mthc1", "t,S", 0x5400383b, 0xfc00ffff, RD_1|WR_2|FP_D|COD, 0, I1, 0, 0 }, +{"mthc1", "t,G", 0x5400383b, 0xfc00ffff, RD_1|WR_2|FP_D|COD, 0, I1, 0, 0 }, {"mthc2", "t,G", 0x00009d3c, 0xfc00ffff, RD_1|WR_C2|WR_CC, 0, I1, 0, 0 }, {"mthi", "s", 0x00002d7c, 0xffe0ffff, RD_1|WR_HI, 0, I1, 0, 0 }, {"mthi", "s,7", 0x0000207c, 0xffe03fff, RD_1|WR_HI, 0, 0, D32, 0 }, diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c index e2c258c..ed74f90 100644 --- a/opcodes/mips-opc.c +++ b/opcodes/mips-opc.c @@ -901,12 +901,12 @@ const struct mips_opcode mips_builtin_opcodes[] = {"ceil.w.d", "D,S", 0x4620000e, 0xffff003f, WR_1|RD_2|FP_S|FP_D, 0, I2, 0, SF }, {"ceil.w.s", "D,S", 0x4600000e, 0xffff003f, WR_1|RD_2|FP_S, 0, I2, 0, EE }, /* cfc0 is at the bottom of the table. */ -{"cfc1", "t,G", 0x44400000, 0xffe007ff, WR_1|RD_C1|LCD|FP_S, 0, I1, 0, 0 }, -{"cfc1", "t,S", 0x44400000, 0xffe007ff, WR_1|RD_C1|LCD|FP_S, 0, I1, 0, 0 }, +{"cfc1", "t,G", 0x44400000, 0xffe007ff, WR_1|RD_C1|LCD, 0, I1, 0, 0 }, +{"cfc1", "t,S", 0x44400000, 0xffe007ff, WR_1|RD_C1|LCD, 0, I1, 0, 0 }, /* cfc2 is at the bottom of the table. */ /* cfc3 is at the bottom of the table. */ -{"cftc1", "d,E", 0x41000023, 0xffe007ff, WR_1|RD_C1|TRAP|LCD|FP_S, 0, 0, MT32, 0 }, -{"cftc1", "d,T", 0x41000023, 0xffe007ff, WR_1|RD_C1|TRAP|LCD|FP_S, 0, 0, MT32, 0 }, +{"cftc1", "d,E", 0x41000023, 0xffe007ff, WR_1|RD_C1|TRAP|LCD, 0, 0, MT32, 0 }, +{"cftc1", "d,T", 0x41000023, 0xffe007ff, WR_1|RD_C1|TRAP|LCD, 0, 0, MT32, 0 }, {"cftc2", "d,E", 0x41000025, 0xffe007ff, WR_1|RD_C2|TRAP|LCD, 0, 0, MT32, IOCT|IOCTP|IOCT2 }, {"cins32", "t,r,+p,+s", 0x70000033, 0xfc00003f, WR_1|RD_2, 0, IOCT, 0, 0 }, {"cins", "t,r,+P,+S", 0x70000033, 0xfc00003f, WR_1|RD_2, 0, IOCT, 0, 0 }, /* cins32 */ @@ -914,12 +914,12 @@ const struct mips_opcode mips_builtin_opcodes[] = {"clo", "U,s", 0x70000021, 0xfc0007ff, WR_1|RD_2, 0, I32|N55, 0, 0 }, {"clz", "U,s", 0x70000020, 0xfc0007ff, WR_1|RD_2, 0, I32|N55, 0, 0 }, /* ctc0 is at the bottom of the table. */ -{"ctc1", "t,G", 0x44c00000, 0xffe007ff, RD_1|WR_CC|COD|FP_S, 0, I1, 0, 0 }, -{"ctc1", "t,S", 0x44c00000, 0xffe007ff, RD_1|WR_CC|COD|FP_S, 0, I1, 0, 0 }, +{"ctc1", "t,G", 0x44c00000, 0xffe007ff, RD_1|WR_CC|COD, 0, I1, 0, 0 }, +{"ctc1", "t,S", 0x44c00000, 0xffe007ff, RD_1|WR_CC|COD, 0, I1, 0, 0 }, /* ctc2 is at the bottom of the table. */ /* ctc3 is at the bottom of the table. */ -{"cttc1", "t,g", 0x41800023, 0xffe007ff, RD_1|WR_CC|TRAP|COD|FP_S, 0, 0, MT32, 0 }, -{"cttc1", "t,S", 0x41800023, 0xffe007ff, RD_1|WR_CC|TRAP|COD|FP_S, 0, 0, MT32, 0 }, +{"cttc1", "t,G", 0x41800023, 0xffe007ff, RD_1|WR_CC|TRAP|COD, 0, 0, MT32, 0 }, +{"cttc1", "t,S", 0x41800023, 0xffe007ff, RD_1|WR_CC|TRAP|COD, 0, 0, MT32, 0 }, {"cttc2", "t,g", 0x41800025, 0xffe007ff, RD_1|WR_CC|TRAP|COD, 0, 0, MT32, IOCT|IOCTP|IOCT2 }, {"cvt.d.l", "D,S", 0x46a00021, 0xffff003f, WR_1|RD_2|FP_D, 0, I3_33, 0, 0 }, {"cvt.d.s", "D,S", 0x46000021, 0xffff003f, WR_1|RD_2|FP_S|FP_D, 0, I1, 0, SF }, |