diff options
40 files changed, 178 insertions, 106 deletions
diff --git a/cpu/ChangeLog b/cpu/ChangeLog index 30b884c..41ff181 100644 --- a/cpu/ChangeLog +++ b/cpu/ChangeLog @@ -1,3 +1,8 @@ +2020-06-02 Jose E. Marchesi <jose.marchesi@oracle.com> + + * mep.opc (print_slot_insn): Pass the insn endianness to + cgen_get_insn_value. + 2020-05-28 Jose E. Marchesi <jose.marchesi@oracle.com> David Faust <david.faust@oracle.com> diff --git a/cpu/mep.opc b/cpu/mep.opc index 34e279d..5a4c93d 100644 --- a/cpu/mep.opc +++ b/cpu/mep.opc @@ -1271,7 +1271,7 @@ print_slot_insn (CGEN_CPU_DESC cd, CGEN_INSN_INT insn_value; CGEN_EXTRACT_INFO ex_info; - insn_value = cgen_get_insn_value (cd, buf, 32); + insn_value = cgen_get_insn_value (cd, buf, 32, cd->insn_endian); /* Fill in ex_info fields like read_insn would. Don't actually call read_insn, since the incoming buffer is already read (and possibly diff --git a/gas/ChangeLog b/gas/ChangeLog index 6484c62..bb917cc 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,14 @@ +2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com> + + * cgen.c (gas_cgen_finish_insn): Pass the endianness to + cgen_put_insn_value. + (gas_cgen_md_apply_fix): Likewise. + (gas_cgen_md_apply_fix): Likewise. + * config/tc-bpf.c (md_apply_fix): Pass data endianness to + cgen_put_insn_value. + * config/tc-mep.c (mep_check_ivc2_scheduling): Pass endianness to + cgen_put_insn_value. + 2020-06-04 Alan Modra <amodra@gmail.com> * testsuite/config/default.exp: Remove global directive outside @@ -621,7 +621,8 @@ gas_cgen_finish_insn (const CGEN_INSN *insn, CGEN_INSN_BYTES_PTR buf, /* If we're recording insns as numbers (rather than a string of bytes), target byte order handling is deferred until now. */ #if CGEN_INT_INSN_P - cgen_put_insn_value (gas_cgen_cpu_desc, (unsigned char *) f, length, *buf); + cgen_put_insn_value (gas_cgen_cpu_desc, (unsigned char *) f, length, *buf, + gas_cgen_cpu_desc->insn_endian); #else memcpy (f, buf, byte_len); #endif @@ -906,13 +907,15 @@ gas_cgen_md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED) { CGEN_INSN_INT insn_value = cgen_get_insn_value (cd, (unsigned char *) where, - CGEN_INSN_BITSIZE (insn)); + CGEN_INSN_BITSIZE (insn), + cd->insn_endian); /* ??? 0 is passed for `pc'. */ errmsg = CGEN_CPU_INSERT_OPERAND (cd) (cd, opindex, fields, &insn_value, (bfd_vma) 0); cgen_put_insn_value (cd, (unsigned char *) where, - CGEN_INSN_BITSIZE (insn), insn_value); + CGEN_INSN_BITSIZE (insn), insn_value, + cd->insn_endian); } #else /* ??? 0 is passed for `pc'. */ diff --git a/gas/config/tc-bpf.c b/gas/config/tc-bpf.c index a379acb..7c7d22e 100644 --- a/gas/config/tc-bpf.c +++ b/gas/config/tc-bpf.c @@ -324,7 +324,8 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg) this code is executed only once per instruction. */ where = fixP->fx_frag->fr_literal + fixP->fx_where; cgen_put_insn_value (gas_cgen_cpu_desc, (unsigned char *) where + 1, 8, - target_big_endian ? 0x01 : 0x10); + target_big_endian ? 0x01 : 0x10, + gas_cgen_cpu_desc->endian); /* Fallthrough. */ case BPF_OPERAND_DISP16: /* The PC-relative displacement fields in jump instructions diff --git a/gas/config/tc-mep.c b/gas/config/tc-mep.c index 26fb80e..6b52841 100644 --- a/gas/config/tc-mep.c +++ b/gas/config/tc-mep.c @@ -1111,7 +1111,7 @@ mep_check_ivc2_scheduling (void) #if CGEN_INT_INSN_P cgen_put_insn_value (gas_cgen_cpu_desc, (unsigned char *) temp, 32, - m->buffer[0]); + m->buffer[0], gas_cgen_cpu_desc->insn_endian); #else memcpy (temp, m->buffer, byte_len); #endif diff --git a/include/ChangeLog b/include/ChangeLog index df4208e..e0bef67 100644 --- a/include/ChangeLog +++ b/include/ChangeLog @@ -1,3 +1,8 @@ +2020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com> + + * opcode/cgen.h: Get an `endian' argument in both + cgen_get_insn_value and cgen_put_insn_value. + 2020-06-04 Jose E. Marchesi <jemarch@gnu.org> * opcode/cgen.h (enum cgen_cpu_open_arg): New value diff --git a/include/opcode/cgen.h b/include/opcode/cgen.h index 3f32544..cae2795 100644 --- a/include/opcode/cgen.h +++ b/include/opcode/cgen.h @@ -1463,9 +1463,9 @@ extern const CGEN_INSN * cgen_lookup_get_insn_operands /* Cover fns to bfd_get/set. */ extern CGEN_INSN_INT cgen_get_insn_value - (CGEN_CPU_DESC, unsigned char *, int); + (CGEN_CPU_DESC, unsigned char *, int, int); extern void cgen_put_insn_value - (CGEN_CPU_DESC, unsigned char *, int, CGEN_INSN_INT); + (CGEN_CPU_DESC, unsigned char *, int, CGEN_INSN_INT, int); extern CGEN_INSN_INT cgen_get_base_insn_value (CGEN_CPU_DESC, unsigned char *, int); diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index dc4c285..39df27e 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,46 @@ +2020-06-03 Jose E. Marchesi <jose.marchesi@oracle.com> + + * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument. + (cgen_put_insn_value): Likewise. + (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value. + * cgen-dis.in (print_insn): Likewise. + * cgen-ibld.in (insert_1): Likewise. + (insert_1): Likewise. + (insert_insn_normal): Likewise. + (extract_1): Likewise. + * bpf-dis.c: Regenerate. + * bpf-ibld.c: Likewise. + * bpf-ibld.c: Likewise. + * cgen-dis.in: Likewise. + * cgen-ibld.in: Likewise. + * cgen-opc.c: Likewise. + * epiphany-dis.c: Likewise. + * epiphany-ibld.c: Likewise. + * fr30-dis.c: Likewise. + * fr30-ibld.c: Likewise. + * frv-dis.c: Likewise. + * frv-ibld.c: Likewise. + * ip2k-dis.c: Likewise. + * ip2k-ibld.c: Likewise. + * iq2000-dis.c: Likewise. + * iq2000-ibld.c: Likewise. + * lm32-dis.c: Likewise. + * lm32-ibld.c: Likewise. + * m32c-dis.c: Likewise. + * m32c-ibld.c: Likewise. + * m32r-dis.c: Likewise. + * m32r-ibld.c: Likewise. + * mep-dis.c: Likewise. + * mep-ibld.c: Likewise. + * mt-dis.c: Likewise. + * mt-ibld.c: Likewise. + * or1k-dis.c: Likewise. + * or1k-ibld.c: Likewise. + * xc16x-dis.c: Likewise. + * xc16x-ibld.c: Likewise. + * xstormy16-dis.c: Likewise. + * xstormy16-ibld.c: Likewise. + 2020-06-04 Jose E. Marchesi <jemarch@gnu.org> * cgen-dis.in (cpu_desc_list): New field `insn_endian'. diff --git a/opcodes/bpf-dis.c b/opcodes/bpf-dis.c index 21d9308..4d01112 100644 --- a/opcodes/bpf-dis.c +++ b/opcodes/bpf-dis.c @@ -376,7 +376,7 @@ print_insn (CGEN_CPU_DESC cd, /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */ basesize = cd->base_insn_bitsize < buflen * 8 ? cd->base_insn_bitsize : buflen * 8; - insn_value = cgen_get_insn_value (cd, buf, basesize); + insn_value = cgen_get_insn_value (cd, buf, basesize, cd->insn_endian); /* Fill in ex_info fields like read_insn would. Don't actually call diff --git a/opcodes/bpf-ibld.c b/opcodes/bpf-ibld.c index d5fa57a..392dceb 100644 --- a/opcodes/bpf-ibld.c +++ b/opcodes/bpf-ibld.c @@ -88,7 +88,7 @@ insert_1 (CGEN_CPU_DESC cd, unsigned long x,mask; int shift; - x = cgen_get_insn_value (cd, bufp, word_length); + x = cgen_get_insn_value (cd, bufp, word_length, cd->endian); /* Written this way to avoid undefined behaviour. */ mask = (((1L << (length - 1)) - 1) << 1) | 1; @@ -98,7 +98,7 @@ insert_1 (CGEN_CPU_DESC cd, shift = (word_length - (start + length)); x = (x & ~(mask << shift)) | ((value & mask) << shift); - cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x); + cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x, cd->endian); } #endif /* ! CGEN_INT_INSN_P */ @@ -269,8 +269,8 @@ insert_insn_normal (CGEN_CPU_DESC cd, #else cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize, - (unsigned) CGEN_FIELDS_BITSIZE (fields)), - value); + (unsigned) CGEN_FIELDS_BITSIZE (fields)), + value, cd->insn_endian); #endif /* ! CGEN_INT_INSN_P */ @@ -387,7 +387,7 @@ extract_1 (CGEN_CPU_DESC cd, unsigned long x; int shift; - x = cgen_get_insn_value (cd, bufp, word_length); + x = cgen_get_insn_value (cd, bufp, word_length, cd->endian); if (CGEN_INSN_LSB0_P) shift = (start + 1) - length; diff --git a/opcodes/cgen-dis.in b/opcodes/cgen-dis.in index 378b984..2d5feeb 100644 --- a/opcodes/cgen-dis.in +++ b/opcodes/cgen-dis.in @@ -210,7 +210,7 @@ print_insn (CGEN_CPU_DESC cd, /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */ basesize = cd->base_insn_bitsize < buflen * 8 ? cd->base_insn_bitsize : buflen * 8; - insn_value = cgen_get_insn_value (cd, buf, basesize); + insn_value = cgen_get_insn_value (cd, buf, basesize, cd->insn_endian); /* Fill in ex_info fields like read_insn would. Don't actually call diff --git a/opcodes/cgen-ibld.in b/opcodes/cgen-ibld.in index 6a9b97f..ae9d20d 100644 --- a/opcodes/cgen-ibld.in +++ b/opcodes/cgen-ibld.in @@ -87,7 +87,7 @@ insert_1 (CGEN_CPU_DESC cd, unsigned long x,mask; int shift; - x = cgen_get_insn_value (cd, bufp, word_length); + x = cgen_get_insn_value (cd, bufp, word_length, cd->endian); /* Written this way to avoid undefined behaviour. */ mask = (((1L << (length - 1)) - 1) << 1) | 1; @@ -97,7 +97,7 @@ insert_1 (CGEN_CPU_DESC cd, shift = (word_length - (start + length)); x = (x & ~(mask << shift)) | ((value & mask) << shift); - cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x); + cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x, cd->endian); } #endif /* ! CGEN_INT_INSN_P */ @@ -268,8 +268,8 @@ insert_insn_normal (CGEN_CPU_DESC cd, #else cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize, - (unsigned) CGEN_FIELDS_BITSIZE (fields)), - value); + (unsigned) CGEN_FIELDS_BITSIZE (fields)), + value, cd->insn_endian); #endif /* ! CGEN_INT_INSN_P */ @@ -386,7 +386,7 @@ extract_1 (CGEN_CPU_DESC cd, unsigned long x; int shift; - x = cgen_get_insn_value (cd, bufp, word_length); + x = cgen_get_insn_value (cd, bufp, word_length, cd->endian); if (CGEN_INSN_LSB0_P) shift = (start + 1) - length; diff --git a/opcodes/cgen-opc.c b/opcodes/cgen-opc.c index f3cfa9d..18f9aae 100644 --- a/opcodes/cgen-opc.c +++ b/opcodes/cgen-opc.c @@ -357,9 +357,10 @@ cgen_macro_insn_count (CGEN_CPU_DESC cd) /* Cover function to read and properly byteswap an insn value. */ CGEN_INSN_INT -cgen_get_insn_value (CGEN_CPU_DESC cd, unsigned char *buf, int length) +cgen_get_insn_value (CGEN_CPU_DESC cd, unsigned char *buf, int length, + int endian) { - int big_p = (cd->insn_endian == CGEN_ENDIAN_BIG); + int big_p = (endian == CGEN_ENDIAN_BIG); int insn_chunk_bitsize = cd->insn_chunk_bitsize; CGEN_INSN_INT value = 0; @@ -385,7 +386,7 @@ cgen_get_insn_value (CGEN_CPU_DESC cd, unsigned char *buf, int length) } else { - value = bfd_get_bits (buf, length, cd->insn_endian == CGEN_ENDIAN_BIG); + value = bfd_get_bits (buf, length, endian == CGEN_ENDIAN_BIG); } return value; @@ -397,9 +398,10 @@ void cgen_put_insn_value (CGEN_CPU_DESC cd, unsigned char *buf, int length, - CGEN_INSN_INT value) + CGEN_INSN_INT value, + int endian) { - int big_p = (cd->insn_endian == CGEN_ENDIAN_BIG); + int big_p = (endian == CGEN_ENDIAN_BIG); int insn_chunk_bitsize = cd->insn_chunk_bitsize; if (insn_chunk_bitsize != 0 && insn_chunk_bitsize < length) @@ -459,7 +461,8 @@ cgen_lookup_insn (CGEN_CPU_DESC cd, { info = NULL; insn_bytes_value = (unsigned char *) xmalloc (cd->max_insn_bitsize / 8); - cgen_put_insn_value (cd, insn_bytes_value, length, insn_int_value); + cgen_put_insn_value (cd, insn_bytes_value, length, insn_int_value, + cd->insn_endian); } else { @@ -467,7 +470,8 @@ cgen_lookup_insn (CGEN_CPU_DESC cd, ex_info.dis_info = NULL; ex_info.insn_bytes = insn_bytes_value; ex_info.valid = -1; - insn_int_value = cgen_get_insn_value (cd, insn_bytes_value, length); + insn_int_value = cgen_get_insn_value (cd, insn_bytes_value, length, + cd->insn_endian); } if (!insn) diff --git a/opcodes/epiphany-dis.c b/opcodes/epiphany-dis.c index 966b39f..83f8d79 100644 --- a/opcodes/epiphany-dis.c +++ b/opcodes/epiphany-dis.c @@ -451,7 +451,7 @@ print_insn (CGEN_CPU_DESC cd, /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */ basesize = cd->base_insn_bitsize < buflen * 8 ? cd->base_insn_bitsize : buflen * 8; - insn_value = cgen_get_insn_value (cd, buf, basesize); + insn_value = cgen_get_insn_value (cd, buf, basesize, cd->insn_endian); /* Fill in ex_info fields like read_insn would. Don't actually call diff --git a/opcodes/epiphany-ibld.c b/opcodes/epiphany-ibld.c index c23a969..4a974ed 100644 --- a/opcodes/epiphany-ibld.c +++ b/opcodes/epiphany-ibld.c @@ -88,7 +88,7 @@ insert_1 (CGEN_CPU_DESC cd, unsigned long x,mask; int shift; - x = cgen_get_insn_value (cd, bufp, word_length); + x = cgen_get_insn_value (cd, bufp, word_length, cd->endian); /* Written this way to avoid undefined behaviour. */ mask = (((1L << (length - 1)) - 1) << 1) | 1; @@ -98,7 +98,7 @@ insert_1 (CGEN_CPU_DESC cd, shift = (word_length - (start + length)); x = (x & ~(mask << shift)) | ((value & mask) << shift); - cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x); + cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x, cd->endian); } #endif /* ! CGEN_INT_INSN_P */ @@ -269,8 +269,8 @@ insert_insn_normal (CGEN_CPU_DESC cd, #else cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize, - (unsigned) CGEN_FIELDS_BITSIZE (fields)), - value); + (unsigned) CGEN_FIELDS_BITSIZE (fields)), + value, cd->insn_endian); #endif /* ! CGEN_INT_INSN_P */ @@ -387,7 +387,7 @@ extract_1 (CGEN_CPU_DESC cd, unsigned long x; int shift; - x = cgen_get_insn_value (cd, bufp, word_length); + x = cgen_get_insn_value (cd, bufp, word_length, cd->endian); if (CGEN_INSN_LSB0_P) shift = (start + 1) - length; diff --git a/opcodes/fr30-dis.c b/opcodes/fr30-dis.c index b98ea94..ed89926 100644 --- a/opcodes/fr30-dis.c +++ b/opcodes/fr30-dis.c @@ -472,7 +472,7 @@ print_insn (CGEN_CPU_DESC cd, /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */ basesize = cd->base_insn_bitsize < buflen * 8 ? cd->base_insn_bitsize : buflen * 8; - insn_value = cgen_get_insn_value (cd, buf, basesize); + insn_value = cgen_get_insn_value (cd, buf, basesize, cd->insn_endian); /* Fill in ex_info fields like read_insn would. Don't actually call diff --git a/opcodes/fr30-ibld.c b/opcodes/fr30-ibld.c index 5544d55..6816154 100644 --- a/opcodes/fr30-ibld.c +++ b/opcodes/fr30-ibld.c @@ -88,7 +88,7 @@ insert_1 (CGEN_CPU_DESC cd, unsigned long x,mask; int shift; - x = cgen_get_insn_value (cd, bufp, word_length); + x = cgen_get_insn_value (cd, bufp, word_length, cd->endian); /* Written this way to avoid undefined behaviour. */ mask = (((1L << (length - 1)) - 1) << 1) | 1; @@ -98,7 +98,7 @@ insert_1 (CGEN_CPU_DESC cd, shift = (word_length - (start + length)); x = (x & ~(mask << shift)) | ((value & mask) << shift); - cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x); + cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x, cd->endian); } #endif /* ! CGEN_INT_INSN_P */ @@ -269,8 +269,8 @@ insert_insn_normal (CGEN_CPU_DESC cd, #else cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize, - (unsigned) CGEN_FIELDS_BITSIZE (fields)), - value); + (unsigned) CGEN_FIELDS_BITSIZE (fields)), + value, cd->insn_endian); #endif /* ! CGEN_INT_INSN_P */ @@ -387,7 +387,7 @@ extract_1 (CGEN_CPU_DESC cd, unsigned long x; int shift; - x = cgen_get_insn_value (cd, bufp, word_length); + x = cgen_get_insn_value (cd, bufp, word_length, cd->endian); if (CGEN_INSN_LSB0_P) shift = (start + 1) - length; diff --git a/opcodes/frv-dis.c b/opcodes/frv-dis.c index 60f1a61..48b3359 100644 --- a/opcodes/frv-dis.c +++ b/opcodes/frv-dis.c @@ -569,7 +569,7 @@ print_insn (CGEN_CPU_DESC cd, /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */ basesize = cd->base_insn_bitsize < buflen * 8 ? cd->base_insn_bitsize : buflen * 8; - insn_value = cgen_get_insn_value (cd, buf, basesize); + insn_value = cgen_get_insn_value (cd, buf, basesize, cd->insn_endian); /* Fill in ex_info fields like read_insn would. Don't actually call diff --git a/opcodes/frv-ibld.c b/opcodes/frv-ibld.c index 0421884..43bccba 100644 --- a/opcodes/frv-ibld.c +++ b/opcodes/frv-ibld.c @@ -88,7 +88,7 @@ insert_1 (CGEN_CPU_DESC cd, unsigned long x,mask; int shift; - x = cgen_get_insn_value (cd, bufp, word_length); + x = cgen_get_insn_value (cd, bufp, word_length, cd->endian); /* Written this way to avoid undefined behaviour. */ mask = (((1L << (length - 1)) - 1) << 1) | 1; @@ -98,7 +98,7 @@ insert_1 (CGEN_CPU_DESC cd, shift = (word_length - (start + length)); x = (x & ~(mask << shift)) | ((value & mask) << shift); - cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x); + cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x, cd->endian); } #endif /* ! CGEN_INT_INSN_P */ @@ -269,8 +269,8 @@ insert_insn_normal (CGEN_CPU_DESC cd, #else cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize, - (unsigned) CGEN_FIELDS_BITSIZE (fields)), - value); + (unsigned) CGEN_FIELDS_BITSIZE (fields)), + value, cd->insn_endian); #endif /* ! CGEN_INT_INSN_P */ @@ -387,7 +387,7 @@ extract_1 (CGEN_CPU_DESC cd, unsigned long x; int shift; - x = cgen_get_insn_value (cd, bufp, word_length); + x = cgen_get_insn_value (cd, bufp, word_length, cd->endian); if (CGEN_INSN_LSB0_P) shift = (start + 1) - length; diff --git a/opcodes/ip2k-dis.c b/opcodes/ip2k-dis.c index 4a53a7c..6cc08ba 100644 --- a/opcodes/ip2k-dis.c +++ b/opcodes/ip2k-dis.c @@ -461,7 +461,7 @@ print_insn (CGEN_CPU_DESC cd, /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */ basesize = cd->base_insn_bitsize < buflen * 8 ? cd->base_insn_bitsize : buflen * 8; - insn_value = cgen_get_insn_value (cd, buf, basesize); + insn_value = cgen_get_insn_value (cd, buf, basesize, cd->insn_endian); /* Fill in ex_info fields like read_insn would. Don't actually call diff --git a/opcodes/ip2k-ibld.c b/opcodes/ip2k-ibld.c index 9258f7d..605d0bd 100644 --- a/opcodes/ip2k-ibld.c +++ b/opcodes/ip2k-ibld.c @@ -88,7 +88,7 @@ insert_1 (CGEN_CPU_DESC cd, unsigned long x,mask; int shift; - x = cgen_get_insn_value (cd, bufp, word_length); + x = cgen_get_insn_value (cd, bufp, word_length, cd->endian); /* Written this way to avoid undefined behaviour. */ mask = (((1L << (length - 1)) - 1) << 1) | 1; @@ -98,7 +98,7 @@ insert_1 (CGEN_CPU_DESC cd, shift = (word_length - (start + length)); x = (x & ~(mask << shift)) | ((value & mask) << shift); - cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x); + cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x, cd->endian); } #endif /* ! CGEN_INT_INSN_P */ @@ -269,8 +269,8 @@ insert_insn_normal (CGEN_CPU_DESC cd, #else cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize, - (unsigned) CGEN_FIELDS_BITSIZE (fields)), - value); + (unsigned) CGEN_FIELDS_BITSIZE (fields)), + value, cd->insn_endian); #endif /* ! CGEN_INT_INSN_P */ @@ -387,7 +387,7 @@ extract_1 (CGEN_CPU_DESC cd, unsigned long x; int shift; - x = cgen_get_insn_value (cd, bufp, word_length); + x = cgen_get_insn_value (cd, bufp, word_length, cd->endian); if (CGEN_INSN_LSB0_P) shift = (start + 1) - length; diff --git a/opcodes/iq2000-dis.c b/opcodes/iq2000-dis.c index 3aab139..fbe70c0 100644 --- a/opcodes/iq2000-dis.c +++ b/opcodes/iq2000-dis.c @@ -362,7 +362,7 @@ print_insn (CGEN_CPU_DESC cd, /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */ basesize = cd->base_insn_bitsize < buflen * 8 ? cd->base_insn_bitsize : buflen * 8; - insn_value = cgen_get_insn_value (cd, buf, basesize); + insn_value = cgen_get_insn_value (cd, buf, basesize, cd->insn_endian); /* Fill in ex_info fields like read_insn would. Don't actually call diff --git a/opcodes/iq2000-ibld.c b/opcodes/iq2000-ibld.c index 319e994..2a87c70 100644 --- a/opcodes/iq2000-ibld.c +++ b/opcodes/iq2000-ibld.c @@ -88,7 +88,7 @@ insert_1 (CGEN_CPU_DESC cd, unsigned long x,mask; int shift; - x = cgen_get_insn_value (cd, bufp, word_length); + x = cgen_get_insn_value (cd, bufp, word_length, cd->endian); /* Written this way to avoid undefined behaviour. */ mask = (((1L << (length - 1)) - 1) << 1) | 1; @@ -98,7 +98,7 @@ insert_1 (CGEN_CPU_DESC cd, shift = (word_length - (start + length)); x = (x & ~(mask << shift)) | ((value & mask) << shift); - cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x); + cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x, cd->endian); } #endif /* ! CGEN_INT_INSN_P */ @@ -269,8 +269,8 @@ insert_insn_normal (CGEN_CPU_DESC cd, #else cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize, - (unsigned) CGEN_FIELDS_BITSIZE (fields)), - value); + (unsigned) CGEN_FIELDS_BITSIZE (fields)), + value, cd->insn_endian); #endif /* ! CGEN_INT_INSN_P */ @@ -387,7 +387,7 @@ extract_1 (CGEN_CPU_DESC cd, unsigned long x; int shift; - x = cgen_get_insn_value (cd, bufp, word_length); + x = cgen_get_insn_value (cd, bufp, word_length, cd->endian); if (CGEN_INSN_LSB0_P) shift = (start + 1) - length; diff --git a/opcodes/lm32-dis.c b/opcodes/lm32-dis.c index 7ba84b3..e66ad06 100644 --- a/opcodes/lm32-dis.c +++ b/opcodes/lm32-dis.c @@ -320,7 +320,7 @@ print_insn (CGEN_CPU_DESC cd, /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */ basesize = cd->base_insn_bitsize < buflen * 8 ? cd->base_insn_bitsize : buflen * 8; - insn_value = cgen_get_insn_value (cd, buf, basesize); + insn_value = cgen_get_insn_value (cd, buf, basesize, cd->insn_endian); /* Fill in ex_info fields like read_insn would. Don't actually call diff --git a/opcodes/lm32-ibld.c b/opcodes/lm32-ibld.c index 9b594e8..2b0efda 100644 --- a/opcodes/lm32-ibld.c +++ b/opcodes/lm32-ibld.c @@ -88,7 +88,7 @@ insert_1 (CGEN_CPU_DESC cd, unsigned long x,mask; int shift; - x = cgen_get_insn_value (cd, bufp, word_length); + x = cgen_get_insn_value (cd, bufp, word_length, cd->endian); /* Written this way to avoid undefined behaviour. */ mask = (((1L << (length - 1)) - 1) << 1) | 1; @@ -98,7 +98,7 @@ insert_1 (CGEN_CPU_DESC cd, shift = (word_length - (start + length)); x = (x & ~(mask << shift)) | ((value & mask) << shift); - cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x); + cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x, cd->endian); } #endif /* ! CGEN_INT_INSN_P */ @@ -269,8 +269,8 @@ insert_insn_normal (CGEN_CPU_DESC cd, #else cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize, - (unsigned) CGEN_FIELDS_BITSIZE (fields)), - value); + (unsigned) CGEN_FIELDS_BITSIZE (fields)), + value, cd->insn_endian); #endif /* ! CGEN_INT_INSN_P */ @@ -387,7 +387,7 @@ extract_1 (CGEN_CPU_DESC cd, unsigned long x; int shift; - x = cgen_get_insn_value (cd, bufp, word_length); + x = cgen_get_insn_value (cd, bufp, word_length, cd->endian); if (CGEN_INSN_LSB0_P) shift = (start + 1) - length; diff --git a/opcodes/m32c-dis.c b/opcodes/m32c-dis.c index 41afca3..19135fa 100644 --- a/opcodes/m32c-dis.c +++ b/opcodes/m32c-dis.c @@ -1064,7 +1064,7 @@ print_insn (CGEN_CPU_DESC cd, /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */ basesize = cd->base_insn_bitsize < buflen * 8 ? cd->base_insn_bitsize : buflen * 8; - insn_value = cgen_get_insn_value (cd, buf, basesize); + insn_value = cgen_get_insn_value (cd, buf, basesize, cd->insn_endian); /* Fill in ex_info fields like read_insn would. Don't actually call diff --git a/opcodes/m32c-ibld.c b/opcodes/m32c-ibld.c index c1fca2e..6ad4da9 100644 --- a/opcodes/m32c-ibld.c +++ b/opcodes/m32c-ibld.c @@ -88,7 +88,7 @@ insert_1 (CGEN_CPU_DESC cd, unsigned long x,mask; int shift; - x = cgen_get_insn_value (cd, bufp, word_length); + x = cgen_get_insn_value (cd, bufp, word_length, cd->endian); /* Written this way to avoid undefined behaviour. */ mask = (((1L << (length - 1)) - 1) << 1) | 1; @@ -98,7 +98,7 @@ insert_1 (CGEN_CPU_DESC cd, shift = (word_length - (start + length)); x = (x & ~(mask << shift)) | ((value & mask) << shift); - cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x); + cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x, cd->endian); } #endif /* ! CGEN_INT_INSN_P */ @@ -269,8 +269,8 @@ insert_insn_normal (CGEN_CPU_DESC cd, #else cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize, - (unsigned) CGEN_FIELDS_BITSIZE (fields)), - value); + (unsigned) CGEN_FIELDS_BITSIZE (fields)), + value, cd->insn_endian); #endif /* ! CGEN_INT_INSN_P */ @@ -387,7 +387,7 @@ extract_1 (CGEN_CPU_DESC cd, unsigned long x; int shift; - x = cgen_get_insn_value (cd, bufp, word_length); + x = cgen_get_insn_value (cd, bufp, word_length, cd->endian); if (CGEN_INSN_LSB0_P) shift = (start + 1) - length; diff --git a/opcodes/m32r-dis.c b/opcodes/m32r-dis.c index e666739..e15d3c3 100644 --- a/opcodes/m32r-dis.c +++ b/opcodes/m32r-dis.c @@ -452,7 +452,7 @@ print_insn (CGEN_CPU_DESC cd, /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */ basesize = cd->base_insn_bitsize < buflen * 8 ? cd->base_insn_bitsize : buflen * 8; - insn_value = cgen_get_insn_value (cd, buf, basesize); + insn_value = cgen_get_insn_value (cd, buf, basesize, cd->insn_endian); /* Fill in ex_info fields like read_insn would. Don't actually call diff --git a/opcodes/m32r-ibld.c b/opcodes/m32r-ibld.c index ddebc32..559f471 100644 --- a/opcodes/m32r-ibld.c +++ b/opcodes/m32r-ibld.c @@ -88,7 +88,7 @@ insert_1 (CGEN_CPU_DESC cd, unsigned long x,mask; int shift; - x = cgen_get_insn_value (cd, bufp, word_length); + x = cgen_get_insn_value (cd, bufp, word_length, cd->endian); /* Written this way to avoid undefined behaviour. */ mask = (((1L << (length - 1)) - 1) << 1) | 1; @@ -98,7 +98,7 @@ insert_1 (CGEN_CPU_DESC cd, shift = (word_length - (start + length)); x = (x & ~(mask << shift)) | ((value & mask) << shift); - cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x); + cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x, cd->endian); } #endif /* ! CGEN_INT_INSN_P */ @@ -269,8 +269,8 @@ insert_insn_normal (CGEN_CPU_DESC cd, #else cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize, - (unsigned) CGEN_FIELDS_BITSIZE (fields)), - value); + (unsigned) CGEN_FIELDS_BITSIZE (fields)), + value, cd->insn_endian); #endif /* ! CGEN_INT_INSN_P */ @@ -387,7 +387,7 @@ extract_1 (CGEN_CPU_DESC cd, unsigned long x; int shift; - x = cgen_get_insn_value (cd, bufp, word_length); + x = cgen_get_insn_value (cd, bufp, word_length, cd->endian); if (CGEN_INSN_LSB0_P) shift = (start + 1) - length; diff --git a/opcodes/mep-dis.c b/opcodes/mep-dis.c index d2df588..1292d83 100644 --- a/opcodes/mep-dis.c +++ b/opcodes/mep-dis.c @@ -467,7 +467,7 @@ print_slot_insn (CGEN_CPU_DESC cd, CGEN_INSN_INT insn_value; CGEN_EXTRACT_INFO ex_info; - insn_value = cgen_get_insn_value (cd, buf, 32); + insn_value = cgen_get_insn_value (cd, buf, 32, cd->insn_endian); /* Fill in ex_info fields like read_insn would. Don't actually call read_insn, since the incoming buffer is already read (and possibly @@ -1360,7 +1360,7 @@ print_insn (CGEN_CPU_DESC cd, /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */ basesize = cd->base_insn_bitsize < buflen * 8 ? cd->base_insn_bitsize : buflen * 8; - insn_value = cgen_get_insn_value (cd, buf, basesize); + insn_value = cgen_get_insn_value (cd, buf, basesize, cd->insn_endian); /* Fill in ex_info fields like read_insn would. Don't actually call diff --git a/opcodes/mep-ibld.c b/opcodes/mep-ibld.c index 6a73f41..66a30e1 100644 --- a/opcodes/mep-ibld.c +++ b/opcodes/mep-ibld.c @@ -88,7 +88,7 @@ insert_1 (CGEN_CPU_DESC cd, unsigned long x,mask; int shift; - x = cgen_get_insn_value (cd, bufp, word_length); + x = cgen_get_insn_value (cd, bufp, word_length, cd->endian); /* Written this way to avoid undefined behaviour. */ mask = (((1L << (length - 1)) - 1) << 1) | 1; @@ -98,7 +98,7 @@ insert_1 (CGEN_CPU_DESC cd, shift = (word_length - (start + length)); x = (x & ~(mask << shift)) | ((value & mask) << shift); - cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x); + cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x, cd->endian); } #endif /* ! CGEN_INT_INSN_P */ @@ -269,8 +269,8 @@ insert_insn_normal (CGEN_CPU_DESC cd, #else cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize, - (unsigned) CGEN_FIELDS_BITSIZE (fields)), - value); + (unsigned) CGEN_FIELDS_BITSIZE (fields)), + value, cd->insn_endian); #endif /* ! CGEN_INT_INSN_P */ @@ -387,7 +387,7 @@ extract_1 (CGEN_CPU_DESC cd, unsigned long x; int shift; - x = cgen_get_insn_value (cd, bufp, word_length); + x = cgen_get_insn_value (cd, bufp, word_length, cd->endian); if (CGEN_INSN_LSB0_P) shift = (start + 1) - length; diff --git a/opcodes/mt-dis.c b/opcodes/mt-dis.c index 3d552e8..b0358e3 100644 --- a/opcodes/mt-dis.c +++ b/opcodes/mt-dis.c @@ -463,7 +463,7 @@ print_insn (CGEN_CPU_DESC cd, /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */ basesize = cd->base_insn_bitsize < buflen * 8 ? cd->base_insn_bitsize : buflen * 8; - insn_value = cgen_get_insn_value (cd, buf, basesize); + insn_value = cgen_get_insn_value (cd, buf, basesize, cd->insn_endian); /* Fill in ex_info fields like read_insn would. Don't actually call diff --git a/opcodes/mt-ibld.c b/opcodes/mt-ibld.c index 53a0775..683b76b 100644 --- a/opcodes/mt-ibld.c +++ b/opcodes/mt-ibld.c @@ -88,7 +88,7 @@ insert_1 (CGEN_CPU_DESC cd, unsigned long x,mask; int shift; - x = cgen_get_insn_value (cd, bufp, word_length); + x = cgen_get_insn_value (cd, bufp, word_length, cd->endian); /* Written this way to avoid undefined behaviour. */ mask = (((1L << (length - 1)) - 1) << 1) | 1; @@ -98,7 +98,7 @@ insert_1 (CGEN_CPU_DESC cd, shift = (word_length - (start + length)); x = (x & ~(mask << shift)) | ((value & mask) << shift); - cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x); + cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x, cd->endian); } #endif /* ! CGEN_INT_INSN_P */ @@ -269,8 +269,8 @@ insert_insn_normal (CGEN_CPU_DESC cd, #else cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize, - (unsigned) CGEN_FIELDS_BITSIZE (fields)), - value); + (unsigned) CGEN_FIELDS_BITSIZE (fields)), + value, cd->insn_endian); #endif /* ! CGEN_INT_INSN_P */ @@ -387,7 +387,7 @@ extract_1 (CGEN_CPU_DESC cd, unsigned long x; int shift; - x = cgen_get_insn_value (cd, bufp, word_length); + x = cgen_get_insn_value (cd, bufp, word_length, cd->endian); if (CGEN_INSN_LSB0_P) shift = (start + 1) - length; diff --git a/opcodes/or1k-dis.c b/opcodes/or1k-dis.c index d350d2b..87ff206 100644 --- a/opcodes/or1k-dis.c +++ b/opcodes/or1k-dis.c @@ -347,7 +347,7 @@ print_insn (CGEN_CPU_DESC cd, /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */ basesize = cd->base_insn_bitsize < buflen * 8 ? cd->base_insn_bitsize : buflen * 8; - insn_value = cgen_get_insn_value (cd, buf, basesize); + insn_value = cgen_get_insn_value (cd, buf, basesize, cd->insn_endian); /* Fill in ex_info fields like read_insn would. Don't actually call diff --git a/opcodes/or1k-ibld.c b/opcodes/or1k-ibld.c index 2e476cb..7b89260 100644 --- a/opcodes/or1k-ibld.c +++ b/opcodes/or1k-ibld.c @@ -88,7 +88,7 @@ insert_1 (CGEN_CPU_DESC cd, unsigned long x,mask; int shift; - x = cgen_get_insn_value (cd, bufp, word_length); + x = cgen_get_insn_value (cd, bufp, word_length, cd->endian); /* Written this way to avoid undefined behaviour. */ mask = (((1L << (length - 1)) - 1) << 1) | 1; @@ -98,7 +98,7 @@ insert_1 (CGEN_CPU_DESC cd, shift = (word_length - (start + length)); x = (x & ~(mask << shift)) | ((value & mask) << shift); - cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x); + cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x, cd->endian); } #endif /* ! CGEN_INT_INSN_P */ @@ -269,8 +269,8 @@ insert_insn_normal (CGEN_CPU_DESC cd, #else cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize, - (unsigned) CGEN_FIELDS_BITSIZE (fields)), - value); + (unsigned) CGEN_FIELDS_BITSIZE (fields)), + value, cd->insn_endian); #endif /* ! CGEN_INT_INSN_P */ @@ -387,7 +387,7 @@ extract_1 (CGEN_CPU_DESC cd, unsigned long x; int shift; - x = cgen_get_insn_value (cd, bufp, word_length); + x = cgen_get_insn_value (cd, bufp, word_length, cd->endian); if (CGEN_INSN_LSB0_P) shift = (start + 1) - length; diff --git a/opcodes/xc16x-dis.c b/opcodes/xc16x-dis.c index 2cf926b..d4c24f0 100644 --- a/opcodes/xc16x-dis.c +++ b/opcodes/xc16x-dis.c @@ -593,7 +593,7 @@ print_insn (CGEN_CPU_DESC cd, /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */ basesize = cd->base_insn_bitsize < buflen * 8 ? cd->base_insn_bitsize : buflen * 8; - insn_value = cgen_get_insn_value (cd, buf, basesize); + insn_value = cgen_get_insn_value (cd, buf, basesize, cd->insn_endian); /* Fill in ex_info fields like read_insn would. Don't actually call diff --git a/opcodes/xc16x-ibld.c b/opcodes/xc16x-ibld.c index 6b228bc..b2802fe 100644 --- a/opcodes/xc16x-ibld.c +++ b/opcodes/xc16x-ibld.c @@ -88,7 +88,7 @@ insert_1 (CGEN_CPU_DESC cd, unsigned long x,mask; int shift; - x = cgen_get_insn_value (cd, bufp, word_length); + x = cgen_get_insn_value (cd, bufp, word_length, cd->endian); /* Written this way to avoid undefined behaviour. */ mask = (((1L << (length - 1)) - 1) << 1) | 1; @@ -98,7 +98,7 @@ insert_1 (CGEN_CPU_DESC cd, shift = (word_length - (start + length)); x = (x & ~(mask << shift)) | ((value & mask) << shift); - cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x); + cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x, cd->endian); } #endif /* ! CGEN_INT_INSN_P */ @@ -269,8 +269,8 @@ insert_insn_normal (CGEN_CPU_DESC cd, #else cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize, - (unsigned) CGEN_FIELDS_BITSIZE (fields)), - value); + (unsigned) CGEN_FIELDS_BITSIZE (fields)), + value, cd->insn_endian); #endif /* ! CGEN_INT_INSN_P */ @@ -387,7 +387,7 @@ extract_1 (CGEN_CPU_DESC cd, unsigned long x; int shift; - x = cgen_get_insn_value (cd, bufp, word_length); + x = cgen_get_insn_value (cd, bufp, word_length, cd->endian); if (CGEN_INSN_LSB0_P) shift = (start + 1) - length; diff --git a/opcodes/xstormy16-dis.c b/opcodes/xstormy16-dis.c index 8382c3d..c272316 100644 --- a/opcodes/xstormy16-dis.c +++ b/opcodes/xstormy16-dis.c @@ -341,7 +341,7 @@ print_insn (CGEN_CPU_DESC cd, /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */ basesize = cd->base_insn_bitsize < buflen * 8 ? cd->base_insn_bitsize : buflen * 8; - insn_value = cgen_get_insn_value (cd, buf, basesize); + insn_value = cgen_get_insn_value (cd, buf, basesize, cd->insn_endian); /* Fill in ex_info fields like read_insn would. Don't actually call diff --git a/opcodes/xstormy16-ibld.c b/opcodes/xstormy16-ibld.c index 70cf88d..eaffbee 100644 --- a/opcodes/xstormy16-ibld.c +++ b/opcodes/xstormy16-ibld.c @@ -88,7 +88,7 @@ insert_1 (CGEN_CPU_DESC cd, unsigned long x,mask; int shift; - x = cgen_get_insn_value (cd, bufp, word_length); + x = cgen_get_insn_value (cd, bufp, word_length, cd->endian); /* Written this way to avoid undefined behaviour. */ mask = (((1L << (length - 1)) - 1) << 1) | 1; @@ -98,7 +98,7 @@ insert_1 (CGEN_CPU_DESC cd, shift = (word_length - (start + length)); x = (x & ~(mask << shift)) | ((value & mask) << shift); - cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x); + cgen_put_insn_value (cd, bufp, word_length, (bfd_vma) x, cd->endian); } #endif /* ! CGEN_INT_INSN_P */ @@ -269,8 +269,8 @@ insert_insn_normal (CGEN_CPU_DESC cd, #else cgen_put_insn_value (cd, buffer, min ((unsigned) cd->base_insn_bitsize, - (unsigned) CGEN_FIELDS_BITSIZE (fields)), - value); + (unsigned) CGEN_FIELDS_BITSIZE (fields)), + value, cd->insn_endian); #endif /* ! CGEN_INT_INSN_P */ @@ -387,7 +387,7 @@ extract_1 (CGEN_CPU_DESC cd, unsigned long x; int shift; - x = cgen_get_insn_value (cd, bufp, word_length); + x = cgen_get_insn_value (cd, bufp, word_length, cd->endian); if (CGEN_INSN_LSB0_P) shift = (start + 1) - length; |