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-rw-r--r--gas/ChangeLog5
-rw-r--r--gas/config/tc-aarch64.c16
-rw-r--r--gas/testsuite/ChangeLog7
-rw-r--r--gas/testsuite/gas/aarch64/illegal.l9
-rw-r--r--gas/testsuite/gas/aarch64/illegal.s8
-rw-r--r--gas/testsuite/gas/aarch64/sysreg-1.d10
-rw-r--r--gas/testsuite/gas/aarch64/sysreg-1.s6
-rw-r--r--opcodes/ChangeLog5
-rw-r--r--opcodes/aarch64-dis-2.c120
-rw-r--r--opcodes/aarch64-tbl.h4
10 files changed, 75 insertions, 115 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog
index 687c800..8dcd6ff 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,5 +1,10 @@
2014-09-03 Jiong Wang <jiong.wang@arm.com>
+ * config/tc-aarch64.c (parse_sys_reg): Remove the restriction on op0
+ field.
+
+2014-09-03 Jiong Wang <jiong.wang@arm.com>
+
* config/tc-aarch64.c (parse_operands): Recognize PAIRREG.
(aarch64_features): Add entry for lse extension.
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index b322d35..03fddd1 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -3333,19 +3333,13 @@ parse_sys_reg (char **str, struct hash_control *sys_regs, int imple_defined_p)
return PARSE_FAIL;
else
{
- /* Parse S<op0>_<op1>_<Cn>_<Cm>_<op2>, the implementation defined
- registers. */
+ /* Parse S<op0>_<op1>_<Cn>_<Cm>_<op2>. */
unsigned int op0, op1, cn, cm, op2;
- if (sscanf (buf, "s%u_%u_c%u_c%u_%u", &op0, &op1, &cn, &cm, &op2) != 5)
+
+ if (sscanf (buf, "s%u_%u_c%u_c%u_%u", &op0, &op1, &cn, &cm, &op2)
+ != 5)
return PARSE_FAIL;
- /* The architecture specifies the encoding space for implementation
- defined registers as:
- op0 op1 CRn CRm op2
- 1x xxx 1x11 xxxx xxx
- For convenience GAS accepts a wider encoding space, as follows:
- op0 op1 CRn CRm op2
- 1x xxx xxxx xxxx xxx */
- if ((op0 != 2 && op0 != 3) || op1 > 7 || cn > 15 || cm > 15 || op2 > 7)
+ if (op0 > 3 || op1 > 7 || cn > 15 || cm > 15 || op2 > 7)
return PARSE_FAIL;
value = (op0 << 14) | (op1 << 11) | (cn << 7) | (cm << 3) | op2;
}
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index e81cdda..db580e4 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,5 +1,12 @@
2014-09-03 Jiong Wang <jiong.wang@arm.com>
+ * gas/aarch64/illegal.s: Update testcase.
+ * gas/aarch64/illegal.d: Likewise.
+ * gas/aarch64/sysreg-1.s: Likewise.
+ * gas/aarch64/sysreg-1.d: Likewise.
+
+2014-09-03 Jiong Wang <jiong.wang@arm.com>
+
* gas/aarch64/lse-atomic.d: New.
* gas/aarch64/lse-atomic.s: Likewise.
* gas/aarch64/illegal-lse.d: Likewise.
diff --git a/gas/testsuite/gas/aarch64/illegal.l b/gas/testsuite/gas/aarch64/illegal.l
index 044b787..0e8c7eb 100644
--- a/gas/testsuite/gas/aarch64/illegal.l
+++ b/gas/testsuite/gas/aarch64/illegal.l
@@ -519,7 +519,7 @@
[^:]*:494: Error: .*`bfi x3,x7,#31,#48'
[^:]*:496: Error: .*`str x1,page_table_count'
[^:]*:498: Error: .*`prfm PLDL3KEEP,\[x9,x15,sxtx#2\]'
-[^:]*:500: Error: .*`mrs x5,S1_0_C13_C8_0'
+[^:]*:500: Error: .*`mrs x5,S1_0_C17_C8_0'
[^:]*:502: Error: .*`msr S3_1_C11_C15_-1,x7'
[^:]*:503: Error: .*`msr S3_1_11_15_1,x7'
[^:]*:506: Error: .*`movi w1,#15'
@@ -562,4 +562,9 @@
[^:]*:561: Error: .*`csetm w0,nv'
[^:]*:562: Error: .*`cneg w0,w1,al'
[^:]*:563: Error: .*`cneg w0,w1,nv'
-[^:]*:563: Error: .*
+[^:]*:565: Error: .*`mrs x5,S4_0_C12_C8_0'
+[^:]*:566: Error: .*`mrs x6,S0_8_C11_C7_5'
+[^:]*:567: Error: .*`mrs x7,S1_1_C16_C6_6'
+[^:]*:568: Error: .*`mrs x8,S2_2_C15_C16_7'
+[^:]*:569: Error: .*`mrs x9,S3_3_C14_C15_8'
+[^:]*:569: Error: .*
diff --git a/gas/testsuite/gas/aarch64/illegal.s b/gas/testsuite/gas/aarch64/illegal.s
index f4746a5..9cf0600 100644
--- a/gas/testsuite/gas/aarch64/illegal.s
+++ b/gas/testsuite/gas/aarch64/illegal.s
@@ -497,7 +497,7 @@
prfm PLDL3KEEP, [x9, x15, sxtx #2]
- mrs x5, S1_0_C13_C8_0
+ mrs x5, S1_0_C17_C8_0
msr S3_1_C13_C15_1, x7
msr S3_1_C11_C15_-1, x7
msr S3_1_11_15_1, x7
@@ -561,3 +561,9 @@ one_label:
csetm w0, nv
cneg w0, w1, al
cneg w0, w1, nv
+
+ mrs x5, S4_0_C12_C8_0
+ mrs x6, S0_8_C11_C7_5
+ mrs x7, S1_1_C16_C6_6
+ mrs x8, S2_2_C15_C16_7
+ mrs x9, S3_3_C14_C15_8
diff --git a/gas/testsuite/gas/aarch64/sysreg-1.d b/gas/testsuite/gas/aarch64/sysreg-1.d
index 81717c1..c6be2c4 100644
--- a/gas/testsuite/gas/aarch64/sysreg-1.d
+++ b/gas/testsuite/gas/aarch64/sysreg-1.d
@@ -4283,3 +4283,13 @@ Disassembly of section \.text:
42cc: d53c400f mrs x15, spsr_el2
42d0: d51e400f msr spsr_el3, x15
42d4: d53e400f mrs x15, spsr_el3
+ 42d8: d500000f msr s0_0_c0_c0_0, x15
+ 42dc: d520000f mrs x15, s0_0_c0_c0_0
+ 42e0: d50ffffb sys #7, C15, C15, #7, x27
+ 42e4: d52ffffb sysl x27, #7, C15, C15, #7
+ 42e8: d514680e msr s2_4_c6_c8_0, x14
+ 42ec: d534680e mrs x14, s2_4_c6_c8_0
+ 42f0: d50ae444 sys #2, C14, C4, #2, x4
+ 42f4: d52ae444 sysl x4, #2, C14, C4, #2
+ 42f8: d501d167 msr s0_1_c13_c1_3, x7
+ 42fc: d521d167 mrs x7, s0_1_c13_c1_3
diff --git a/gas/testsuite/gas/aarch64/sysreg-1.s b/gas/testsuite/gas/aarch64/sysreg-1.s
index 700dd24..fc08328 100644
--- a/gas/testsuite/gas/aarch64/sysreg-1.s
+++ b/gas/testsuite/gas/aarch64/sysreg-1.s
@@ -166,3 +166,9 @@
rw_sys_reg sys_reg=spsr_el1 xreg=x15 r=1 w=1
rw_sys_reg sys_reg=spsr_el2 xreg=x15 r=1 w=1
rw_sys_reg sys_reg=spsr_el3 xreg=x15 r=1 w=1
+
+ rw_sys_reg sys_reg=s0_0_C0_C0_0 xreg=x15 r=1 w=1
+ rw_sys_reg sys_reg=s1_7_C15_C15_7 xreg=x27 r=1 w=1
+ rw_sys_reg sys_reg=s2_4_C6_C8_0 xreg=x14 r=1 w=1
+ rw_sys_reg sys_reg=s1_2_C14_C4_2 xreg=x4 r=1 w=1
+ rw_sys_reg sys_reg=s0_1_C13_C1_3 xreg=x7 r=1 w=1
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index a0b4e19..83118a5 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,5 +1,10 @@
2014-09-03 Jiong Wang <jiong.wang@arm.com>
+ * aarch64-tbl.h (aarch64_opcode_table): Update encoding for mrs/msr.
+ * aarch64-dis-2.c: Update auto-generated file.
+
+2014-09-03 Jiong Wang <jiong.wang@arm.com>
+
* aarch64-tbl.h (QL_R4NIL): New qualifiers.
(aarch64_feature_lse): New feature added.
(LSE): New Added.
diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c
index a0f1a38..fd1da83 100644
--- a/opcodes/aarch64-dis-2.c
+++ b/opcodes/aarch64-dis-2.c
@@ -3250,109 +3250,21 @@ aarch64_opcode_lookup_1 (uint32_t word)
}
else
{
- if (((word >> 20) & 0x1) == 0)
+ if (((word >> 21) & 0x1) == 0)
{
- if (((word >> 19) & 0x1) == 0)
- {
- if (((word >> 12) & 0x1) == 0)
- {
- if (((word >> 13) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xxxxxxxxxxxx00xxxxx00xxx1x10x01x
- msr. */
- return 955;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xxxxxxxxxxxx01xxxxx00xxx1x10x01x
- hint. */
- return 956;
- }
- }
- else
- {
- if (((word >> 5) & 0x1) == 0)
- {
- if (((word >> 6) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xxxxx00xxxxx1xxxxxx00xxx1x10x01x
- dsb. */
- return 964;
- }
- else
- {
- if (((word >> 7) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xxxxx010xxxx1xxxxxx00xxx1x10x01x
- clrex. */
- return 963;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xxxxx011xxxx1xxxxxx00xxx1x10x01x
- isb. */
- return 966;
- }
- }
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xxxxx1xxxxxx1xxxxxx00xxx1x10x01x
- dmb. */
- return 965;
- }
- }
- }
- else
- {
- if (((word >> 21) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xxxxxxxxxxxxxxxxxxx100xx1x10x01x
- sys. */
- return 967;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xxxxxxxxxxxxxxxxxxx101xx1x10x01x
- sysl. */
- return 973;
- }
- }
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxxxxxxxx0xx1x10x01x
+ msr. */
+ return 955;
}
else
{
- if (((word >> 21) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xxxxxxxxxxxxxxxxxxxx10xx1x10x01x
- msr. */
- return 972;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- xxxxxxxxxxxxxxxxxxxx11xx1x10x01x
- mrs. */
- return 974;
- }
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ xxxxxxxxxxxxxxxxxxxxx1xx1x10x01x
+ sysl. */
+ return 973;
}
}
}
@@ -8799,6 +8711,16 @@ aarch64_find_next_opcode (const aarch64_opcode *opcode)
case 743: return NULL; /* stp --> NULL. */
case 740: value = 744; break; /* ldnp --> ldp. */
case 744: return NULL; /* ldp --> NULL. */
+ case 955: value = 956; break; /* msr --> hint. */
+ case 956: value = 963; break; /* hint --> clrex. */
+ case 963: value = 964; break; /* clrex --> dsb. */
+ case 964: value = 965; break; /* dsb --> dmb. */
+ case 965: value = 966; break; /* dmb --> isb. */
+ case 966: value = 967; break; /* isb --> sys. */
+ case 967: value = 972; break; /* sys --> msr. */
+ case 972: return NULL; /* msr --> NULL. */
+ case 973: value = 974; break; /* sysl --> mrs. */
+ case 974: return NULL; /* mrs --> NULL. */
case 355: value = 356; break; /* st4 --> st1. */
case 356: value = 357; break; /* st1 --> st2. */
case 357: value = 358; break; /* st2 --> st3. */
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 13a205f..1a16656 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -2272,9 +2272,9 @@ struct aarch64_opcode aarch64_opcode_table[] =
{"dc", 0xd5080000, 0xfff80000, ic_system, 0, CORE, OP2 (SYSREG_DC, Rt), QL_SRC_X, F_ALIAS},
{"ic", 0xd5080000, 0xfff80000, ic_system, 0, CORE, OP2 (SYSREG_IC, Rt_SYS), QL_SRC_X, F_ALIAS | F_OPD1_OPT | F_DEFAULT (0x1F)},
{"tlbi", 0xd5080000, 0xfff80000, ic_system, 0, CORE, OP2 (SYSREG_TLBI, Rt_SYS), QL_SRC_X, F_ALIAS | F_OPD1_OPT | F_DEFAULT (0x1F)},
- {"msr", 0xd5100000, 0xfff00000, ic_system, 0, CORE, OP2 (SYSREG, Rt), QL_SRC_X, 0},
+ {"msr", 0xd5000000, 0xffe00000, ic_system, 0, CORE, OP2 (SYSREG, Rt), QL_SRC_X, 0},
{"sysl", 0xd5280000, 0xfff80000, ic_system, 0, CORE, OP5 (Rt, UIMM3_OP1, Cn, Cm, UIMM3_OP2), QL_SYSL, 0},
- {"mrs", 0xd5300000, 0xfff00000, ic_system, 0, CORE, OP2 (Rt, SYSREG), QL_DST_X, 0},
+ {"mrs", 0xd5200000, 0xffe00000, ic_system, 0, CORE, OP2 (Rt, SYSREG), QL_DST_X, 0},
/* Test & branch (immediate). */
{"tbz", 0x36000000, 0x7f000000, testbranch, 0, CORE, OP3 (Rt, BIT_NUM, ADDR_PCREL14), QL_PCREL_14, 0},
{"tbnz", 0x37000000, 0x7f000000, testbranch, 0, CORE, OP3 (Rt, BIT_NUM, ADDR_PCREL14), QL_PCREL_14, 0},
generated by cgit v1.1 at 2024-11-03 05:38:57 +0000