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-rw-r--r--gas/ChangeLog18
-rw-r--r--gas/config/tc-sparc.c112
-rw-r--r--gas/testsuite/gas/sparc/hwcaps-bump.l2
-rw-r--r--gas/testsuite/gas/sparc/hwcaps-bump.s5
-rw-r--r--gas/testsuite/gas/sparc/sparc.exp1
-rw-r--r--include/ChangeLog5
-rw-r--r--include/opcode/sparc.h4
-rw-r--r--opcodes/ChangeLog16
-rw-r--r--opcodes/sparc-opc.c49
9 files changed, 139 insertions, 73 deletions
diff --git a/gas/ChangeLog b/gas/ChangeLog
index 58142ea..b2f6040 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,21 @@
+2016-11-22 Jose E. Marchesi <jose.marchesi@oracle.com>
+
+ * config/tc-sparc.c: Move HWS_* and HWS2_* definitions to
+ opcodes/sparc-opc.c.
+ (sparc_arch): Clarify the new role of the hwcap_allowed and
+ hwcap2_allowed fields.
+ (sparc_arch_table): Remove HWS_* and HWS2_* instances from
+ hwcap_allowed and hwcap2_allowed respectively.
+ (md_parse_option): Include the opcode arch hwcaps when processing
+ -A.
+ (sparc_ip): Use the current opcode arch hwcaps to update
+ hwcap_allowed, as well as the hwcaps of the instruction triggering
+ the bump.
+ * testsuite/gas/sparc/hwcaps-bump.s: New file.
+ * testsuite/gas/sparc/hwcaps-bump.l: Likewise.
+ * testsuite/gas/sparc/sparc.exp (gas_64_check): Run tests in
+ hwcaps-bump.
+
2016-11-22 Claudiu Zissulescu <claziss@synopsys.com>
* testsuite/gas/arc/b.d: Update test result.
diff --git a/gas/config/tc-sparc.c b/gas/config/tc-sparc.c
index d7b9a98..edece05 100644
--- a/gas/config/tc-sparc.c
+++ b/gas/config/tc-sparc.c
@@ -226,25 +226,6 @@ static void output_insn (const struct sparc_opcode *, struct sparc_it *);
enum sparc_arch_types {v6, v7, v8, leon, sparclet, sparclite, sparc86x, v8plus,
v8plusa, v9, v9a, v9b, v9_64};
-/* Hardware capability sets, used to keep sparc_arch_table easy to
- read. */
-#define HWS_V8 HWCAP_MUL32 | HWCAP_DIV32 | HWCAP_FSMULD
-#define HWS_V9 HWS_V8 | HWCAP_POPC
-#define HWS_VA HWS_V9 | HWCAP_VIS
-#define HWS_VB HWS_VA | HWCAP_VIS2
-#define HWS_VC HWS_VB | HWCAP_ASI_BLK_INIT
-#define HWS_VD HWS_VC | HWCAP_FMAF | HWCAP_VIS3 | HWCAP_HPC
-#define HWS_VE HWS_VD \
- | HWCAP_AES | HWCAP_DES | HWCAP_KASUMI | HWCAP_CAMELLIA \
- | HWCAP_MD5 | HWCAP_SHA1 | HWCAP_SHA256 |HWCAP_SHA512 | HWCAP_MPMUL \
- | HWCAP_MONT | HWCAP_CRC32C | HWCAP_CBCOND | HWCAP_PAUSE
-#define HWS_VV HWS_VE | HWCAP_FJFMAU | HWCAP_IMA
-#define HWS_VM HWS_VV
-
-#define HWS2_VM \
- HWCAP2_VIS3B | HWCAP2_ADP | HWCAP2_SPARC5 | HWCAP2_MWAIT \
- | HWCAP2_XMPMUL | HWCAP2_XMONT
-
static struct sparc_arch {
const char *name;
const char *opcode_arch;
@@ -254,50 +235,53 @@ static struct sparc_arch {
int default_arch_size;
/* Allowable arg to -A? */
int user_option_p;
+ /* Extra hardware capabilities allowed. These are added to the
+ hardware capabilities associated with the opcode
+ architecture. */
int hwcap_allowed;
int hwcap2_allowed;
} sparc_arch_table[] = {
{ "v6", "v6", v6, 0, 1, 0, 0 },
{ "v7", "v7", v7, 0, 1, 0, 0 },
- { "v8", "v8", v8, 32, 1, HWS_V8, 0 },
- { "v8a", "v8", v8, 32, 1, HWS_V8, 0 },
- { "sparc", "v9", v9, 0, 1, HWCAP_V8PLUS|HWS_V9, 0 },
- { "sparcvis", "v9a", v9, 0, 1, HWS_VA, 0 },
- { "sparcvis2", "v9b", v9, 0, 1, HWS_VB, 0 },
- { "sparcfmaf", "v9b", v9, 0, 1, HWS_VB|HWCAP_FMAF, 0 },
- { "sparcima", "v9b", v9, 0, 1, HWS_VB|HWCAP_FMAF|HWCAP_IMA, 0 },
- { "sparcvis3", "v9b", v9, 0, 1, HWS_VB|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC, 0 },
- { "sparcvis3r", "v9b", v9, 0, 1, HWS_VB|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC|HWCAP_FJFMAU, 0 },
-
- { "sparc4", "v9v", v9, 0, 1, HWS_VV, 0 },
- { "sparc5", "v9m", v9, 0, 1, HWS_VM, HWS2_VM },
-
- { "leon", "leon", leon, 32, 1, HWS_V8, 0 },
- { "sparclet", "sparclet", sparclet, 32, 1, HWS_V8, 0 },
- { "sparclite", "sparclite", sparclite, 32, 1, HWS_V8, 0 },
- { "sparc86x", "sparclite", sparc86x, 32, 1, HWS_V8, 0 },
-
- { "v8plus", "v9", v9, 0, 1, HWCAP_V8PLUS|HWS_V9, 0 },
- { "v8plusa", "v9a", v9, 0, 1, HWCAP_V8PLUS|HWS_VA, 0 },
- { "v8plusb", "v9b", v9, 0, 1, HWCAP_V8PLUS|HWS_VB, 0 },
- { "v8plusc", "v9c", v9, 0, 1, HWCAP_V8PLUS|HWS_VC, 0 },
- { "v8plusd", "v9d", v9, 0, 1, HWCAP_V8PLUS|HWS_VD, 0 },
- { "v8pluse", "v9e", v9, 0, 1, HWCAP_V8PLUS|HWS_VE, 0 },
- { "v8plusv", "v9v", v9, 0, 1, HWCAP_V8PLUS|HWS_VV, 0 },
- { "v8plusm", "v9m", v9, 0, 1, HWCAP_V8PLUS|HWS_VM, 0 },
-
- { "v9", "v9", v9, 0, 1, HWS_V9, 0 },
- { "v9a", "v9a", v9, 0, 1, HWS_VA, 0 },
- { "v9b", "v9b", v9, 0, 1, HWS_VB, 0 },
- { "v9c", "v9c", v9, 0, 1, HWS_VC, 0 },
- { "v9d", "v9d", v9, 0, 1, HWS_VD, 0 },
- { "v9e", "v9e", v9, 0, 1, HWS_VE, 0 },
- { "v9v", "v9v", v9, 0, 1, HWS_VV, 0 },
- { "v9m", "v9m", v9, 0, 1, HWS_VM, HWS2_VM },
+ { "v8", "v8", v8, 32, 1, 0, 0 },
+ { "v8a", "v8", v8, 32, 1, 0, 0 },
+ { "sparc", "v9", v9, 0, 1, HWCAP_V8PLUS, 0 },
+ { "sparcvis", "v9a", v9, 0, 1, 0, 0 },
+ { "sparcvis2", "v9b", v9, 0, 1, 0, 0 },
+ { "sparcfmaf", "v9b", v9, 0, 1, HWCAP_FMAF, 0 },
+ { "sparcima", "v9b", v9, 0, 1, HWCAP_FMAF|HWCAP_IMA, 0 },
+ { "sparcvis3", "v9b", v9, 0, 1, HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC, 0 },
+ { "sparcvis3r", "v9b", v9, 0, 1, HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC|HWCAP_FJFMAU, 0 },
+
+ { "sparc4", "v9v", v9, 0, 1, 0, 0 },
+ { "sparc5", "v9m", v9, 0, 1, 0, 0 },
+
+ { "leon", "leon", leon, 32, 1, 0, 0 },
+ { "sparclet", "sparclet", sparclet, 32, 1, 0, 0 },
+ { "sparclite", "sparclite", sparclite, 32, 1, 0, 0 },
+ { "sparc86x", "sparclite", sparc86x, 32, 1, 0, 0 },
+
+ { "v8plus", "v9", v9, 0, 1, HWCAP_V8PLUS, 0 },
+ { "v8plusa", "v9a", v9, 0, 1, HWCAP_V8PLUS, 0 },
+ { "v8plusb", "v9b", v9, 0, 1, HWCAP_V8PLUS, 0 },
+ { "v8plusc", "v9c", v9, 0, 1, HWCAP_V8PLUS, 0 },
+ { "v8plusd", "v9d", v9, 0, 1, HWCAP_V8PLUS, 0 },
+ { "v8pluse", "v9e", v9, 0, 1, HWCAP_V8PLUS, 0 },
+ { "v8plusv", "v9v", v9, 0, 1, HWCAP_V8PLUS, 0 },
+ { "v8plusm", "v9m", v9, 0, 1, HWCAP_V8PLUS, 0 },
+
+ { "v9", "v9", v9, 0, 1, 0, 0 },
+ { "v9a", "v9a", v9, 0, 1, 0, 0 },
+ { "v9b", "v9b", v9, 0, 1, 0, 0 },
+ { "v9c", "v9c", v9, 0, 1, 0, 0 },
+ { "v9d", "v9d", v9, 0, 1, 0, 0 },
+ { "v9e", "v9e", v9, 0, 1, 0, 0 },
+ { "v9v", "v9v", v9, 0, 1, 0, 0 },
+ { "v9m", "v9m", v9, 0, 1, 0, 0 },
/* This exists to allow configure.tgt to pass one
value to specify both the default machine and default word size. */
- { "v9-64", "v9", v9, 64, 0, HWS_V9, 0 },
+ { "v9-64", "v9", v9, 64, 0, 0, 0 },
{ NULL, NULL, v8, 0, 0, 0, 0 }
};
@@ -551,8 +535,16 @@ md_parse_option (int c, const char *arg)
if (!architecture_requested
|| opcode_arch > max_architecture)
max_architecture = opcode_arch;
- hwcap_allowed
- |= (((bfd_uint64_t) sa->hwcap2_allowed) << 32) | sa->hwcap_allowed;
+
+ /* The allowed hardware capabilities are the implied by the
+ opcodes arch plus any extra capabilities defined in the GAS
+ arch. */
+ hwcap_allowed
+ = (hwcap_allowed
+ | (((bfd_uint64_t) sparc_opcode_archs[opcode_arch].hwcaps2) << 32)
+ | (((bfd_uint64_t) sa->hwcap2_allowed) << 32)
+ | sparc_opcode_archs[opcode_arch].hwcaps
+ | sa->hwcap_allowed);
architecture_requested = 1;
}
break;
@@ -3194,7 +3186,11 @@ sparc_ip (char *str, const struct sparc_opcode **pinsn)
warn_after_architecture = needed_architecture;
}
current_architecture = needed_architecture;
- hwcap_allowed |= hwcaps;
+ hwcap_allowed
+ = (hwcap_allowed
+ | hwcaps
+ | (((bfd_uint64_t) sparc_opcode_archs[current_architecture].hwcaps2) << 32)
+ | sparc_opcode_archs[current_architecture].hwcaps);
}
/* Conflict. */
/* ??? This seems to be a bit fragile. What if the next entry in
diff --git a/gas/testsuite/gas/sparc/hwcaps-bump.l b/gas/testsuite/gas/sparc/hwcaps-bump.l
new file mode 100644
index 0000000..b860745
--- /dev/null
+++ b/gas/testsuite/gas/sparc/hwcaps-bump.l
@@ -0,0 +1,2 @@
+.*hwcaps-bump.s: Assembler messages:
+.*hwcaps-bump.s:4: Warning: architecture bumped from "v6" to "v9m" on "wr"
diff --git a/gas/testsuite/gas/sparc/hwcaps-bump.s b/gas/testsuite/gas/sparc/hwcaps-bump.s
new file mode 100644
index 0000000..4b12b89
--- /dev/null
+++ b/gas/testsuite/gas/sparc/hwcaps-bump.s
@@ -0,0 +1,5 @@
+# Tests to check for the proper bumping of hardware capabilities
+# associated to opcode architectures.
+ .text
+ wr %g1, %g2, %mcdper
+ wr %g2, 0x3, %mwait
diff --git a/gas/testsuite/gas/sparc/sparc.exp b/gas/testsuite/gas/sparc/sparc.exp
index 580656f..1dc8125 100644
--- a/gas/testsuite/gas/sparc/sparc.exp
+++ b/gas/testsuite/gas/sparc/sparc.exp
@@ -90,6 +90,7 @@ if [istarget sparc*-*-*] {
run_dump_test "pcrel64"
run_dump_test "plt64"
run_dump_test "gotop64"
+ run_list_test "hwcaps-bump" "-bump"
}
run_dump_test "synth"
diff --git a/include/ChangeLog b/include/ChangeLog
index 3703f80..ce86557 100644
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,3 +1,8 @@
+2016-11-22 Jose E. Marchesi <jose.marchesi@oracle.com>
+
+ * opcode/sparc.h (sparc_opcode_arch): New fields hwcaps and
+ hwcaps2.
+
2016-11-22 Alan Modra <amodra@gmail.com>
PR 20744
diff --git a/include/opcode/sparc.h b/include/opcode/sparc.h
index 7e44408..6c66771 100644
--- a/include/opcode/sparc.h
+++ b/include/opcode/sparc.h
@@ -80,6 +80,10 @@ typedef struct sparc_opcode_arch
(SPARC_OPCODE_ARCH_MASK (..._V6) | SPARC_OPCODE_ARCH_MASK (..._V7)).
These are short's because sparc_opcode.architecture is. */
short supported;
+ /* Bitmaps describing the set of hardware capabilities implemented
+ by the opcode arch. */
+ int hwcaps;
+ int hwcaps2;
} sparc_opcode_arch;
extern const struct sparc_opcode_arch sparc_opcode_archs[];
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 9cd641a..834750f 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,19 @@
+2016-11-22 Jose E. Marchesi <jose.marchesi@oracle.com>
+
+ * sparc-opc.c (HWS_V8): Definition moved from
+ gas/config/tc-sparc.c.
+ (HWS_V9): Likewise.
+ (HWS_VA): Likewise.
+ (HWS_VB): Likewise.
+ (HWS_VC): Likewise.
+ (HWS_VD): Likewise.
+ (HWS_VE): Likewise.
+ (HWS_VV): Likewise.
+ (HWS_VM): Likewise.
+ (HWS2_VM): Likewise.
+ (sparc_opcode_archs): Initialize hwcaps and hwcaps2 fields of
+ existing entries.
+
2016-11-22 Claudiu Zissulescu <claziss@synopsys.com>
* arc-tbl.h: Reorder conditional flags with delay flags for 'b'
diff --git a/opcodes/sparc-opc.c b/opcodes/sparc-opc.c
index 04dd338..6b93618 100644
--- a/opcodes/sparc-opc.c
+++ b/opcodes/sparc-opc.c
@@ -92,40 +92,59 @@
otherwise. */
#define v9notv9a (MASK_V9)
+/* Hardware capability sets, used to keep sparc_opcode_archs easy to
+ read. */
+#define HWS_V8 HWCAP_MUL32 | HWCAP_DIV32 | HWCAP_FSMULD
+#define HWS_V9 HWS_V8 | HWCAP_POPC
+#define HWS_VA HWS_V9 | HWCAP_VIS
+#define HWS_VB HWS_VA | HWCAP_VIS2
+#define HWS_VC HWS_VB | HWCAP_ASI_BLK_INIT
+#define HWS_VD HWS_VC | HWCAP_FMAF | HWCAP_VIS3 | HWCAP_HPC
+#define HWS_VE HWS_VD \
+ | HWCAP_AES | HWCAP_DES | HWCAP_KASUMI | HWCAP_CAMELLIA \
+ | HWCAP_MD5 | HWCAP_SHA1 | HWCAP_SHA256 |HWCAP_SHA512 | HWCAP_MPMUL \
+ | HWCAP_MONT | HWCAP_CRC32C | HWCAP_CBCOND | HWCAP_PAUSE
+#define HWS_VV HWS_VE | HWCAP_FJFMAU | HWCAP_IMA
+#define HWS_VM HWS_VV
+
+#define HWS2_VM \
+ HWCAP2_VIS3B | HWCAP2_ADP | HWCAP2_SPARC5 | HWCAP2_MWAIT \
+ | HWCAP2_XMPMUL | HWCAP2_XMONT
+
/* Table of opcode architectures.
The order is defined in opcode/sparc.h. */
const struct sparc_opcode_arch sparc_opcode_archs[] =
{
- { "v6", MASK_V6 },
- { "v7", MASK_V6 | MASK_V7 },
- { "v8", MASK_V6 | MASK_V7 | MASK_V8 },
- { "leon", MASK_V6 | MASK_V7 | MASK_V8 | MASK_LEON },
- { "sparclet", MASK_V6 | MASK_V7 | MASK_V8 | MASK_SPARCLET },
- { "sparclite", MASK_V6 | MASK_V7 | MASK_V8 | MASK_SPARCLITE },
+ { "v6", MASK_V6, 0, 0 },
+ { "v7", MASK_V6 | MASK_V7, 0, 0 },
+ { "v8", MASK_V6 | MASK_V7 | MASK_V8, HWS_V8, 0 },
+ { "leon", MASK_V6 | MASK_V7 | MASK_V8 | MASK_LEON, HWS_V8, 0 },
+ { "sparclet", MASK_V6 | MASK_V7 | MASK_V8 | MASK_SPARCLET, HWS_V8, 0 },
+ { "sparclite", MASK_V6 | MASK_V7 | MASK_V8 | MASK_SPARCLITE, HWS_V8, 0 },
/* ??? Don't some v8 priviledged insns conflict with v9? */
- { "v9", MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 },
+ { "v9", MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9, HWS_V9, 0 },
/* v9 with ultrasparc additions */
- { "v9a", MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 | MASK_V9A },
+ { "v9a", MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 | MASK_V9A, HWS_VA, 0 },
/* v9 with cheetah additions */
- { "v9b", MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 | MASK_V9A | MASK_V9B },
+ { "v9b", MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 | MASK_V9A | MASK_V9B, HWS_VB, 0 },
/* v9 with UA2005 and T1 additions. */
{ "v9c", (MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 | MASK_V9A | MASK_V9B
- | MASK_V9C) },
+ | MASK_V9C), HWS_VC, 0 },
/* v9 with UA2007 and T3 additions. */
{ "v9d", (MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 | MASK_V9A | MASK_V9B
- | MASK_V9C | MASK_V9D) },
+ | MASK_V9C | MASK_V9D), HWS_VD, 0 },
/* v9 with OSA2011 and T4 additions modulus integer multiply-add. */
{ "v9e", (MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 | MASK_V9A | MASK_V9B
- | MASK_V9C | MASK_V9D | MASK_V9E) },
+ | MASK_V9C | MASK_V9D | MASK_V9E), HWS_VE, 0 },
/* V9 with OSA2011 and T4 additions, integer multiply and Fujitsu fp
multiply-add. */
{ "v9v", (MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 | MASK_V9A | MASK_V9B
- | MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V) },
+ | MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V), HWS_VV, 0 },
/* v9 with OSA2015 and M7 additions. */
{ "v9m", (MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 | MASK_V9A | MASK_V9B
- | MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M) },
- { NULL, 0 }
+ | MASK_V9C | MASK_V9D | MASK_V9E | MASK_V9V | MASK_V9M), HWS_VM, HWS2_VM },
+ { NULL, 0, 0, 0 }
};
/* Given NAME, return it's architecture entry. */
generated by cgit v1.1 at 2024-11-07 02:57:26 +0000