diff options
| -rw-r--r-- | sim/aarch64/ChangeLog | 4 | ||||
| -rw-r--r-- | sim/aarch64/cpustate.c | 4 |
2 files changed, 6 insertions, 2 deletions
diff --git a/sim/aarch64/ChangeLog b/sim/aarch64/ChangeLog index f11eaad..e8f8b48 100644 --- a/sim/aarch64/ChangeLog +++ b/sim/aarch64/ChangeLog @@ -4,6 +4,10 @@ Print hex equivalents of floats and doubles. Check element number against array size when accessing vector registers. + (GET_VEC_ELEMENT): Fix off by one error checking for an invalid + element index. + (SET_VEC_ELEMENT): Likewise. + * memory.c: Trace memory reads when --trace-memory is enabled. Remove float and double load and store functions. * memory.h (aarch64_get_mem_float): Delete prototype. diff --git a/sim/aarch64/cpustate.c b/sim/aarch64/cpustate.c index 86b1b15..19f485e 100644 --- a/sim/aarch64/cpustate.c +++ b/sim/aarch64/cpustate.c @@ -345,7 +345,7 @@ aarch64_set_FP_long_double (sim_cpu *cpu, VReg reg, FRegister a) #define GET_VEC_ELEMENT(REG, ELEMENT, FIELD) \ do \ { \ - if (element > ARRAY_SIZE (cpu->fr[0].FIELD)) \ + if (element >= ARRAY_SIZE (cpu->fr[0].FIELD)) \ { \ TRACE_REGISTER (cpu, \ "Internal SIM error: invalid element number: %d ",\ @@ -421,7 +421,7 @@ aarch64_get_vec_double (sim_cpu *cpu, VReg reg, unsigned element) #define SET_VEC_ELEMENT(REG, ELEMENT, VAL, FIELD, PRINTER) \ do \ { \ - if (ELEMENT > ARRAY_SIZE (cpu->fr[0].FIELD)) \ + if (ELEMENT >= ARRAY_SIZE (cpu->fr[0].FIELD)) \ { \ TRACE_REGISTER (cpu, \ "Internal SIM error: invalid element number: %d ",\ |