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-rw-r--r--sim/mips/ChangeLog5
-rw-r--r--sim/mips/mips.igen12
2 files changed, 11 insertions, 6 deletions
diff --git a/sim/mips/ChangeLog b/sim/mips/ChangeLog
index 93d77ba..ce00570 100644
--- a/sim/mips/ChangeLog
+++ b/sim/mips/ChangeLog
@@ -1,3 +1,8 @@
+Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
+
+ * mips.igen (SWC1) : Correct the handling of ReverseEndian
+ and BigEndianCPU.
+
Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
* configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
diff --git a/sim/mips/mips.igen b/sim/mips/mips.igen
index 48c6216..10ed6b8 100644
--- a/sim/mips/mips.igen
+++ b/sim/mips/mips.igen
@@ -5213,14 +5213,14 @@
{
uword64 memval = 0;
uword64 memval1 = 0;
- uword64 mask = 0x7;
+ uword64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
+ address_word reverseendian = (ReverseEndian ?(mask ^ AccessLength_WORD): 0);
+ address_word bigendiancpu = (BigEndianCPU ?(mask ^ AccessLength_WORD): 0);
unsigned int byte;
- paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
- byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
+ paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
+ byte = ((vaddr & mask) ^ bigendiancpu);
memval = (((uword64)COP_SW(((instruction >> 26) & 0x3),destreg)) << (8 * byte));
- {
- StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
- }
+ StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
}
}
}