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-rw-r--r--bfd/ChangeLog5
-rw-r--r--bfd/elf64-ppc.c89
-rw-r--r--ld/testsuite/ChangeLog9
-rw-r--r--ld/testsuite/ld-powerpc/tlsexe.d27
-rw-r--r--ld/testsuite/ld-powerpc/tlsexe.r2
-rw-r--r--ld/testsuite/ld-powerpc/tlsexetoc.d27
-rw-r--r--ld/testsuite/ld-powerpc/tlsexetoc.r2
-rw-r--r--ld/testsuite/ld-powerpc/tlsso.d27
-rw-r--r--ld/testsuite/ld-powerpc/tlstocso.d27
9 files changed, 111 insertions, 104 deletions
diff --git a/bfd/ChangeLog b/bfd/ChangeLog
index ca26d60..affb063 100644
--- a/bfd/ChangeLog
+++ b/bfd/ChangeLog
@@ -1,5 +1,10 @@
2006-08-17 Alan Modra <amodra@bigpond.net.au>
+ * elf64-ppc.c (create_linkage_sections): Align .glink to 8 bytes.
+ (ppc64_elf_build_stubs): Use new lazy linking stub.
+
+2006-08-17 Alan Modra <amodra@bigpond.net.au>
+
* elf64-ppc.c (ppc64_elf_size_stubs): Ignore non-code sections.
2006-08-16 H.J. Lu <hongjiu.lu@intel.com>
diff --git a/bfd/elf64-ppc.c b/bfd/elf64-ppc.c
index 67e2713..de2dd79 100644
--- a/bfd/elf64-ppc.c
+++ b/bfd/elf64-ppc.c
@@ -135,30 +135,29 @@ static bfd_vma opd_entry_value
#define BCTR 0x4e800420 /* bctr */
+#define ADDIS_R12_R12 0x3d8c0000 /* addis %r12,%r12,off@ha */
#define ADDIS_R2_R2 0x3c420000 /* addis %r2,%r2,off@ha */
#define ADDI_R2_R2 0x38420000 /* addi %r2,%r2,off@l */
#define LD_R2_40R1 0xe8410028 /* ld %r2,40(%r1) */
-/* glink call stub instructions. We enter with the index in R0, and the
- address of glink entry in CTR. From that, we can calculate PLT0. */
+/* glink call stub instructions. We enter with the index in R0. */
#define GLINK_CALL_STUB_SIZE (16*4)
-#define MFCTR_R12 0x7d8902a6 /* mfctr %r12 */
-#define SLDI_R11_R0_3 0x780b1f24 /* sldi %r11,%r0,3 */
-#define ADDIC_R2_R0_32K 0x34408000 /* addic. %r2,%r0,-32768 */
-#define SUB_R12_R12_R11 0x7d8b6050 /* sub %r12,%r12,%r11 */
-#define SRADI_R2_R2_63 0x7c42fe76 /* sradi %r2,%r2,63 */
-#define SLDI_R11_R0_2 0x780b1764 /* sldi %r11,%r0,2 */
-#define AND_R2_R2_R11 0x7c425838 /* and %r2,%r2,%r11 */
- /* sub %r12,%r12,%r11 */
-#define ADD_R12_R12_R2 0x7d8c1214 /* add %r12,%r12,%r2 */
-#define ADDIS_R12_R12 0x3d8c0000 /* addis %r12,%r12,xxx@ha */
- /* ld %r11,xxx@l(%r12) */
-#define ADDI_R12_R12 0x398c0000 /* addi %r12,%r12,xxx@l */
- /* ld %r2,8(%r12) */
- /* mtctr %r11 */
- /* ld %r11,16(%r12) */
- /* bctr */
+ /* 0: */
+ /* .quad plt0-1f */
+ /* __glink: */
+#define MFLR_R12 0x7d8802a6 /* mflr %12 */
+#define BCL_20_31 0x429f0005 /* bcl 20,31,1f */
+ /* 1: */
+#define MFLR_R11 0x7d6802a6 /* mflr %11 */
+#define LD_R2_M16R11 0xe84bfff0 /* ld %2,(0b-1b)(%11) */
+#define MTLR_R12 0x7d8803a6 /* mtlr %12 */
+#define ADD_R12_R2_R11 0x7d825a14 /* add %12,%2,%11 */
+ /* ld %11,0(%12) */
+ /* ld %2,8(%12) */
+ /* mtctr %11 */
+ /* ld %11,16(%12) */
+ /* bctr */
/* Pad with this. */
#define NOP 0x60000000
@@ -3728,7 +3727,7 @@ create_linkage_sections (bfd *dynobj, struct bfd_link_info *info)
htab->glink = bfd_make_section_anyway_with_flags (dynobj, ".glink",
flags);
if (htab->glink == NULL
- || ! bfd_set_section_alignment (dynobj, htab->glink, 2))
+ || ! bfd_set_section_alignment (dynobj, htab->glink, 3))
return FALSE;
/* Create branch lookup table for plt_branch stubs. */
@@ -9458,18 +9457,6 @@ ppc64_elf_build_stubs (bfd_boolean emit_stub_syms,
bfd_vma plt0;
/* Build the .glink plt call stub. */
- plt0 = (htab->plt->output_section->vma
- + htab->plt->output_offset
- - (htab->glink->output_section->vma
- + htab->glink->output_offset
- + GLINK_CALL_STUB_SIZE));
- if (plt0 + 0x80008000 > 0xffffffff)
- {
- (*_bfd_error_handler) (_(".glink and .plt too far apart"));
- bfd_set_error (bfd_error_bad_value);
- return FALSE;
- }
-
if (htab->emit_stub_syms)
{
struct elf_link_hash_entry *h;
@@ -9480,7 +9467,7 @@ ppc64_elf_build_stubs (bfd_boolean emit_stub_syms,
{
h->root.type = bfd_link_hash_defined;
h->root.u.def.section = htab->glink;
- h->root.u.def.value = 0;
+ h->root.u.def.value = 8;
h->ref_regular = 1;
h->def_regular = 1;
h->ref_regular_nonweak = 1;
@@ -9489,29 +9476,26 @@ ppc64_elf_build_stubs (bfd_boolean emit_stub_syms,
}
}
p = htab->glink->contents;
- bfd_put_32 (htab->glink->owner, MFCTR_R12, p);
- p += 4;
- bfd_put_32 (htab->glink->owner, SLDI_R11_R0_3, p);
- p += 4;
- bfd_put_32 (htab->glink->owner, ADDIC_R2_R0_32K, p);
- p += 4;
- bfd_put_32 (htab->glink->owner, SUB_R12_R12_R11, p);
- p += 4;
- bfd_put_32 (htab->glink->owner, SRADI_R2_R2_63, p);
- p += 4;
- bfd_put_32 (htab->glink->owner, SLDI_R11_R0_2, p);
+ plt0 = (htab->plt->output_section->vma
+ + htab->plt->output_offset
+ - (htab->glink->output_section->vma
+ + htab->glink->output_offset
+ + 16));
+ bfd_put_64 (htab->glink->owner, plt0, p);
+ p += 8;
+ bfd_put_32 (htab->glink->owner, MFLR_R12, p);
p += 4;
- bfd_put_32 (htab->glink->owner, AND_R2_R2_R11, p);
+ bfd_put_32 (htab->glink->owner, BCL_20_31, p);
p += 4;
- bfd_put_32 (htab->glink->owner, SUB_R12_R12_R11, p);
+ bfd_put_32 (htab->glink->owner, MFLR_R11, p);
p += 4;
- bfd_put_32 (htab->glink->owner, ADD_R12_R12_R2, p);
+ bfd_put_32 (htab->glink->owner, LD_R2_M16R11, p);
p += 4;
- bfd_put_32 (htab->glink->owner, ADDIS_R12_R12 | PPC_HA (plt0), p);
+ bfd_put_32 (htab->glink->owner, MTLR_R12, p);
p += 4;
- bfd_put_32 (htab->glink->owner, LD_R11_0R12 | PPC_LO (plt0), p);
+ bfd_put_32 (htab->glink->owner, ADD_R12_R2_R11, p);
p += 4;
- bfd_put_32 (htab->glink->owner, ADDI_R12_R12 | PPC_LO (plt0), p);
+ bfd_put_32 (htab->glink->owner, LD_R11_0R12, p);
p += 4;
bfd_put_32 (htab->glink->owner, LD_R2_0R12 | 8, p);
p += 4;
@@ -9521,6 +9505,11 @@ ppc64_elf_build_stubs (bfd_boolean emit_stub_syms,
p += 4;
bfd_put_32 (htab->glink->owner, BCTR, p);
p += 4;
+ while (p - htab->glink->contents < GLINK_CALL_STUB_SIZE)
+ {
+ bfd_put_32 (htab->glink->owner, NOP, p);
+ p += 4;
+ }
/* Build the .glink lazy link call stubs. */
indx = 0;
@@ -9539,7 +9528,7 @@ ppc64_elf_build_stubs (bfd_boolean emit_stub_syms,
p += 4;
}
bfd_put_32 (htab->glink->owner,
- B_DOT | ((htab->glink->contents - p) & 0x3fffffc), p);
+ B_DOT | ((htab->glink->contents - p + 8) & 0x3fffffc), p);
indx++;
p += 4;
}
diff --git a/ld/testsuite/ChangeLog b/ld/testsuite/ChangeLog
index 3e25f61..fae1e90 100644
--- a/ld/testsuite/ChangeLog
+++ b/ld/testsuite/ChangeLog
@@ -1,3 +1,12 @@
+2006-08-17 Alan Modra <amodra@bigpond.net.au>
+
+ * ld-powerpc/tlsexe.d: Update for lazy link stub change.
+ * ld-powerpc/tlsexe.r: Likewise.
+ * ld-powerpc/tlsexetoc.d: Likewise.
+ * ld-powerpc/tlsexetoc.r: Likewise.
+ * ld-powerpc/tlsso.d: Likewise.
+ * ld-powerpc/tlstocso.d: Likewise.
+
2006-08-16 H.J. Lu <hongjiu.lu@intel.com>
PR ld/3015
diff --git a/ld/testsuite/ld-powerpc/tlsexe.d b/ld/testsuite/ld-powerpc/tlsexe.d
index 546daf3..26599ac 100644
--- a/ld/testsuite/ld-powerpc/tlsexe.d
+++ b/ld/testsuite/ld-powerpc/tlsexe.d
@@ -56,21 +56,22 @@ Disassembly of section \.text:
.* e9 4d 90 2a lwa r10,-28632\(r13\)
.* 3d 2d 00 00 addis r9,r13,0
.* a9 49 90 30 lha r10,-28624\(r9\)
-.* 7d 89 02 a6 mfctr r12
-.* 78 0b 1f 24 rldicr r11,r0,3,60
-.* 34 40 80 00 addic\. r2,r0,-32768
-.* 7d 8b 60 50 subf r12,r11,r12
-.* 7c 42 fe 76 sradi r2,r2,63
-.* 78 0b 17 64 rldicr r11,r0,2,61
-.* 7c 42 58 38 and r2,r2,r11
-.* 7d 8b 60 50 subf r12,r11,r12
-.* 7d 8c 12 14 add r12,r12,r2
-.* 3d 8c 00 01 addis r12,r12,1
-.* e9 6c 01 c4 ld r11,452\(r12\)
-.* 39 8c 01 c4 addi r12,r12,452
+.* 60 00 00 00 nop
+.* 00 00 00 00 .*
+.* 00 01 01 f0 .*
+.* 7d 88 02 a6 mflr r12
+.* 42 9f 00 05 bcl- 20,4\*cr7\+so,.*
+.* 7d 68 02 a6 mflr r11
+.* e8 4b ff f0 ld r2,-16\(r11\)
+.* 7d 88 03 a6 mtlr r12
+.* 7d 82 5a 14 add r12,r2,r11
+.* e9 6c 00 00 ld r11,0\(r12\)
.* e8 4c 00 08 ld r2,8\(r12\)
.* 7d 69 03 a6 mtctr r11
.* e9 6c 00 10 ld r11,16\(r12\)
.* 4e 80 04 20 bctr
+.* 60 00 00 00 nop
+.* 60 00 00 00 nop
+.* 60 00 00 00 nop
.* 38 00 00 00 li r0,0
-.* 4b ff ff bc b .*
+.* 4b ff ff c4 b .*
diff --git a/ld/testsuite/ld-powerpc/tlsexe.r b/ld/testsuite/ld-powerpc/tlsexe.r
index ed5185a..1cf4cef 100644
--- a/ld/testsuite/ld-powerpc/tlsexe.r
+++ b/ld/testsuite/ld-powerpc/tlsexe.r
@@ -16,7 +16,7 @@ Section Headers:
+\[ 4\] \.dynstr +.*
+\[ 5\] \.rela\.dyn +.*
+\[ 6\] \.rela\.plt +.*
- +\[ 7\] \.text +PROGBITS .* 0+fc 0+ +AX +0 +0 +4
+ +\[ 7\] \.text +PROGBITS .* 0+100 0+ +AX +0 +0 +8
+\[ 8\] \.rodata + PROGBITS .* 0+ 0+ +A +0 +0 +8
+\[ 9\] \.tdata +PROGBITS .* 0+38 0+ WAT +0 +0 +8
+\[10\] \.tbss +NOBITS .* 0+38 0+ WAT +0 +0 +8
diff --git a/ld/testsuite/ld-powerpc/tlsexetoc.d b/ld/testsuite/ld-powerpc/tlsexetoc.d
index 7ec07d2..c1cb190 100644
--- a/ld/testsuite/ld-powerpc/tlsexetoc.d
+++ b/ld/testsuite/ld-powerpc/tlsexetoc.d
@@ -40,21 +40,22 @@ Disassembly of section \.text:
.* 89 4d 90 60 lbz r10,-28576\(r13\)
.* 3d 2d 00 00 addis r9,r13,0
.* 99 49 90 68 stb r10,-28568\(r9\)
-.* 7d 89 02 a6 mfctr r12
-.* 78 0b 1f 24 rldicr r11,r0,3,60
-.* 34 40 80 00 addic\. r2,r0,-32768
-.* 7d 8b 60 50 subf r12,r11,r12
-.* 7c 42 fe 76 sradi r2,r2,63
-.* 78 0b 17 64 rldicr r11,r0,2,61
-.* 7c 42 58 38 and r2,r2,r11
-.* 7d 8b 60 50 subf r12,r11,r12
-.* 7d 8c 12 14 add r12,r12,r2
-.* 3d 8c 00 01 addis r12,r12,1
-.* e9 6c 01 ec ld r11,492\(r12\)
-.* 39 8c 01 ec addi r12,r12,492
+.* 60 00 00 00 nop
+.* 00 00 00 00 .*
+.* 00 01 02 18 .*
+.* 7d 88 02 a6 mflr r12
+.* 42 9f 00 05 bcl- 20,4\*cr7\+so,.*
+.* 7d 68 02 a6 mflr r11
+.* e8 4b ff f0 ld r2,-16\(r11\)
+.* 7d 88 03 a6 mtlr r12
+.* 7d 82 5a 14 add r12,r2,r11
+.* e9 6c 00 00 ld r11,0\(r12\)
.* e8 4c 00 08 ld r2,8\(r12\)
.* 7d 69 03 a6 mtctr r11
.* e9 6c 00 10 ld r11,16\(r12\)
.* 4e 80 04 20 bctr
+.* 60 00 00 00 nop
+.* 60 00 00 00 nop
+.* 60 00 00 00 nop
.* 38 00 00 00 li r0,0
-.* 4b ff ff bc b .*
+.* 4b ff ff c4 b .*
diff --git a/ld/testsuite/ld-powerpc/tlsexetoc.r b/ld/testsuite/ld-powerpc/tlsexetoc.r
index d57d7f2..40fe383 100644
--- a/ld/testsuite/ld-powerpc/tlsexetoc.r
+++ b/ld/testsuite/ld-powerpc/tlsexetoc.r
@@ -16,7 +16,7 @@ Section Headers:
+\[ 4\] \.dynstr +.*
+\[ 5\] \.rela\.dyn +.*
+\[ 6\] \.rela\.plt +.*
- +\[ 7\] \.text +PROGBITS .* 0+bc 0+ +AX +0 +0 +4
+ +\[ 7\] \.text +PROGBITS .* 0+c0 0+ +AX +0 +0 +8
+\[ 8\] \.rodata +PROGBITS .* 0+ 0+ +A +0 +0 +8
+\[ 9\] \.tdata +PROGBITS .* 0+38 0+ WAT +0 +0 +8
+\[10\] \.tbss +NOBITS .* 0+38 0+ WAT +0 +0 +8
diff --git a/ld/testsuite/ld-powerpc/tlsso.d b/ld/testsuite/ld-powerpc/tlsso.d
index dc4ae18..0dbc849 100644
--- a/ld/testsuite/ld-powerpc/tlsso.d
+++ b/ld/testsuite/ld-powerpc/tlsso.d
@@ -56,21 +56,22 @@ Disassembly of section \.text:
.* e9 4d 00 02 lwa r10,0\(r13\)
.* 3d 2d 00 00 addis r9,r13,0
.* a9 49 00 00 lha r10,0\(r9\)
-.* 7d 89 02 a6 mfctr r12
-.* 78 0b 1f 24 rldicr r11,r0,3,60
-.* 34 40 80 00 addic\. r2,r0,-32768
-.* 7d 8b 60 50 subf r12,r11,r12
-.* 7c 42 fe 76 sradi r2,r2,63
-.* 78 0b 17 64 rldicr r11,r0,2,61
-.* 7c 42 58 38 and r2,r2,r11
-.* 7d 8b 60 50 subf r12,r11,r12
-.* 7d 8c 12 14 add r12,r12,r2
-.* 3d 8c 00 01 addis r12,r12,1
-.* e9 6c 01 f4 ld r11,500\(r12\)
-.* 39 8c 01 f4 addi r12,r12,500
+.* 60 00 00 00 nop
+.* 00 00 00 00 .*
+.* 00 01 02 20 .*
+.* 7d 88 02 a6 mflr r12
+.* 42 9f 00 05 bcl- 20,4\*cr7\+so,.*
+.* 7d 68 02 a6 mflr r11
+.* e8 4b ff f0 ld r2,-16\(r11\)
+.* 7d 88 03 a6 mtlr r12
+.* 7d 82 5a 14 add r12,r2,r11
+.* e9 6c 00 00 ld r11,0\(r12\)
.* e8 4c 00 08 ld r2,8\(r12\)
.* 7d 69 03 a6 mtctr r11
.* e9 6c 00 10 ld r11,16\(r12\)
.* 4e 80 04 20 bctr
+.* 60 00 00 00 nop
+.* 60 00 00 00 nop
+.* 60 00 00 00 nop
.* 38 00 00 00 li r0,0
-.* 4b ff ff bc b .*
+.* 4b ff ff c4 b .*
diff --git a/ld/testsuite/ld-powerpc/tlstocso.d b/ld/testsuite/ld-powerpc/tlstocso.d
index 0534b3b..073e85d 100644
--- a/ld/testsuite/ld-powerpc/tlstocso.d
+++ b/ld/testsuite/ld-powerpc/tlstocso.d
@@ -40,21 +40,22 @@ Disassembly of section \.text:
.* 89 4d 00 00 lbz r10,0\(r13\)
.* 3d 2d 00 00 addis r9,r13,0
.* 99 49 00 00 stb r10,0\(r9\)
-.* 7d 89 02 a6 mfctr r12
-.* 78 0b 1f 24 rldicr r11,r0,3,60
-.* 34 40 80 00 addic\. r2,r0,-32768
-.* 7d 8b 60 50 subf r12,r11,r12
-.* 7c 42 fe 76 sradi r2,r2,63
-.* 78 0b 17 64 rldicr r11,r0,2,61
-.* 7c 42 58 38 and r2,r2,r11
-.* 7d 8b 60 50 subf r12,r11,r12
-.* 7d 8c 12 14 add r12,r12,r2
-.* 3d 8c 00 01 addis r12,r12,1
-.* e9 6c 01 ec ld r11,492\(r12\)
-.* 39 8c 01 ec addi r12,r12,492
+.* 60 00 00 00 nop
+.* 00 00 00 00 .*
+.* 00 01 02 18 .*
+.* 7d 88 02 a6 mflr r12
+.* 42 9f 00 05 bcl- 20,4\*cr7\+so,.*
+.* 7d 68 02 a6 mflr r11
+.* e8 4b ff f0 ld r2,-16\(r11\)
+.* 7d 88 03 a6 mtlr r12
+.* 7d 82 5a 14 add r12,r2,r11
+.* e9 6c 00 00 ld r11,0\(r12\)
.* e8 4c 00 08 ld r2,8\(r12\)
.* 7d 69 03 a6 mtctr r11
.* e9 6c 00 10 ld r11,16\(r12\)
.* 4e 80 04 20 bctr
+.* 60 00 00 00 nop
+.* 60 00 00 00 nop
+.* 60 00 00 00 nop
.* 38 00 00 00 li r0,0
-.* 4b ff ff bc b .*
+.* 4b ff ff c4 b .*
generated by cgit v1.1 at 2024-08-31 05:30:32 +0000