diff options
37 files changed, 123 insertions, 115 deletions
diff --git a/include/sim/sim.h b/include/sim/sim.h index 4afdf01..5569481 100644 --- a/include/sim/sim.h +++ b/include/sim/sim.h @@ -189,7 +189,7 @@ int sim_write (SIM_DESC sd, SIM_ADDR mem, const void *buf, int length); If LENGTH does not match the size of REGNO no data is transfered (the actual register size is still returned). */ -int sim_fetch_register (SIM_DESC sd, int regno, unsigned char *buf, int length); +int sim_fetch_register (SIM_DESC sd, int regno, void *buf, int length); /* Store register REGNO from the raw (target endian) value in BUF. @@ -203,8 +203,7 @@ int sim_fetch_register (SIM_DESC sd, int regno, unsigned char *buf, int length); Return a LENGTH of 0 to indicate the register was not updated but no error has occurred. */ -int sim_store_register (SIM_DESC sd, int regno, const unsigned char *buf, - int length); +int sim_store_register (SIM_DESC sd, int regno, const void *buf, int length); /* Print whatever statistics the simulator has collected. diff --git a/sim/aarch64/interp.c b/sim/aarch64/interp.c index 34a4c72..eb8d055 100644 --- a/sim/aarch64/interp.c +++ b/sim/aarch64/interp.c @@ -210,7 +210,7 @@ reg_size (int regno) } static int -aarch64_reg_get (SIM_CPU *cpu, int regno, unsigned char *buf, int length) +aarch64_reg_get (SIM_CPU *cpu, int regno, void *buf, int length) { size_t size; bfd_vma val; @@ -257,7 +257,7 @@ aarch64_reg_get (SIM_CPU *cpu, int regno, unsigned char *buf, int length) } static int -aarch64_reg_set (SIM_CPU *cpu, int regno, const unsigned char *buf, int length) +aarch64_reg_set (SIM_CPU *cpu, int regno, const void *buf, int length) { size_t size; bfd_vma val; diff --git a/sim/arm/wrapper.c b/sim/arm/wrapper.c index 455f320..831a0ff 100644 --- a/sim/arm/wrapper.c +++ b/sim/arm/wrapper.c @@ -429,7 +429,7 @@ tomem (struct ARMul_State *state, } static int -arm_reg_store (SIM_CPU *cpu, int rn, const unsigned char *memory, int length) +arm_reg_store (SIM_CPU *cpu, int rn, const void *buf, int length) { init (); @@ -460,11 +460,11 @@ arm_reg_store (SIM_CPU *cpu, int rn, const unsigned char *memory, int length) case SIM_ARM_FP6_REGNUM: case SIM_ARM_FP7_REGNUM: case SIM_ARM_FPS_REGNUM: - ARMul_SetReg (state, state->Mode, rn, frommem (state, memory)); + ARMul_SetReg (state, state->Mode, rn, frommem (state, buf)); break; case SIM_ARM_PS_REGNUM: - state->Cpsr = frommem (state, memory); + state->Cpsr = frommem (state, buf); ARMul_CPSRAltered (state); break; @@ -485,11 +485,11 @@ arm_reg_store (SIM_CPU *cpu, int rn, const unsigned char *memory, int length) case SIM_ARM_MAVERIC_COP0R14_REGNUM: case SIM_ARM_MAVERIC_COP0R15_REGNUM: memcpy (& DSPregs [rn - SIM_ARM_MAVERIC_COP0R0_REGNUM], - memory, sizeof (struct maverick_regs)); + buf, sizeof (struct maverick_regs)); return sizeof (struct maverick_regs); case SIM_ARM_MAVERIC_DSPSC_REGNUM: - memcpy (&DSPsc, memory, sizeof DSPsc); + memcpy (&DSPsc, buf, sizeof DSPsc); return sizeof DSPsc; case SIM_ARM_IWMMXT_COP0R0_REGNUM: @@ -524,7 +524,7 @@ arm_reg_store (SIM_CPU *cpu, int rn, const unsigned char *memory, int length) case SIM_ARM_IWMMXT_COP1R13_REGNUM: case SIM_ARM_IWMMXT_COP1R14_REGNUM: case SIM_ARM_IWMMXT_COP1R15_REGNUM: - return Store_Iwmmxt_Register (rn - SIM_ARM_IWMMXT_COP0R0_REGNUM, memory); + return Store_Iwmmxt_Register (rn - SIM_ARM_IWMMXT_COP0R0_REGNUM, buf); default: return 0; @@ -534,8 +534,9 @@ arm_reg_store (SIM_CPU *cpu, int rn, const unsigned char *memory, int length) } static int -arm_reg_fetch (SIM_CPU *cpu, int rn, unsigned char *memory, int length) +arm_reg_fetch (SIM_CPU *cpu, int rn, void *buf, int length) { + unsigned char *memory = buf; ARMword regval; int len = length; diff --git a/sim/avr/interp.c b/sim/avr/interp.c index 0aa7132..9be19a1 100644 --- a/sim/avr/interp.c +++ b/sim/avr/interp.c @@ -1600,8 +1600,10 @@ sim_read (SIM_DESC sd, SIM_ADDR addr, void *buffer, int size) } static int -avr_reg_store (SIM_CPU *cpu, int rn, const unsigned char *memory, int length) +avr_reg_store (SIM_CPU *cpu, int rn, const void *buf, int length) { + const unsigned char *memory = buf; + if (rn < 32 && length == 1) { sram[rn] = *memory; @@ -1629,8 +1631,10 @@ avr_reg_store (SIM_CPU *cpu, int rn, const unsigned char *memory, int length) } static int -avr_reg_fetch (SIM_CPU *cpu, int rn, unsigned char *memory, int length) +avr_reg_fetch (SIM_CPU *cpu, int rn, void *buf, int length) { + unsigned char *memory = buf; + if (rn < 32 && length == 1) { *memory = sram[rn]; diff --git a/sim/bfin/machs.c b/sim/bfin/machs.c index 035eb31..bbc3b51 100644 --- a/sim/bfin/machs.c +++ b/sim/bfin/machs.c @@ -1850,7 +1850,7 @@ bfin_get_reg (SIM_CPU *cpu, int rn) } static int -bfin_reg_fetch (SIM_CPU *cpu, int rn, unsigned char *buf, int len) +bfin_reg_fetch (SIM_CPU *cpu, int rn, void *buf, int len) { bu32 value, *reg; @@ -1881,7 +1881,7 @@ bfin_reg_fetch (SIM_CPU *cpu, int rn, unsigned char *buf, int len) } static int -bfin_reg_store (SIM_CPU *cpu, int rn, const unsigned char *buf, int len) +bfin_reg_store (SIM_CPU *cpu, int rn, const void *buf, int len) { bu32 value, *reg; diff --git a/sim/bpf/bpf.c b/sim/bpf/bpf.c index 9db61ff..c3ba0e0 100644 --- a/sim/bpf/bpf.c +++ b/sim/bpf/bpf.c @@ -45,7 +45,7 @@ IDESC *bpf_idesc_be; int bpfbf_fetch_register (SIM_CPU *current_cpu, int rn, - unsigned char *buf, + void *buf, int len) { if (rn == 11) @@ -61,7 +61,7 @@ bpfbf_fetch_register (SIM_CPU *current_cpu, int bpfbf_store_register (SIM_CPU *current_cpu, int rn, - const unsigned char *buf, + const void *buf, int len) { if (rn == 11) diff --git a/sim/common/sim-cpu.h b/sim/common/sim-cpu.h index 2ad5667..4f5972b 100644 --- a/sim/common/sim-cpu.h +++ b/sim/common/sim-cpu.h @@ -30,8 +30,8 @@ typedef const char * (CPU_INSN_NAME_FN) (sim_cpu *, int); /* Types for register access functions. These routines implement the sim_{fetch,store}_register interface. */ -typedef int (CPUREG_FETCH_FN) (sim_cpu *, int, unsigned char *, int); -typedef int (CPUREG_STORE_FN) (sim_cpu *, int, const unsigned char *, int); +typedef int (CPUREG_FETCH_FN) (sim_cpu *, int, void *, int); +typedef int (CPUREG_STORE_FN) (sim_cpu *, int, const void *, int); /* Types for PC access functions. Some simulators require a functional interface to access the program diff --git a/sim/common/sim-reg.c b/sim/common/sim-reg.c index 54ce562..ca242de 100644 --- a/sim/common/sim-reg.c +++ b/sim/common/sim-reg.c @@ -30,7 +30,7 @@ along with this program. If not, see <http://www.gnu.org/licenses/>. */ cpus. */ int -sim_fetch_register (SIM_DESC sd, int rn, unsigned char *buf, int length) +sim_fetch_register (SIM_DESC sd, int rn, void *buf, int length) { SIM_CPU *cpu = STATE_CPU (sd, 0); @@ -45,7 +45,7 @@ sim_fetch_register (SIM_DESC sd, int rn, unsigned char *buf, int length) cpus. */ int -sim_store_register (SIM_DESC sd, int rn, const unsigned char *buf, int length) +sim_store_register (SIM_DESC sd, int rn, const void *buf, int length) { SIM_CPU *cpu = STATE_CPU (sd, 0); diff --git a/sim/cr16/interp.c b/sim/cr16/interp.c index 6e27fad..cfe157c 100644 --- a/sim/cr16/interp.c +++ b/sim/cr16/interp.c @@ -385,8 +385,8 @@ free_state (SIM_DESC sd) sim_state_free (sd); } -static int cr16_reg_fetch (SIM_CPU *, int, unsigned char *, int); -static int cr16_reg_store (SIM_CPU *, int, const unsigned char *, int); +static int cr16_reg_fetch (SIM_CPU *, int, void *, int); +static int cr16_reg_store (SIM_CPU *, int, const void *, int); SIM_DESC sim_open (SIM_OPEN_KIND kind, struct host_callback_struct *cb, @@ -720,7 +720,7 @@ cr16_store_unsigned_integer (unsigned char *addr, int len, uint32_t val) } static int -cr16_reg_fetch (SIM_CPU *cpu, int rn, unsigned char *memory, int length) +cr16_reg_fetch (SIM_CPU *cpu, int rn, void *memory, int length) { int size; switch ((enum sim_cr16_regs) rn) @@ -769,7 +769,7 @@ cr16_reg_fetch (SIM_CPU *cpu, int rn, unsigned char *memory, int length) } static int -cr16_reg_store (SIM_CPU *cpu, int rn, const unsigned char *memory, int length) +cr16_reg_store (SIM_CPU *cpu, int rn, const void *memory, int length) { SIM_DESC sd = CPU_STATE (cpu); int size; diff --git a/sim/cris/cris-tmpl.c b/sim/cris/cris-tmpl.c index a21a79a..2b5c14a 100644 --- a/sim/cris/cris-tmpl.c +++ b/sim/cris/cris-tmpl.c @@ -78,8 +78,8 @@ MY (f_break_handler) (SIM_CPU *cpu, USI breaknum, USI pc) Note the contents of BUF are in target byte order. */ int -MY (f_fetch_register) (SIM_CPU *current_cpu, int rn, - unsigned char *buf, int len ATTRIBUTE_UNUSED) +MY (f_fetch_register) (SIM_CPU *current_cpu, int rn, void *buf, + int len ATTRIBUTE_UNUSED) { SETTSI (buf, XCONCAT3(crisv,BASENUM,f_h_gr_get) (current_cpu, rn)); return -1; @@ -89,8 +89,8 @@ MY (f_fetch_register) (SIM_CPU *current_cpu, int rn, Note the contents of BUF are in target byte order. */ int -MY (f_store_register) (SIM_CPU *current_cpu, int rn, - const unsigned char *buf, int len ATTRIBUTE_UNUSED) +MY (f_store_register) (SIM_CPU *current_cpu, int rn, const void *buf, + int len ATTRIBUTE_UNUSED) { XCONCAT3(crisv,BASENUM,f_h_gr_set) (current_cpu, rn, GETTSI (buf)); return -1; diff --git a/sim/d10v/interp.c b/sim/d10v/interp.c index f17033f..496ccff 100644 --- a/sim/d10v/interp.c +++ b/sim/d10v/interp.c @@ -743,8 +743,8 @@ free_state (SIM_DESC sd) sim_state_free (sd); } -static int d10v_reg_fetch (SIM_CPU *, int, unsigned char *, int); -static int d10v_reg_store (SIM_CPU *, int, const unsigned char *, int); +static int d10v_reg_fetch (SIM_CPU *, int, void *, int); +static int d10v_reg_store (SIM_CPU *, int, const void *, int); SIM_DESC sim_open (SIM_OPEN_KIND kind, host_callback *cb, @@ -1209,7 +1209,7 @@ sim_create_inferior (SIM_DESC sd, struct bfd *abfd, } static int -d10v_reg_fetch (SIM_CPU *cpu, int rn, unsigned char *memory, int length) +d10v_reg_fetch (SIM_CPU *cpu, int rn, void *memory, int length) { SIM_DESC sd = CPU_STATE (cpu); int size; @@ -1293,7 +1293,7 @@ d10v_reg_fetch (SIM_CPU *cpu, int rn, unsigned char *memory, int length) } static int -d10v_reg_store (SIM_CPU *cpu, int rn, const unsigned char *memory, int length) +d10v_reg_store (SIM_CPU *cpu, int rn, const void *memory, int length) { SIM_DESC sd = CPU_STATE (cpu); int size; diff --git a/sim/erc32/interf.c b/sim/erc32/interf.c index 9e0c5a2..e88e5ed 100644 --- a/sim/erc32/interf.c +++ b/sim/erc32/interf.c @@ -310,8 +310,9 @@ sim_create_inferior(SIM_DESC sd, bfd *abfd, char * const *argv, } int -sim_store_register(SIM_DESC sd, int regno, const unsigned char *value, int length) +sim_store_register(SIM_DESC sd, int regno, const void *buf, int length) { + const unsigned char *value = buf; int regval; regval = (value[0] << 24) | (value[1] << 16) @@ -322,7 +323,7 @@ sim_store_register(SIM_DESC sd, int regno, const unsigned char *value, int lengt int -sim_fetch_register(SIM_DESC sd, int regno, unsigned char *buf, int length) +sim_fetch_register(SIM_DESC sd, int regno, void *buf, int length) { get_regi(&sregs, regno, buf); return -1; diff --git a/sim/frv/frv.c b/sim/frv/frv.c index 6cc95d4..19bf4b9 100644 --- a/sim/frv/frv.c +++ b/sim/frv/frv.c @@ -40,7 +40,7 @@ int frvbf_write_next_vliw_addr_to_LR; /* The contents of BUF are in target byte order. */ int -frvbf_fetch_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, int len) +frvbf_fetch_register (SIM_CPU *current_cpu, int rn, void *buf, int len) { if (SIM_FRV_GR0_REGNUM <= rn && rn <= SIM_FRV_GR63_REGNUM) { @@ -89,7 +89,7 @@ frvbf_fetch_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, int len) /* The contents of BUF are in target byte order. */ int -frvbf_store_register (SIM_CPU *current_cpu, int rn, const unsigned char *buf, int len) +frvbf_store_register (SIM_CPU *current_cpu, int rn, const void *buf, int len) { if (SIM_FRV_GR0_REGNUM <= rn && rn <= SIM_FRV_GR63_REGNUM) { diff --git a/sim/ft32/interp.c b/sim/ft32/interp.c index 65c7141..5625856 100644 --- a/sim/ft32/interp.c +++ b/sim/ft32/interp.c @@ -745,7 +745,7 @@ ft32_lookup_register (SIM_CPU *cpu, int nr) static int ft32_reg_store (SIM_CPU *cpu, int rn, - const unsigned char *memory, + const void *memory, int length) { if (0 <= rn && rn <= 32) @@ -762,7 +762,7 @@ ft32_reg_store (SIM_CPU *cpu, static int ft32_reg_fetch (SIM_CPU *cpu, int rn, - unsigned char *memory, + void *memory, int length) { if (0 <= rn && rn <= 32) diff --git a/sim/h8300/compile.c b/sim/h8300/compile.c index ada7f72..b8256b1 100644 --- a/sim/h8300/compile.c +++ b/sim/h8300/compile.c @@ -4476,11 +4476,13 @@ sim_read (SIM_DESC sd, SIM_ADDR addr, void *buffer, int size) } static int -h8300_reg_store (SIM_CPU *cpu, int rn, const unsigned char *value, int length) +h8300_reg_store (SIM_CPU *cpu, int rn, const void *buf, int length) { + const unsigned char *value = buf; int longval; int shortval; int intval; + longval = (value[0] << 24) | (value[1] << 16) | (value[2] << 8) | value[3]; shortval = (value[0] << 8) | (value[1]); intval = h8300hmode ? longval : shortval; @@ -4522,8 +4524,9 @@ h8300_reg_store (SIM_CPU *cpu, int rn, const unsigned char *value, int length) } static int -h8300_reg_fetch (SIM_CPU *cpu, int rn, unsigned char *buf, int length) +h8300_reg_fetch (SIM_CPU *cpu, int rn, void *buf, int length) { + unsigned char *value = buf; int v; int longreg = 0; @@ -4567,16 +4570,16 @@ h8300_reg_fetch (SIM_CPU *cpu, int rn, unsigned char *buf, int length) /* In Normal mode PC is 2 byte, but other registers are 4 byte */ if ((h8300hmode || longreg) && !(rn == PC_REGNUM && h8300_normal_mode)) { - buf[0] = v >> 24; - buf[1] = v >> 16; - buf[2] = v >> 8; - buf[3] = v >> 0; + value[0] = v >> 24; + value[1] = v >> 16; + value[2] = v >> 8; + value[3] = v >> 0; return 4; } else { - buf[0] = v >> 8; - buf[1] = v; + value[0] = v >> 8; + value[1] = v; return 2; } } diff --git a/sim/iq2000/iq2000.c b/sim/iq2000/iq2000.c index d758867..af8fb49 100644 --- a/sim/iq2000/iq2000.c +++ b/sim/iq2000/iq2000.c @@ -206,7 +206,7 @@ set_h_pc (SIM_CPU *cpu, PCADDR addr) } int -iq2000bf_fetch_register (SIM_CPU *cpu, int nr, unsigned char *buf, int len) +iq2000bf_fetch_register (SIM_CPU *cpu, int nr, void *buf, int len) { if (nr >= GPR0_REGNUM && nr < (GPR0_REGNUM + NR_GPR) @@ -227,7 +227,7 @@ iq2000bf_fetch_register (SIM_CPU *cpu, int nr, unsigned char *buf, int len) } int -iq2000bf_store_register (SIM_CPU *cpu, int nr, const unsigned char *buf, int len) +iq2000bf_store_register (SIM_CPU *cpu, int nr, const void *buf, int len) { if (nr >= GPR0_REGNUM && nr < (GPR0_REGNUM + NR_GPR) diff --git a/sim/lm32/lm32.c b/sim/lm32/lm32.c index e8e8386..21746c3 100644 --- a/sim/lm32/lm32.c +++ b/sim/lm32/lm32.c @@ -31,8 +31,7 @@ /* The contents of BUF are in target byte order. */ int -lm32bf_fetch_register (SIM_CPU * current_cpu, int rn, unsigned char *buf, - int len) +lm32bf_fetch_register (SIM_CPU * current_cpu, int rn, void *buf, int len) { if (rn < 32) SETTSI (buf, lm32bf_h_gr_get (current_cpu, rn)); @@ -52,8 +51,7 @@ lm32bf_fetch_register (SIM_CPU * current_cpu, int rn, unsigned char *buf, /* The contents of BUF are in target byte order. */ int -lm32bf_store_register (SIM_CPU * current_cpu, int rn, const unsigned char *buf, - int len) +lm32bf_store_register (SIM_CPU * current_cpu, int rn, const void *buf, int len) { if (rn < 32) lm32bf_h_gr_set (current_cpu, rn, GETTSI (buf)); diff --git a/sim/m32c/gdb-if.c b/sim/m32c/gdb-if.c index a74dde9..2b33f40 100644 --- a/sim/m32c/gdb-if.c +++ b/sim/m32c/gdb-if.c @@ -291,7 +291,7 @@ reg_size (enum m32c_sim_reg regno) } int -sim_fetch_register (SIM_DESC sd, int regno, unsigned char *buf, int length) +sim_fetch_register (SIM_DESC sd, int regno, void *buf, int length) { size_t size; @@ -403,7 +403,7 @@ sim_fetch_register (SIM_DESC sd, int regno, unsigned char *buf, int length) } int -sim_store_register (SIM_DESC sd, int regno, const unsigned char *buf, int length) +sim_store_register (SIM_DESC sd, int regno, const void *buf, int length) { size_t size; diff --git a/sim/m32r/m32r.c b/sim/m32r/m32r.c index f857369..478a45c 100644 --- a/sim/m32r/m32r.c +++ b/sim/m32r/m32r.c @@ -58,7 +58,7 @@ m32r_decode_gdb_ctrl_regnum (int gdb_regnum) /* The contents of BUF are in target byte order. */ int -m32rbf_fetch_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, int len) +m32rbf_fetch_register (SIM_CPU *current_cpu, int rn, void *buf, int len) { int size = m32rbf_register_size (rn); if (len != size) @@ -98,7 +98,7 @@ m32rbf_fetch_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, int len /* The contents of BUF are in target byte order. */ int -m32rbf_store_register (SIM_CPU *current_cpu, int rn, const unsigned char *buf, int len) +m32rbf_store_register (SIM_CPU *current_cpu, int rn, const void *buf, int len) { int size = m32rbf_register_size (rn); if (len != size) diff --git a/sim/m32r/m32r2.c b/sim/m32r/m32r2.c index a057a4c..8881bc68 100644 --- a/sim/m32r/m32r2.c +++ b/sim/m32r/m32r2.c @@ -30,7 +30,7 @@ /* The contents of BUF are in target byte order. */ int -m32r2f_fetch_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, int len) +m32r2f_fetch_register (SIM_CPU *current_cpu, int rn, void *buf, int len) { return m32rbf_fetch_register (current_cpu, rn, buf, len); } @@ -38,7 +38,7 @@ m32r2f_fetch_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, int len /* The contents of BUF are in target byte order. */ int -m32r2f_store_register (SIM_CPU *current_cpu, int rn, const unsigned char *buf, int len) +m32r2f_store_register (SIM_CPU *current_cpu, int rn, const void *buf, int len) { return m32rbf_store_register (current_cpu, rn, buf, len); } diff --git a/sim/m32r/m32rx.c b/sim/m32r/m32rx.c index deafcbe..e5724c5 100644 --- a/sim/m32r/m32rx.c +++ b/sim/m32r/m32rx.c @@ -30,7 +30,7 @@ along with this program. If not, see <http://www.gnu.org/licenses/>. */ /* The contents of BUF are in target byte order. */ int -m32rxf_fetch_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, int len) +m32rxf_fetch_register (SIM_CPU *current_cpu, int rn, void *buf, int len) { return m32rbf_fetch_register (current_cpu, rn, buf, len); } @@ -38,7 +38,7 @@ m32rxf_fetch_register (SIM_CPU *current_cpu, int rn, unsigned char *buf, int len /* The contents of BUF are in target byte order. */ int -m32rxf_store_register (SIM_CPU *current_cpu, int rn, const unsigned char *buf, int len) +m32rxf_store_register (SIM_CPU *current_cpu, int rn, const void *buf, int len) { return m32rbf_store_register (current_cpu, rn, buf, len); } diff --git a/sim/m68hc11/interp.c b/sim/m68hc11/interp.c index ab87068..49353ba 100644 --- a/sim/m68hc11/interp.c +++ b/sim/m68hc11/interp.c @@ -391,8 +391,8 @@ m68hc11_pc_set (sim_cpu *cpu, sim_cia pc) cpu_set_pc (cpu, pc); } -static int m68hc11_reg_fetch (SIM_CPU *, int, unsigned char *, int); -static int m68hc11_reg_store (SIM_CPU *, int, const unsigned char *, int); +static int m68hc11_reg_fetch (SIM_CPU *, int, void *, int); +static int m68hc11_reg_store (SIM_CPU *, int, const void *, int); SIM_DESC sim_open (SIM_OPEN_KIND kind, host_callback *callback, @@ -531,8 +531,9 @@ sim_create_inferior (SIM_DESC sd, struct bfd *abfd, } static int -m68hc11_reg_fetch (SIM_CPU *cpu, int rn, unsigned char *memory, int length) +m68hc11_reg_fetch (SIM_CPU *cpu, int rn, void *buf, int length) { + unsigned char *memory = buf; uint16_t val; int size = 2; @@ -595,8 +596,9 @@ m68hc11_reg_fetch (SIM_CPU *cpu, int rn, unsigned char *memory, int length) } static int -m68hc11_reg_store (SIM_CPU *cpu, int rn, const unsigned char *memory, int length) +m68hc11_reg_store (SIM_CPU *cpu, int rn, const void *buf, int length) { + const unsigned char *memory = buf; uint16_t val; val = *memory++; diff --git a/sim/mcore/interp.c b/sim/mcore/interp.c index 8ca2eee..0a538b3 100644 --- a/sim/mcore/interp.c +++ b/sim/mcore/interp.c @@ -1242,7 +1242,7 @@ sim_engine_run (SIM_DESC sd, } static int -mcore_reg_store (SIM_CPU *cpu, int rn, const unsigned char *memory, int length) +mcore_reg_store (SIM_CPU *cpu, int rn, const void *memory, int length) { if (rn < NUM_MCORE_REGS && rn >= 0) { @@ -1262,7 +1262,7 @@ mcore_reg_store (SIM_CPU *cpu, int rn, const unsigned char *memory, int length) } static int -mcore_reg_fetch (SIM_CPU *cpu, int rn, unsigned char *memory, int length) +mcore_reg_fetch (SIM_CPU *cpu, int rn, void *memory, int length) { if (rn < NUM_MCORE_REGS && rn >= 0) { diff --git a/sim/microblaze/interp.c b/sim/microblaze/interp.c index 1435ecc..ad0812e 100644 --- a/sim/microblaze/interp.c +++ b/sim/microblaze/interp.c @@ -321,7 +321,7 @@ sim_engine_run (SIM_DESC sd, } static int -microblaze_reg_store (SIM_CPU *cpu, int rn, const unsigned char *memory, int length) +microblaze_reg_store (SIM_CPU *cpu, int rn, const void *memory, int length) { if (rn < NUM_REGS + NUM_SPECIAL && rn >= 0) { @@ -343,7 +343,7 @@ microblaze_reg_store (SIM_CPU *cpu, int rn, const unsigned char *memory, int len } static int -microblaze_reg_fetch (SIM_CPU *cpu, int rn, unsigned char *memory, int length) +microblaze_reg_fetch (SIM_CPU *cpu, int rn, void *memory, int length) { long ival; diff --git a/sim/mips/interp.c b/sim/mips/interp.c index 5540d5c..ab20f07 100644 --- a/sim/mips/interp.c +++ b/sim/mips/interp.c @@ -336,8 +336,8 @@ mips_pc_set (sim_cpu *cpu, sim_cia pc) PC = pc; } -static int mips_reg_fetch (SIM_CPU *, int, unsigned char *, int); -static int mips_reg_store (SIM_CPU *, int, const unsigned char *, int); +static int mips_reg_fetch (SIM_CPU *, int, void *, int); +static int mips_reg_store (SIM_CPU *, int, const void *, int); SIM_DESC sim_open (SIM_OPEN_KIND kind, host_callback *cb, @@ -846,7 +846,7 @@ mips_sim_close (SIM_DESC sd, int quitting) } static int -mips_reg_store (SIM_CPU *cpu, int rn, const unsigned char *memory, int length) +mips_reg_store (SIM_CPU *cpu, int rn, const void *memory, int length) { /* NOTE: gdb (the client) stores registers in target byte order while the simulator uses host byte order */ @@ -925,7 +925,7 @@ mips_reg_store (SIM_CPU *cpu, int rn, const unsigned char *memory, int length) } static int -mips_reg_fetch (SIM_CPU *cpu, int rn, unsigned char *memory, int length) +mips_reg_fetch (SIM_CPU *cpu, int rn, void *memory, int length) { /* NOTE: gdb (the client) stores registers in target byte order while the simulator uses host byte order */ diff --git a/sim/mn10300/interp.c b/sim/mn10300/interp.c index 020fd04..3ea8079 100644 --- a/sim/mn10300/interp.c +++ b/sim/mn10300/interp.c @@ -79,8 +79,8 @@ mn10300_pc_set (sim_cpu *cpu, sim_cia pc) PC = pc; } -static int mn10300_reg_fetch (SIM_CPU *, int, unsigned char *, int); -static int mn10300_reg_store (SIM_CPU *, int, const unsigned char *, int); +static int mn10300_reg_fetch (SIM_CPU *, int, void *, int); +static int mn10300_reg_store (SIM_CPU *, int, const void *, int); /* These default values correspond to expected usage for the chip. */ @@ -332,7 +332,7 @@ sim_create_inferior (SIM_DESC sd, but need to be changed to use the memory map. */ static int -mn10300_reg_fetch (SIM_CPU *cpu, int rn, unsigned char *memory, int length) +mn10300_reg_fetch (SIM_CPU *cpu, int rn, void *memory, int length) { reg_t reg = State.regs[rn]; uint8_t *a = memory; @@ -344,7 +344,7 @@ mn10300_reg_fetch (SIM_CPU *cpu, int rn, unsigned char *memory, int length) } static int -mn10300_reg_store (SIM_CPU *cpu, int rn, const unsigned char *memory, int length) +mn10300_reg_store (SIM_CPU *cpu, int rn, const void *memory, int length) { const uint8_t *a = memory; State.regs[rn] = (a[3] << 24) + (a[2] << 16) + (a[1] << 8) + a[0]; diff --git a/sim/moxie/interp.c b/sim/moxie/interp.c index 325bd14..fec79aa 100644 --- a/sim/moxie/interp.c +++ b/sim/moxie/interp.c @@ -1132,7 +1132,7 @@ sim_engine_run (SIM_DESC sd, } static int -moxie_reg_store (SIM_CPU *scpu, int rn, const unsigned char *memory, int length) +moxie_reg_store (SIM_CPU *scpu, int rn, const void *memory, int length) { if (rn < NUM_MOXIE_REGS && rn >= 0) { @@ -1152,7 +1152,7 @@ moxie_reg_store (SIM_CPU *scpu, int rn, const unsigned char *memory, int length) } static int -moxie_reg_fetch (SIM_CPU *scpu, int rn, unsigned char *memory, int length) +moxie_reg_fetch (SIM_CPU *scpu, int rn, void *memory, int length) { if (rn < NUM_MOXIE_REGS && rn >= 0) { diff --git a/sim/msp430/msp430-sim.c b/sim/msp430/msp430-sim.c index d253f2e..5a8479c 100644 --- a/sim/msp430/msp430-sim.c +++ b/sim/msp430/msp430-sim.c @@ -46,24 +46,26 @@ msp430_pc_store (SIM_CPU *cpu, sim_cia newpc) } static int -msp430_reg_fetch (SIM_CPU *cpu, int regno, unsigned char *buf, int len) +msp430_reg_fetch (SIM_CPU *cpu, int regno, void *buf, int len) { + unsigned char *memory = buf; + if (0 <= regno && regno < 16) { if (len == 2) { int val = cpu->state.regs[regno]; - buf[0] = val & 0xff; - buf[1] = (val >> 8) & 0xff; + memory[0] = val & 0xff; + memory[1] = (val >> 8) & 0xff; return 0; } else if (len == 4) { int val = cpu->state.regs[regno]; - buf[0] = val & 0xff; - buf[1] = (val >> 8) & 0xff; - buf[2] = (val >> 16) & 0x0f; /* Registers are only 20 bits wide. */ - buf[3] = 0; + memory[0] = val & 0xff; + memory[1] = (val >> 8) & 0xff; + memory[2] = (val >> 16) & 0x0f; /* Registers are only 20 bits wide. */ + memory[3] = 0; return 0; } else @@ -74,20 +76,22 @@ msp430_reg_fetch (SIM_CPU *cpu, int regno, unsigned char *buf, int len) } static int -msp430_reg_store (SIM_CPU *cpu, int regno, const unsigned char *buf, int len) +msp430_reg_store (SIM_CPU *cpu, int regno, const void *buf, int len) { + const unsigned char *memory = buf; + if (0 <= regno && regno < 16) { if (len == 2) { - cpu->state.regs[regno] = (buf[1] << 8) | buf[0]; + cpu->state.regs[regno] = (memory[1] << 8) | memory[0]; return len; } if (len == 4) { - cpu->state.regs[regno] = ((buf[2] << 16) & 0xf0000) - | (buf[1] << 8) | buf[0]; + cpu->state.regs[regno] = ((memory[2] << 16) & 0xf0000) + | (memory[1] << 8) | memory[0]; return len; } } diff --git a/sim/or1k/or1k-sim.h b/sim/or1k/or1k-sim.h index 045f171..4172720 100644 --- a/sim/or1k/or1k-sim.h +++ b/sim/or1k/or1k-sim.h @@ -68,10 +68,9 @@ void or1k32bf_nop (sim_cpu *current_cpu, USI uimm16); USI or1k32bf_mfspr (sim_cpu *current_cpu, USI addr); void or1k32bf_mtspr (sim_cpu *current_cpu, USI addr, USI val); -int or1k32bf_fetch_register (sim_cpu *current_cpu, int rn, unsigned char *buf, +int or1k32bf_fetch_register (sim_cpu *current_cpu, int rn, void *buf, int len); +int or1k32bf_store_register (sim_cpu *current_cpu, int rn, const void *buf, int len); -int or1k32bf_store_register (sim_cpu *current_cpu, int rn, - const unsigned char *buf, int len); int or1k32bf_model_or1200_u_exec (sim_cpu *current_cpu, const IDESC *idesc, int unit_num, int referenced); int or1k32bf_model_or1200nd_u_exec (sim_cpu *current_cpu, const IDESC *idesc, diff --git a/sim/or1k/or1k.c b/sim/or1k/or1k.c index 488d756..1d2d51f 100644 --- a/sim/or1k/or1k.c +++ b/sim/or1k/or1k.c @@ -31,8 +31,7 @@ #include <string.h> int -or1k32bf_fetch_register (sim_cpu *current_cpu, int rn, unsigned char *buf, - int len) +or1k32bf_fetch_register (sim_cpu *current_cpu, int rn, void *buf, int len) { if (rn < 32) SETTWI (buf, GET_H_GPR (rn)); @@ -55,8 +54,7 @@ or1k32bf_fetch_register (sim_cpu *current_cpu, int rn, unsigned char *buf, } int -or1k32bf_store_register (sim_cpu *current_cpu, int rn, const unsigned char *buf, - int len) +or1k32bf_store_register (sim_cpu *current_cpu, int rn, const void *buf, int len) { if (rn < 32) SET_H_GPR (rn, GETTWI (buf)); diff --git a/sim/ppc/gdb-sim.c b/sim/ppc/gdb-sim.c index 8cf3638..5c4ad11 100644 --- a/sim/ppc/gdb-sim.c +++ b/sim/ppc/gdb-sim.c @@ -1269,7 +1269,7 @@ regnum2name (int regnum) int -sim_fetch_register (SIM_DESC sd, int regno, unsigned char *buf, int length) +sim_fetch_register (SIM_DESC sd, int regno, void *buf, int length) { const char *regname = regnum2name (regno); @@ -1284,8 +1284,7 @@ sim_fetch_register (SIM_DESC sd, int regno, unsigned char *buf, int length) int -sim_store_register (SIM_DESC sd, int regno, const unsigned char *buf, - int length) +sim_store_register (SIM_DESC sd, int regno, const void *buf, int length) { const char *regname = regnum2name (regno); diff --git a/sim/pru/interp.c b/sim/pru/interp.c index 4b7de4c..768e342 100644 --- a/sim/pru/interp.c +++ b/sim/pru/interp.c @@ -650,7 +650,7 @@ pru_pc_set (sim_cpu *cpu, sim_cia pc) /* Implement callback for standard CPU_REG_STORE routine. */ static int -pru_store_register (SIM_CPU *cpu, int rn, const unsigned char *memory, int length) +pru_store_register (SIM_CPU *cpu, int rn, const void *memory, int length) { if (rn < NUM_REGS && rn >= 0) { @@ -673,7 +673,7 @@ pru_store_register (SIM_CPU *cpu, int rn, const unsigned char *memory, int lengt /* Implement callback for standard CPU_REG_FETCH routine. */ static int -pru_fetch_register (SIM_CPU *cpu, int rn, unsigned char *memory, int length) +pru_fetch_register (SIM_CPU *cpu, int rn, void *memory, int length) { long ival; diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c index 1cf7111..6f253d5 100644 --- a/sim/riscv/sim-main.c +++ b/sim/riscv/sim-main.c @@ -1021,7 +1021,7 @@ pc_set (sim_cpu *cpu, sim_cia pc) } static int -reg_fetch (sim_cpu *cpu, int rn, unsigned char *buf, int len) +reg_fetch (sim_cpu *cpu, int rn, void *buf, int len) { if (len <= 0 || len > sizeof (unsigned_word)) return -1; @@ -1054,7 +1054,7 @@ reg_fetch (sim_cpu *cpu, int rn, unsigned char *buf, int len) } static int -reg_store (sim_cpu *cpu, int rn, const unsigned char *buf, int len) +reg_store (sim_cpu *cpu, int rn, const void *buf, int len) { if (len <= 0 || len > sizeof (unsigned_word)) return -1; diff --git a/sim/rl78/gdb-if.c b/sim/rl78/gdb-if.c index ef6c75d..15653cb 100644 --- a/sim/rl78/gdb-if.c +++ b/sim/rl78/gdb-if.c @@ -327,7 +327,7 @@ reg_addr (enum sim_rl78_regnum regno) notion of the register's size. */ int -sim_fetch_register (SIM_DESC sd, int regno, unsigned char *buf, int length) +sim_fetch_register (SIM_DESC sd, int regno, void *buf, int length) { size_t size; SI val; @@ -356,7 +356,7 @@ sim_fetch_register (SIM_DESC sd, int regno, unsigned char *buf, int length) LENGTH must match the sim's internal notion of the register size. */ int -sim_store_register (SIM_DESC sd, int regno, const unsigned char *buf, int length) +sim_store_register (SIM_DESC sd, int regno, const void *buf, int length) { size_t size; SI val; diff --git a/sim/rx/gdb-if.c b/sim/rx/gdb-if.c index 20bb9ef..d4cab50 100644 --- a/sim/rx/gdb-if.c +++ b/sim/rx/gdb-if.c @@ -422,7 +422,7 @@ reg_size (enum sim_rx_regnum regno) } int -sim_fetch_register (SIM_DESC sd, int regno, unsigned char *buf, int length) +sim_fetch_register (SIM_DESC sd, int regno, void *buf, int length) { size_t size; DI val; @@ -532,7 +532,7 @@ sim_fetch_register (SIM_DESC sd, int regno, unsigned char *buf, int length) } int -sim_store_register (SIM_DESC sd, int regno, const unsigned char *buf, int length) +sim_store_register (SIM_DESC sd, int regno, const void *buf, int length) { size_t size; DI val; diff --git a/sim/sh/interp.c b/sim/sh/interp.c index 21de384..bfac1ba 100644 --- a/sim/sh/interp.c +++ b/sim/sh/interp.c @@ -1913,7 +1913,7 @@ enum { }; static int -sh_reg_store (SIM_CPU *cpu, int rn, const unsigned char *memory, int length) +sh_reg_store (SIM_CPU *cpu, int rn, const void *memory, int length) { unsigned val; @@ -2086,7 +2086,7 @@ sh_reg_store (SIM_CPU *cpu, int rn, const unsigned char *memory, int length) } static int -sh_reg_fetch (SIM_CPU *cpu, int rn, unsigned char *memory, int length) +sh_reg_fetch (SIM_CPU *cpu, int rn, void *memory, int length) { int val; diff --git a/sim/v850/interp.c b/sim/v850/interp.c index d0fd132..ab98571 100644 --- a/sim/v850/interp.c +++ b/sim/v850/interp.c @@ -184,8 +184,8 @@ v850_pc_set (sim_cpu *cpu, sim_cia pc) PC = pc; } -static int v850_reg_fetch (SIM_CPU *, int, unsigned char *, int); -static int v850_reg_store (SIM_CPU *, int, const unsigned char *, int); +static int v850_reg_fetch (SIM_CPU *, int, void *, int); +static int v850_reg_store (SIM_CPU *, int, const void *, int); SIM_DESC sim_open (SIM_OPEN_KIND kind, @@ -313,14 +313,14 @@ sim_create_inferior (SIM_DESC sd, } static int -v850_reg_fetch (SIM_CPU *cpu, int rn, unsigned char *memory, int length) +v850_reg_fetch (SIM_CPU *cpu, int rn, void *memory, int length) { *(uint32_t*)memory = H2T_4 (State.regs[rn]); return -1; } static int -v850_reg_store (SIM_CPU *cpu, int rn, const unsigned char *memory, int length) +v850_reg_store (SIM_CPU *cpu, int rn, const void *memory, int length) { State.regs[rn] = T2H_4 (*(uint32_t *) memory); return length; |