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-rw-r--r--sim/v850/ChangeLog12
-rw-r--r--sim/v850/gencode.c14
-rw-r--r--sim/v850/simops.c78
-rw-r--r--sim/v850/v850_sim.h78
4 files changed, 131 insertions, 51 deletions
diff --git a/sim/v850/ChangeLog b/sim/v850/ChangeLog
index 9fbed09..7dd47e1 100644
--- a/sim/v850/ChangeLog
+++ b/sim/v850/ChangeLog
@@ -1,3 +1,15 @@
+Thu Oct 24 10:33:33 1996 Stu Grossman (grossman@critters.cygnus.com)
+
+ * Makefile.in: Get rid of srcroot. Set all INSTALL macros via
+ autoconf.
+ * gencode.c (write_opcodes): Pad operands field to account for
+ MSVC braindamage.
+ * simops.c: Include errno.h. Exclude SYS_chown, since MSVC
+ doesn't support it. (Why is this here in the first place?!?)
+ * v850_sim.h: Get rid of 64 bit defs. Also, get rid of #elif's.
+ Change number of operands in struct simops from 9 to 6. Define
+ SIGTRAP and SIGQUIT for MSVC.
+
Tue Oct 15 16:19:51 1996 Stu Grossman (grossman@critters.cygnus.com)
* interp.c (MEM_SIZE): It's now bytes, not a power of 2.
diff --git a/sim/v850/gencode.c b/sim/v850/gencode.c
index a637fe2..52146cb 100644
--- a/sim/v850/gencode.c
+++ b/sim/v850/gencode.c
@@ -86,6 +86,7 @@ write_opcodes ()
{
struct v850_opcode *opcode;
int i, j;
+ int numops;
/* write out opcode table */
printf ("#include \"v850_sim.h\"\n");
@@ -111,6 +112,7 @@ write_opcodes ()
printf ("%d,{",j);
j = 0;
+ numops = 0;
for (i = 0; i < 6; i++)
{
int flags = v850_operands[opcode->operands[i]].flags;
@@ -123,9 +125,19 @@ write_opcodes ()
printf ("%d,%d,%d", shift,
v850_operands[opcode->operands[i]].bits,flags);
j = 1;
+ numops++;
}
}
+
+ switch (numops)
+ {
+ case 0:
+ printf ("0,0,0");
+ case 1:
+ printf (",0,0,0");
+ }
+
printf ("}},\n");
}
- printf ("{ 0,0,NULL,0,{ }},\n};\n");
+ printf ("{ 0,0,NULL,0,{0,0,0,0,0,0}},\n};\n");
}
diff --git a/sim/v850/simops.c b/sim/v850/simops.c
index 0b92c89..31fa244 100644
--- a/sim/v850/simops.c
+++ b/sim/v850/simops.c
@@ -3,6 +3,7 @@
#include "simops.h"
#include "sys/syscall.h"
#include "bfd.h"
+#include <errno.h>
enum op_types {
OP_UNKNOWN,
@@ -150,7 +151,7 @@ trace_input (name, type, size)
case OP_IMM_REG:
case OP_IMM_REG_CMP:
case OP_IMM_REG_MOVE:
- sprintf (buf, "%d,r%d", OP[1], OP[0]);
+ sprintf (buf, "%d,r%d", OP[0], OP[1]);
break;
case OP_COND_BR:
@@ -166,11 +167,11 @@ trace_input (name, type, size)
break;
case OP_LOAD32:
- sprintf (buf, "%d[r%d],r%d", SEXT16 (OP[2]), OP[0], OP[1]);
+ sprintf (buf, "%d[r%d],r%d", SEXT16 (OP[2]) & ~0x1, OP[0], OP[1]);
break;
case OP_STORE32:
- sprintf (buf, "r%d,%d[r%d]", OP[1], SEXT16 (OP[2]), OP[0]);
+ sprintf (buf, "r%d,%d[r%d]", OP[1], SEXT16 (OP[2] & ~0x1), OP[0]);
break;
case OP_JUMP:
@@ -424,7 +425,7 @@ OP_300 ()
temp = OP[1];
temp = SEXT7 (temp);
op2 = temp;
- result = get_byte (State.mem + State.regs[30] + op2);
+ result = load_mem (State.regs[30] + op2, 1);
State.regs[OP[0]] = SEXT8 (result);
trace_output (OP_LOAD16);
}
@@ -440,7 +441,7 @@ OP_400 ()
temp = OP[1];
temp = SEXT7 (temp);
op2 = temp << 1;
- result = get_half (State.mem + State.regs[30] + op2);
+ result = load_mem (State.regs[30] + op2, 2);
State.regs[OP[0]] = SEXT16 (result);
trace_output (OP_LOAD16);
}
@@ -456,7 +457,7 @@ OP_500 ()
temp = OP[1];
temp = SEXT7 (temp);
op2 = temp << 2;
- result = get_word (State.mem + State.regs[30] + op2);
+ result = load_mem (State.regs[30] + op2, 4);
State.regs[OP[0]] = result;
trace_output (OP_LOAD16);
}
@@ -473,7 +474,7 @@ OP_380 ()
temp = OP[1];
temp = SEXT7 (temp);
op1 = temp;
- put_byte (State.mem + State.regs[30] + op1, op0);
+ store_mem (State.regs[30] + op1, 1, op0);
trace_output (OP_STORE16);
}
@@ -489,7 +490,7 @@ OP_480 ()
temp = OP[1];
temp = SEXT7 (temp);
op1 = temp << 1;
- put_half (State.mem + State.regs[30] + op1, op0);
+ store_mem (State.regs[30] + op1, 2, op0);
trace_output (OP_STORE16);
}
@@ -505,7 +506,7 @@ OP_501 ()
temp = OP[1];
temp = SEXT7 (temp);
op1 = temp << 2;
- put_word (State.mem + State.regs[30] + op1, op0);
+ store_mem (State.regs[30] + op1, 4, op0);
trace_output (OP_STORE16);
}
@@ -520,7 +521,7 @@ OP_700 ()
op0 = State.regs[OP[0]];
temp = SEXT16 (OP[2]);
op2 = temp;
- result = get_byte (State.mem + op0 + op2);
+ result = load_mem (op0 + op2, 1);
State.regs[OP[1]] = SEXT8 (result);
trace_output (OP_LOAD32);
}
@@ -537,7 +538,7 @@ OP_720 ()
temp = SEXT16 (OP[2]);
temp &= ~0x1;
op2 = temp;
- result = get_half (State.mem + op0 + op2);
+ result = load_mem (op0 + op2, 2);
State.regs[OP[1]] = SEXT16 (result);
trace_output (OP_LOAD32);
}
@@ -554,7 +555,7 @@ OP_10720 ()
temp = SEXT16 (OP[2]);
temp &= ~0x1;
op2 = temp;
- result = get_word (State.mem + op0 + op2);
+ result = load_mem (op0 + op2, 4);
State.regs[OP[1]] = result;
trace_output (OP_LOAD32);
}
@@ -571,7 +572,7 @@ OP_740 ()
op1 = State.regs[OP[1]];
temp = SEXT16 (OP[2]);
op2 = temp;
- put_byte (State.mem + op0 + op2, op1);
+ store_mem (op0 + op2, 1, op1);
trace_output (OP_STORE32);
}
@@ -587,7 +588,7 @@ OP_760 ()
op1 = State.regs[OP[1]];
temp = SEXT16 (OP[2] & ~0x1);
op2 = temp;
- put_half (State.mem + op0 + op2, op1);
+ store_mem (op0 + op2, 2, op1);
trace_output (OP_STORE32);
}
@@ -603,7 +604,7 @@ OP_10760 ()
op1 = State.regs[OP[1]];
temp = SEXT16 (OP[2] & ~0x1);
op2 = temp;
- put_word (State.mem + op0 + op2, op1);
+ store_mem (op0 + op2, 4, op1);
trace_output (OP_STORE32);
}
@@ -1828,12 +1829,12 @@ OP_7C0 ()
op1 = OP[1] & 0x7;
temp = SEXT16 (OP[2]);
op2 = temp;
- temp = get_byte (State.mem + op0 + op2);
+ temp = load_mem (op0 + op2, 1);
State.sregs[5] &= ~PSW_Z;
if ((temp & (1 << op1)) == 0)
State.sregs[5] |= PSW_Z;
temp |= (1 << op1);
- put_byte (State.mem + op0 + op2, temp);
+ store_mem (op0 + op2, 1, temp);
trace_output (OP_BIT);
}
@@ -1849,12 +1850,12 @@ OP_47C0 ()
op1 = OP[1] & 0x7;
temp = SEXT16 (OP[2]);
op2 = temp;
- temp = get_byte (State.mem + op0 + op2);
+ temp = load_mem (op0 + op2, 1);
State.sregs[5] &= ~PSW_Z;
if ((temp & (1 << op1)) == 0)
State.sregs[5] |= PSW_Z;
temp ^= (1 << op1);
- put_byte (State.mem + op0 + op2, temp);
+ store_mem (op0 + op2, 1, temp);
trace_output (OP_BIT);
}
@@ -1870,12 +1871,12 @@ OP_87C0 ()
op1 = OP[1] & 0x7;
temp = SEXT16 (OP[2]);
op2 = temp;
- temp = get_byte (State.mem + op0 + op2);
+ temp = load_mem (op0 + op2, 1);
State.sregs[5] &= ~PSW_Z;
if ((temp & (1 << op1)) == 0)
State.sregs[5] |= PSW_Z;
temp &= ~(1 << op1);
- put_byte (State.mem + op0 + op2, temp);
+ store_mem (op0 + op2, 1, temp);
trace_output (OP_BIT);
}
@@ -1891,7 +1892,7 @@ OP_C7C0 ()
op1 = OP[1] & 0x7;
temp = SEXT16 (OP[2]);
op2 = temp;
- temp = get_byte (State.mem + op0 + op2);
+ temp = load_mem (op0 + op2, 1);
State.sregs[5] &= ~PSW_Z;
if ((temp & (1 << op1)) == 0)
State.sregs[5] |= PSW_Z;
@@ -1939,7 +1940,17 @@ OP_14007E0 ()
{
trace_input ("reti", OP_NONE, 0);
trace_output (OP_NONE);
- abort ();
+
+ if ((State.sregs[5] & (PSW_NP | PSW_EP)) == PSW_NP)
+ { /* Only NP is on */
+ PC = State.sregs[2] - 4; /* FEPC */
+ State.sregs[5] = State.sregs[3]; /* FEPSW */
+ }
+ else
+ {
+ PC = State.sregs[0] - 4; /* EIPC */
+ State.sregs[5] = State.sregs[1]; /* EIPSW */
+ }
}
/* trap, not supportd */
@@ -1951,9 +1962,9 @@ OP_10007E0 ()
trace_input ("trap", OP_TRAP, 0);
trace_output (OP_TRAP);
- /* Trap 0 is used for simulating low-level I/O */
+ /* Trap 31 is used for simulating OS I/O functions */
- if (OP[0] == 0)
+ if (OP[0] == 31)
{
int save_errno = errno;
errno = 0;
@@ -1972,8 +1983,7 @@ OP_10007E0 ()
/* Turn a pointer in a register into a pointer into real memory. */
-#define MEMPTR(x) ((char *)((x) + State.mem))
-
+#define MEMPTR(x) (map (x))
switch (FUNC)
{
@@ -2069,12 +2079,12 @@ OP_10007E0 ()
SLW (buf+28, host_stat.st_mtime);
SLW (buf+36, host_stat.st_ctime);
}
-#endif
break;
case SYS_chown:
RETVAL = chown (MEMPTR (PARM1), PARM2, PARM3);
break;
+#endif
case SYS_chmod:
RETVAL = chmod (MEMPTR (PARM1), PARM2);
break;
@@ -2089,10 +2099,14 @@ OP_10007E0 ()
RETERR = errno;
errno = save_errno;
}
- else if (OP[0] == 1 )
- {
- char *fstr = State.regs[2] + State.mem;
- puts (fstr);
+ else
+ { /* Trap 0 -> 30 */
+ State.sregs[0] = PC + 4; /* EIPC */
+ State.sregs[1] = State.sregs[5]; /* EIPSW */
+ State.sregs[4] &= 0xffff0000; /* Mask out EICC */
+ State.sregs[4] |= 0x40 + OP[0]; /* EICC */
+ State.sregs[5] |= PSW_EP | PSW_ID; /* Now doing exception processing */
+ PC = ((OP[0] < 0x10) ? 0x40 : 0x50) - 4;
}
}
diff --git a/sim/v850/v850_sim.h b/sim/v850/v850_sim.h
index e4b7746..641c9e5 100644
--- a/sim/v850/v850_sim.h
+++ b/sim/v850/v850_sim.h
@@ -3,17 +3,45 @@
#include "ansidecl.h"
#include "callback.h"
#include "opcode/v850.h"
+#include <limits.h>
+#include "remote-sim.h"
extern host_callback *v850_callback;
-/* FIXME: host defines */
+#define DEBUG_TRACE 0x00000001
+#define DEBUG_VALUES 0x00000002
+
+extern int v850_debug;
+
+#if UCHAR_MAX == 255
typedef unsigned char uint8;
-typedef unsigned short uint16;
-typedef unsigned int uint32;
typedef signed char int8;
+#else
+#error "Char is not an 8-bit type"
+#endif
+
+#if SHRT_MAX == 32767
+typedef unsigned short uint16;
typedef signed short int16;
+#else
+#error "Short is not a 16-bit type"
+#endif
+
+#if INT_MAX == 2147483647
+
+typedef unsigned int uint32;
typedef signed int int32;
-typedef signed long long int64;
+
+#else
+# if LONG_MAX == 2147483647
+
+typedef unsigned long uint32;
+typedef signed long int32;
+
+# else
+# error "Neither int nor long is a 32-bit type"
+# endif
+#endif
/* FIXME: V850 defines */
typedef uint32 reg_t;
@@ -24,7 +52,7 @@ struct simops
long mask;
void (*func)();
int numops;
- int operands[9];
+ int operands[6];
};
struct _state
@@ -50,17 +78,29 @@ extern struct simops Simops[];
#define PSW_S 0x2
#define PSW_Z 0x1
-#define SEXT3(x) ((((x)&0x7)^(~3))+4)
+#define SEXT3(x) ((((x)&0x7)^(~0x3))+0x4)
/* sign-extend a 4-bit number */
-#define SEXT4(x) ((((x)&0xf)^(~7))+8)
+#define SEXT4(x) ((((x)&0xf)^(~0x7))+0x8)
+
+/* sign-extend a 5-bit number */
+#define SEXT5(x) ((((x)&0x1f)^(~0xf))+0x10)
+
+/* sign-extend a 7-bit number */
+#define SEXT7(x) ((((x)&0x7f)^(~0x4f))+0x40)
/* sign-extend an 8-bit number */
#define SEXT8(x) ((((x)&0xff)^(~0x7f))+0x80)
+/* sign-extend a 9-bit number */
+#define SEXT9(x) ((((x)&0x1ff)^(~0xff))+0x100)
+
/* sign-extend a 16-bit number */
#define SEXT16(x) ((((x)&0xffff)^(~0x7fff))+0x8000)
+/* sign-extend a 22-bit number */
+#define SEXT22(x) ((((x)&0x3fffff)^(~0x1fffff))+0x200000)
+
/* sign-extend a 32-bit number */
#define SEXT32(x) ((((x)&0xffffffffLL)^(~0x7fffffffLL))+0x80000000LL)
@@ -80,22 +120,24 @@ extern struct simops Simops[];
#define INC_ADDR(x,i) x = ((State.MD && x == MOD_E) ? MOD_S : (x)+(i))
-#define RB(x) (*((uint8 *)((x)+State.mem)))
-#define SB(addr,data) ( RB(addr) = (data & 0xff))
-
-#ifdef WORDS_BIGENDIAN
+/*#define RB(x) (*((uint8 *)((x)+State.mem)))*/
+/*#define SB(addr,data) ( RB(addr) = (data & 0xff))*/
uint32 get_word PARAMS ((uint8 *));
uint16 get_half PARAMS ((uint8 *));
uint8 get_byte PARAMS ((uint8 *));
-#define RLW(x) (*((uint32 *)((x)+State.mem)))
+void put_word PARAMS ((uint8 *, uint32));
+void put_half PARAMS ((uint8 *, uint16));
+void put_byte PARAMS ((uint8 *, uint8));
-#else
+uint32 load_mem PARAMS ((SIM_ADDR addr, int len));
+void store_mem PARAMS ((SIM_ADDR addr, int len, uint32 data));
-uint32 get_word PARAMS ((uint8 *));
-uint16 get_half PARAMS ((uint8 *));
-uint8 get_byte PARAMS ((uint8 *));
+uint8 *map PARAMS ((SIM_ADDR addr));
-#define RLW(x) get_word((long)(x)+State.mem)
+#define RLW(x) load_mem (x, 4)
-#endif /* not WORDS_BIGENDIAN */
+#ifdef _WIN32
+#define SIGTRAP 5
+#define SIGQUIT 3
+#endif
generated by cgit v1.1 at 2024-11-10 12:20:17 +0000