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-rw-r--r--cpu/ChangeLog30
-rw-r--r--cpu/bpf.cpu332
-rw-r--r--cpu/bpf.opc1
-rw-r--r--opcodes/ChangeLog8
-rw-r--r--opcodes/bpf-desc.c298
-rw-r--r--opcodes/bpf-dis.c1
-rw-r--r--opcodes/bpf-opc.c120
-rw-r--r--opcodes/bpf-opc.h20
8 files changed, 515 insertions, 295 deletions
diff --git a/cpu/ChangeLog b/cpu/ChangeLog
index f791c00..30b884c 100644
--- a/cpu/ChangeLog
+++ b/cpu/ChangeLog
@@ -1,3 +1,33 @@
+2020-05-28 Jose E. Marchesi <jose.marchesi@oracle.com>
+ David Faust <david.faust@oracle.com>
+
+ * bpf.cpu (define-alu-insn-un): Add definitions of semantics.
+ (define-alu-insn-mov): Likewise.
+ (daib): Likewise.
+ (define-alu-instructions): Likewise.
+ (define-endian-insn): Likewise.
+ (define-lddw): Likewise.
+ (dlabs): Likewise.
+ (dlind): Likewise.
+ (dxli): Likewise.
+ (dxsi): Likewise.
+ (dsti): Likewise.
+ (define-ldstx-insns): Likewise.
+ (define-st-insns): Likewise.
+ (define-cond-jump-insn): Likewise.
+ (dcji): Likewise.
+ (define-condjump-insns): Likewise.
+ (define-call-insn): Likewise.
+ (ja): Likewise.
+ ("exit"): Likewise.
+ (define-atomic-insns): Likewise.
+ (sem-exchange-and-add): New macro.
+ * bpf.cpu ("brkpt"): New instruction.
+ (bpfbf): Set word-bitsize to 32 and insn-endian big.
+ (h-gpr): Prefer r0 to `a' and r6 to `ctx'.
+ (h-pc): Expand definition.
+ * bpf.opc (bpf_print_insn): Set endian_code to BIG.
+
2020-05-21 Alan Modra <amodra@gmail.com>
* mep.opc (mep_cgen_expand_macros_and_parse_operand): Replace
diff --git a/cpu/bpf.cpu b/cpu/bpf.cpu
index 89a27fe..47d7cb0 100644
--- a/cpu/bpf.cpu
+++ b/cpu/bpf.cpu
@@ -32,6 +32,10 @@
(name bpf)
(comment "Linux kernel BPF")
(insn-lsb0? #t)
+ ;; XXX explain the default-alignment setting is for the simulator.
+ ;; It is confusing that the simulator follows the emulated memory
+ ;; access conventions for fetching instructions by pieces...
+ (default-alignment unaligned)
(machs bpf)
(isas ebpfle ebpfbe))
@@ -121,7 +125,8 @@
(define-cpu
(name bpfbf)
(comment "Linux kernel eBPF virtual CPU")
- (word-bitsize 32))
+ (insn-endian big)
+ (word-bitsize 64))
(define-mach
(name bpf)
@@ -159,13 +164,19 @@
(r0 0) (r1 1) (r2 2) (r3 3) (r4 4) (r5 5) (r6 6)
(r7 7) (r8 8) (r9 9) (fp 10)
;; Additional names recognized when assembling.
- (a 0) (ctx 6) (r10 10))))
+ (r0 0) (r6 6) (r10 10))))
;; The program counter. CGEN requires it, even if it is not visible
;; to eBPF programs.
-(dnh h-pc "program counter" (PC PROFILE) (pc) () () ())
-
+(define-hardware
+ (name h-pc)
+ (comment "program counter")
+ (attrs PC PROFILE all-isas)
+ (type pc UDI)
+ (get () (raw-reg h-pc))
+ (set (newval) (set (raw-reg h-pc) newval)))
+
;; A 64-bit h-sint to be used by the imm64 operand below. XXX this
;; shouldn't be needed, as h-sint is supposed to be able to hold
;; 64-bit values. However, in practice CGEN limits h-sint to 32 bits
@@ -361,60 +372,101 @@
;; ADD[32]{i,r}le for the little-endian ISA
;; ADD[32]{i,r}be for the big-endian ISA
;;
-;; The `i' variants perform `src OP dst -> dst' operations.
-;; The `r' variants perform `dst OP imm32 -> dst' operations.
+;; The `i' variants perform `dst OP imm32 -> dst' operations.
+;; The `r' variants perform `dst OP src -> dst' operations.
;;
;; The variants with 32 in their name are of ALU class. Otherwise
;; they are ALU64 class.
-(define-pmacro (define-alu-insn-un x-basename x-suffix x-op-class x-op-code x-endian)
+(define-pmacro (define-alu-insn-un x-basename x-suffix x-op-class x-op-code
+ x-endian x-mode x-semop)
(dni (.sym x-basename x-suffix x-endian)
(.str x-basename x-suffix)
((ISA (.sym ebpf x-endian)))
(.str x-basename x-suffix " $dst" x-endian)
(+ (f-imm32 0) (f-offset16 0) ((.sym f-src x-endian) 0) (.sym dst x-endian)
- x-op-class OP_SRC_K x-op-code) () ()))
+ x-op-class OP_SRC_K x-op-code)
+ (set x-mode (.sym dst x-endian) (x-semop x-mode (.sym dst x-endian)))
+ ()))
-(define-pmacro (define-alu-insn-bin x-basename x-suffix x-op-class x-op-code x-endian)
+(define-pmacro (define-alu-insn-bin x-basename x-suffix x-op-class x-op-code
+ x-endian x-mode x-semop)
(begin
+ ;; dst = dst OP immediate
(dni (.sym x-basename x-suffix "i" x-endian)
(.str x-basename x-suffix " immediate")
((ISA (.sym ebpf x-endian)))
(.str x-basename x-suffix " $dst" x-endian ",$imm32")
(+ imm32 (f-offset16 0) ((.sym f-src x-endian) 0) (.sym dst x-endian)
- x-op-class OP_SRC_K x-op-code) () ())
+ x-op-class OP_SRC_K x-op-code)
+ (set x-mode (.sym dst x-endian) (x-semop x-mode (.sym dst x-endian) imm32))
+ ())
+ ;; dst = dst OP src
(dni (.sym x-basename x-suffix "r" x-endian)
(.str x-basename x-suffix " register")
((ISA (.sym ebpf x-endian)))
(.str x-basename x-suffix " $dst" x-endian ",$src" x-endian)
(+ (f-imm32 0) (f-offset16 0) (.sym src x-endian) (.sym dst x-endian)
- x-op-class OP_SRC_X x-op-code) () ())))
+ x-op-class OP_SRC_X x-op-code)
+ (set x-mode (.sym dst x-endian)
+ (x-semop x-mode (.sym dst x-endian) (.sym src x-endian)))
+ ())))
+
+(define-pmacro (define-alu-insn-mov x-basename x-suffix x-op-class x-op-code
+ x-endian x-mode)
+ (begin
+ (dni (.sym mov x-suffix "i" x-endian)
+ (.str mov x-suffix " immediate")
+ ((ISA (.sym ebpf x-endian)))
+ (.str x-basename x-suffix " $dst" x-endian ",$imm32")
+ (+ imm32 (f-offset16 0) ((.sym f-src x-endian) 0) (.sym dst x-endian)
+ x-op-class OP_SRC_K x-op-code)
+ (set x-mode (.sym dst x-endian) imm32)
+ ())
+ (dni (.sym mov x-suffix "r" x-endian)
+ (.str mov x-suffix " register")
+ ((ISA (.sym ebpf x-endian)))
+ (.str x-basename x-suffix " $dst" x-endian ",$src" x-endian)
+ (+ (f-imm32 0) (f-offset16 0) (.sym src x-endian) (.sym dst x-endian)
+ x-op-class OP_SRC_X x-op-code)
+ (set x-mode (.sym dst x-endian) (.sym src x-endian))
+ ())))
+
-(define-pmacro (daiu x-basename x-op-code x-endian)
+;; Unary ALU instructions (neg)
+(define-pmacro (daiu x-basename x-op-code x-endian x-semop)
(begin
- (define-alu-insn-un x-basename "" OP_CLASS_ALU64 x-op-code x-endian)
- (define-alu-insn-un x-basename "32" OP_CLASS_ALU x-op-code x-endian)))
+ (define-alu-insn-un x-basename "" OP_CLASS_ALU64 x-op-code x-endian DI x-semop)
+ (define-alu-insn-un x-basename "32" OP_CLASS_ALU x-op-code x-endian USI x-semop)))
-(define-pmacro (daib x-basename x-op-code x-endian)
+;; Binary ALU instructions (all the others)
+;; For ALU32: DST = (u32) DST OP (u32) SRC is correct semantics
+(define-pmacro (daib x-basename x-op-code x-endian x-semop)
(begin
- (define-alu-insn-bin x-basename "" OP_CLASS_ALU64 x-op-code x-endian)
- (define-alu-insn-bin x-basename "32" OP_CLASS_ALU x-op-code x-endian)))
+ (define-alu-insn-bin x-basename "" OP_CLASS_ALU64 x-op-code x-endian DI x-semop)
+ (define-alu-insn-bin x-basename "32" OP_CLASS_ALU x-op-code x-endian USI x-semop)))
+
+;; Move ALU instructions (mov)
+(define-pmacro (daim x-basename x-op-code x-endian)
+ (begin
+ (define-alu-insn-mov x-basename "" OP_CLASS_ALU64 x-op-code x-endian DI)
+ (define-alu-insn-mov x-basename "32" OP_CLASS_ALU x-op-code x-endian USI)))
(define-pmacro (define-alu-instructions x-endian)
(begin
- (daib add OP_CODE_ADD x-endian)
- (daib sub OP_CODE_SUB x-endian)
- (daib mul OP_CODE_MUL x-endian)
- (daib div OP_CODE_DIV x-endian)
- (daib or OP_CODE_OR x-endian)
- (daib and OP_CODE_AND x-endian)
- (daib lsh OP_CODE_LSH x-endian)
- (daib rsh OP_CODE_RSH x-endian)
- (daib mod OP_CODE_MOD x-endian)
- (daib xor OP_CODE_XOR x-endian)
- (daib mov OP_CODE_MOV x-endian)
- (daib arsh OP_CODE_ARSH x-endian)
- (daiu neg OP_CODE_NEG x-endian)))
+ (daib add OP_CODE_ADD x-endian add)
+ (daib sub OP_CODE_SUB x-endian sub)
+ (daib mul OP_CODE_MUL x-endian mul)
+ (daib div OP_CODE_DIV x-endian div)
+ (daib or OP_CODE_OR x-endian or)
+ (daib and OP_CODE_AND x-endian and)
+ (daib lsh OP_CODE_LSH x-endian sll)
+ (daib rsh OP_CODE_RSH x-endian srl)
+ (daib mod OP_CODE_MOD x-endian mod)
+ (daib xor OP_CODE_XOR x-endian xor)
+ (daib arsh OP_CODE_ARSH x-endian sra)
+ (daiu neg OP_CODE_NEG x-endian neg)
+ (daim mov OP_CODE_MOV x-endian)))
(define-alu-instructions le)
(define-alu-instructions be)
@@ -438,7 +490,10 @@
((ISA (.sym ebpf x-endian)))
(.str "end" x-suffix " $dst" x-endian ",$endsize")
(+ (f-offset16 0) ((.sym f-src x-endian) 0) (.sym dst x-endian) endsize
- OP_CLASS_ALU x-op-src OP_CODE_END) () ()))
+ OP_CLASS_ALU x-op-src OP_CODE_END)
+ (set (.sym dst x-endian)
+ (c-call DI "bpfbf_end" (.sym dst x-endian) endsize))
+ ()))
(define-endian-insn "le" OP_SRC_K le)
(define-endian-insn "be" OP_SRC_X le)
@@ -461,7 +516,9 @@
(.str "lddw $dst" x-endian ",$imm64")
(+ imm64 (f-offset16 0) ((.sym f-src x-endian) 0)
(.sym dst x-endian)
- OP_CLASS_LD OP_SIZE_DW OP_MODE_IMM) () ()))
+ OP_CLASS_LD OP_SIZE_DW OP_MODE_IMM)
+ (set DI (.sym dst x-endian) imm64)
+ ()))
(define-lddw le)
(define-lddw be)
@@ -471,19 +528,33 @@
;;
;; LDABS{w,h,b,dw}
-(define-pmacro (dlabs x-suffix x-size)
+(define-pmacro (dlabs x-suffix x-size x-smode)
(dni (.sym "ldabs" x-suffix)
(.str "ldabs" x-suffix)
(all-isas)
(.str "ldabs" x-suffix " $imm32")
(+ imm32 (f-offset16 0) (f-regs 0)
OP_CLASS_LD OP_MODE_ABS (.sym OP_SIZE_ x-size))
- () ()))
-
-(dlabs "w" W)
-(dlabs "h" H)
-(dlabs "b" B)
-(dlabs "dw" DW)
+ (set x-smode
+ (reg x-smode h-gpr 0)
+ (mem x-smode
+ (add DI
+ (mem DI
+ (add DI
+ (reg DI h-gpr 6) ;; Pointer to struct sk_buff
+ (const DI 0))) ;; XXX offsetof
+ ;; (struct sk_buff, data) XXX but the offset
+ ;; depends on CONFIG_* options, so this should
+ ;; be configured in the simulator and driven by
+ ;; command-line options. Handle with a c-call.
+ imm32)))
+ ;; XXX this clobbers R1-R5
+ ()))
+
+(dlabs "w" W SI)
+(dlabs "h" H HI)
+(dlabs "b" B QI)
+(dlabs "dw" DW DI)
;; The indirect load instructions are non-generic loads designed to be
;; used in socket filters. They come in several variants:
@@ -491,21 +562,37 @@
;; LDIND{w,h,b,dw}le for the little-endian ISA
;; LDIND[w,h,b,dw}be for the big-endian ISA
-(define-pmacro (dlind x-suffix x-size x-endian)
+(define-pmacro (dlind x-suffix x-size x-endian x-smode)
(dni (.sym "ldind" x-suffix x-endian)
(.str "ldind" x-suffix)
((ISA (.sym ebpf x-endian)))
(.str "ldind" x-suffix " $src" x-endian ",$imm32")
(+ imm32 (f-offset16 0) ((.sym f-dst x-endian) 0) (.sym src x-endian)
OP_CLASS_LD OP_MODE_IND (.sym OP_SIZE_ x-size))
- () ()))
+ (set x-smode
+ (reg x-smode h-gpr 0)
+ (mem x-smode
+ (add DI
+ (mem DI
+ (add DI
+ (reg DI h-gpr 6) ;; Pointer to struct sk_buff
+ (const DI 0))) ;; XXX offsetof
+ ;; (struct sk_buff, data) XXX but the offset
+ ;; depends on CONFIG_* options, so this should
+ ;; be configured in the simulator and driven by
+ ;; command-line options. Handle with a c-call.
+ (add DI
+ (.sym src x-endian)
+ imm32))))
+ ;; XXX this clobbers R1-R5
+ ()))
(define-pmacro (define-ldind x-endian)
(begin
- (dlind "w" W x-endian)
- (dlind "h" H x-endian)
- (dlind "b" B x-endian)
- (dlind "dw" DW x-endian)))
+ (dlind "w" W x-endian SI)
+ (dlind "h" H x-endian HI)
+ (dlind "b" B x-endian QI)
+ (dlind "dw" DW x-endian DI)))
(define-ldind le)
(define-ldind be)
@@ -520,35 +607,41 @@
;; Loads operate on [$SRC+-OFFSET] -> $DST
;; Stores operate on $SRC -> [$DST+-OFFSET]
-(define-pmacro (dxli x-basename x-suffix x-size x-endian)
+(define-pmacro (dxli x-basename x-suffix x-size x-endian x-mode)
(dni (.sym x-basename x-suffix x-endian)
(.str x-basename x-suffix)
((ISA (.sym ebpf x-endian)))
(.str x-basename x-suffix " $dst" x-endian ",[$src" x-endian "+$offset16]")
(+ (f-imm32 0) offset16 (.sym src x-endian) (.sym dst x-endian)
OP_CLASS_LDX (.sym OP_SIZE_ x-size) OP_MODE_MEM)
- () ()))
+ (set x-mode
+ (.sym dst x-endian)
+ (mem x-mode (add DI (.sym src x-endian) (ext DI (trunc HI offset16)))))
+ ()))
-(define-pmacro (dxsi x-basename x-suffix x-size x-endian)
+(define-pmacro (dxsi x-basename x-suffix x-size x-endian x-mode)
(dni (.sym x-basename x-suffix x-endian)
(.str x-basename x-suffix)
((ISA (.sym ebpf x-endian)))
(.str x-basename x-suffix " [$dst" x-endian "+$offset16],$src" x-endian)
(+ (f-imm32 0) offset16 (.sym src x-endian) (.sym dst x-endian)
OP_CLASS_STX (.sym OP_SIZE_ x-size) OP_MODE_MEM)
- () ()))
+ (set x-mode
+ (mem x-mode (add DI (.sym dst x-endian) (ext DI (trunc HI offset16))))
+ (.sym src x-endian)) ;; XXX address is section-relative
+ ()))
(define-pmacro (define-ldstx-insns x-endian)
(begin
- (dxli "ldx" "w" W x-endian)
- (dxli "ldx" "h" H x-endian)
- (dxli "ldx" "b" B x-endian)
- (dxli "ldx" "dw" DW x-endian)
+ (dxli "ldx" "w" W x-endian SI)
+ (dxli "ldx" "h" H x-endian HI)
+ (dxli "ldx" "b" B x-endian QI)
+ (dxli "ldx" "dw" DW x-endian DI)
- (dxsi "stx" "w" W x-endian)
- (dxsi "stx" "h" H x-endian)
- (dxsi "stx" "b" B x-endian)
- (dxsi "stx" "dw" DW x-endian)))
+ (dxsi "stx" "w" W x-endian SI)
+ (dxsi "stx" "h" H x-endian HI)
+ (dxsi "stx" "b" B x-endian QI)
+ (dxsi "stx" "dw" DW x-endian DI)))
(define-ldstx-insns le)
(define-ldstx-insns be)
@@ -559,20 +652,24 @@
;; ST{b,h,w,dw}le for the little-endian ISA
;; ST{b,h,w,dw}be for the big-endian ISA
-(define-pmacro (dsti x-suffix x-size x-endian)
+(define-pmacro (dsti x-suffix x-size x-endian x-mode)
(dni (.sym "st" x-suffix x-endian)
(.str "st" x-suffix)
((ISA (.sym ebpf x-endian)))
(.str "st" x-suffix " [$dst" x-endian "+$offset16],$imm32")
(+ imm32 offset16 ((.sym f-src x-endian) 0) (.sym dst x-endian)
- OP_CLASS_ST (.sym OP_SIZE_ x-size) OP_MODE_MEM) () ()))
+ OP_CLASS_ST (.sym OP_SIZE_ x-size) OP_MODE_MEM)
+ (set x-mode
+ (mem x-mode (add DI (.sym dst x-endian) offset16))
+ imm32) ;; XXX address is section-relative
+ ()))
(define-pmacro (define-st-insns x-endian)
(begin
- (dsti "b" B x-endian)
- (dsti "h" H x-endian)
- (dsti "w" W x-endian)
- (dsti "dw" DW x-endian)))
+ (dsti "b" B x-endian QI)
+ (dsti "h" H x-endian HI)
+ (dsti "w" W x-endian SI)
+ (dsti "dw" DW x-endian DI)))
(define-st-insns le)
(define-st-insns be)
@@ -588,64 +685,102 @@
;; J{eq,gt,ge,lt,le,set,ne.sgt,sge,slt,sle}[32]{i,r}be for the
;; big-endian ISA.
-(define-pmacro (define-cond-jump-insn x-cond x-suffix x-op-class x-op-code x-endian)
+(define-pmacro (define-cond-jump-insn x-cond x-suffix x-op-class x-op-code x-endian x-mode x-semop)
(begin
(dni (.sym j x-cond x-suffix i x-endian)
(.str j x-cond x-suffix " i")
((ISA (.sym ebpf x-endian)))
(.str "j" x-cond x-suffix " $dst" x-endian ",$imm32,$disp16")
(+ imm32 disp16 ((.sym f-src x-endian) 0) (.sym dst x-endian)
- x-op-class OP_SRC_K (.sym OP_CODE_ x-op-code)) () ())
+ x-op-class OP_SRC_K (.sym OP_CODE_ x-op-code))
+ (if VOID (x-semop x-mode (.sym dst x-endian) imm32)
+ (set DI
+ (reg DI h-pc) (add DI (reg DI h-pc)
+ (mul DI (add HI disp16 1) 8))))
+ ())
(dni (.sym j x-cond x-suffix r x-endian)
(.str j x-cond x-suffix " r")
((ISA (.sym ebpf x-endian)))
(.str "j" x-cond x-suffix " $dst" x-endian ",$src" x-endian ",$disp16")
(+ (f-imm32 0) disp16 (.sym src x-endian) (.sym dst x-endian)
- x-op-class OP_SRC_X (.sym OP_CODE_ x-op-code)) () ())))
-
-(define-pmacro (dcji x-cond x-op-code x-endian)
+ x-op-class OP_SRC_X (.sym OP_CODE_ x-op-code))
+ (if VOID (x-semop x-mode (.sym dst x-endian) (.sym src x-endian))
+ (set DI
+ (reg DI h-pc) (add DI (reg DI h-pc)
+ (mul DI (add HI disp16 1) 8))))
+ ())))
+
+(define-pmacro (dcji x-cond x-op-code x-endian x-semop)
(begin
- (define-cond-jump-insn x-cond "" OP_CLASS_JMP x-op-code x-endian)
- (define-cond-jump-insn x-cond "32" OP_CLASS_JMP32 x-op-code x-endian)))
+ (define-cond-jump-insn x-cond "" OP_CLASS_JMP x-op-code x-endian DI x-semop)
+ (define-cond-jump-insn x-cond "32" OP_CLASS_JMP32 x-op-code x-endian SI x-semop )))
(define-pmacro (define-condjump-insns x-endian)
(begin
- (dcji "eq" JEQ x-endian)
- (dcji "gt" JGT x-endian)
- (dcji "ge" JGE x-endian)
- (dcji "lt" JLT x-endian)
- (dcji "le" JLE x-endian)
- (dcji "set" JSET x-endian)
- (dcji "ne" JNE x-endian)
- (dcji "sgt" JSGT x-endian)
- (dcji "sge" JSGE x-endian)
- (dcji "slt" JSLT x-endian)
- (dcji "sle" JSLE x-endian)))
+ (dcji "eq" JEQ x-endian eq)
+ (dcji "gt" JGT x-endian gtu)
+ (dcji "ge" JGE x-endian geu)
+ (dcji "lt" JLT x-endian ltu)
+ (dcji "le" JLE x-endian leu)
+ (dcji "set" JSET x-endian and)
+ (dcji "ne" JNE x-endian ne)
+ (dcji "sgt" JSGT x-endian gt)
+ (dcji "sge" JSGE x-endian ge)
+ (dcji "slt" JSLT x-endian lt)
+ (dcji "sle" JSLE x-endian le)))
(define-condjump-insns le)
(define-condjump-insns be)
-;; The jump-always, `call' and `exit' instructions dont make use of
-;; either source nor destination registers, so only one variant per
+;; The `call' instruction doesn't make use of registers, but the
+;; semantic routine should have access to the src register in order to
+;; properly interpret the meaning of disp32. Therefore we need one
+;; version per ISA.
+
+(define-pmacro (define-call-insn x-endian)
+ (dni (.sym call x-endian)
+ "call"
+ ((ISA (.sym ebpf x-endian)))
+ "call $disp32"
+ (+ disp32 (f-offset16 0) (f-regs 0)
+ OP_CLASS_JMP OP_SRC_K OP_CODE_CALL)
+ (c-call VOID
+ "bpfbf_call" disp32 (ifield (.sym f-src x-endian)))
+ ()))
+
+(define-call-insn le)
+(define-call-insn be)
+
+;; The jump-always and `exit' instructions dont make use of either
+;; source nor destination registers, so only one variant per
;; instruction is defined.
(dni ja "ja" (all-isas) "ja $disp16"
(+ (f-imm32 0) disp16 (f-regs 0)
- OP_CLASS_JMP OP_SRC_K OP_CODE_JA) () ())
-
-(dni call "call" (all-isas) "call $disp32"
- (+ disp32 (f-offset16 0) (f-regs 0)
- OP_CLASS_JMP OP_SRC_K OP_CODE_CALL) () ())
+ OP_CLASS_JMP OP_SRC_K OP_CODE_JA)
+ (set DI (reg DI h-pc) (add DI (reg DI h-pc)
+ (mul DI (add HI disp16 1) 8)))
+ ())
(dni "exit" "exit" (all-isas) "exit"
(+ (f-imm32 0) (f-offset16 0) (f-regs 0)
- OP_CLASS_JMP (f-op-src 0) OP_CODE_EXIT) () ())
+ OP_CLASS_JMP (f-op-src 0) OP_CODE_EXIT)
+ (c-call VOID "bpfbf_exit")
+ ())
;;; Atomic instructions
;; The atomic exchange-and-add instructions come in two flavors: one
;; for swapping 64-bit quantities and another for 32-bit quantities.
+(define-pmacro (sem-exchange-and-add x-endian x-mode)
+ (sequence VOID ((x-mode tmp))
+ ;; XXX acquire lock in simulator... as a hardware element?
+ (set x-mode tmp (mem x-mode (add DI (.sym dst x-endian) offset16)))
+ (set x-mode
+ (mem x-mode (add DI (.sym dst x-endian) offset16))
+ (add x-mode tmp (.sym src x-endian)))))
+
(define-pmacro (define-atomic-insns x-endian)
(begin
(dni (.str "xadddw" x-endian)
@@ -653,13 +788,28 @@
((ISA (.sym ebpf x-endian)))
(.str "xadddw [$dst" x-endian "+$offset16],$src" x-endian)
(+ (f-imm32 0) (.sym src x-endian) (.sym dst x-endian)
- offset16 OP_MODE_XADD OP_SIZE_DW OP_CLASS_STX) () ())
+ offset16 OP_MODE_XADD OP_SIZE_DW OP_CLASS_STX)
+ (sem-exchange-and-add x-endian DI)
+ ())
(dni (.str "xaddw" x-endian)
"xaddw"
((ISA (.sym ebpf x-endian)))
(.str "xaddw [$dst" x-endian "+$offset16],$src" x-endian)
(+ (f-imm32 0) (.sym src x-endian) (.sym dst x-endian)
- offset16 OP_MODE_XADD OP_SIZE_W OP_CLASS_STX) () ())))
+ offset16 OP_MODE_XADD OP_SIZE_W OP_CLASS_STX)
+ (sem-exchange-and-add x-endian SI)
+ ())))
(define-atomic-insns le)
(define-atomic-insns be)
+
+;;; Breakpoint instruction
+
+;; The brkpt instruction is used by the BPF simulator and it doesn't
+;; really belong to the eBPF instruction set.
+
+(dni "brkpt" "brkpt" (all-isas) "brkpt"
+ (+ (f-imm32 0) (f-offset16 0) (f-regs 0)
+ OP_CLASS_ALU OP_SRC_X OP_CODE_NEG)
+ (c-call VOID "bpfbf_breakpoint")
+ ())
diff --git a/cpu/bpf.opc b/cpu/bpf.opc
index e70ee04..e2acaa4 100644
--- a/cpu/bpf.opc
+++ b/cpu/bpf.opc
@@ -129,6 +129,7 @@ bpf_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
info->bytes_per_chunk = 1;
info->bytes_per_line = 8;
+ info->endian_code = BFD_ENDIAN_BIG;
/* Attempt to read the base part of the insn. */
buflen = cd->base_insn_bitsize / 8;
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index d361ea7..15405a5 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,11 @@
+2020-05-28 Jose E. Marchesi <jose.marchesi@oracle.com>
+ David Faust <david.faust@oracle.com>
+
+ * bpf-desc.c: Regenerate.
+ * bpf-opc.h: Likewise.
+ * bpf-opc.c: Likewise.
+ * bpf-dis.c: Likewise.
+
2020-05-28 Alan Modra <amodra@gmail.com>
* nios2-dis.c (nios2_print_insn_arg): Avoid shift left of negative
diff --git a/opcodes/bpf-desc.c b/opcodes/bpf-desc.c
index d2803f0..ddd55b9 100644
--- a/opcodes/bpf-desc.c
+++ b/opcodes/bpf-desc.c
@@ -144,8 +144,8 @@ static CGEN_KEYWORD_ENTRY bpf_cgen_opval_h_gpr_entries[] =
{ "%r8", 8, {0, {{{0, 0}}}}, 0, 0 },
{ "%r9", 9, {0, {{{0, 0}}}}, 0, 0 },
{ "%fp", 10, {0, {{{0, 0}}}}, 0, 0 },
- { "%a", 0, {0, {{{0, 0}}}}, 0, 0 },
- { "%ctx", 6, {0, {{{0, 0}}}}, 0, 0 },
+ { "%r0", 0, {0, {{{0, 0}}}}, 0, 0 },
+ { "%r6", 6, {0, {{{0, 0}}}}, 0, 0 },
{ "%r10", 10, {0, {{{0, 0}}}}, 0, 0 }
};
@@ -169,7 +169,7 @@ const CGEN_HW_ENTRY bpf_cgen_hw_table[] =
{ "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
{ "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
{ "h-gpr", HW_H_GPR, CGEN_ASM_KEYWORD, (PTR) & bpf_cgen_opval_h_gpr, { 0, { { { (1<<MACH_BPF), 0 } }, { { 1, "\xc0" } } } } },
- { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } },
+ { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
{ "h-sint64", HW_H_SINT64, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } } },
{ 0, 0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }
};
@@ -494,26 +494,6 @@ static const CGEN_IBASE bpf_cgen_insn_table[MAX_INSNS] =
BPF_INSN_XOR32RLE, "xor32rle", "xor32", 64,
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
},
-/* mov $dstle,$imm32 */
- {
- BPF_INSN_MOVILE, "movile", "mov", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
- },
-/* mov $dstle,$srcle */
- {
- BPF_INSN_MOVRLE, "movrle", "mov", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
- },
-/* mov32 $dstle,$imm32 */
- {
- BPF_INSN_MOV32ILE, "mov32ile", "mov32", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
- },
-/* mov32 $dstle,$srcle */
- {
- BPF_INSN_MOV32RLE, "mov32rle", "mov32", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
- },
/* arsh $dstle,$imm32 */
{
BPF_INSN_ARSHILE, "arshile", "arsh", 64,
@@ -544,6 +524,26 @@ static const CGEN_IBASE bpf_cgen_insn_table[MAX_INSNS] =
BPF_INSN_NEG32LE, "neg32le", "neg32", 64,
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
},
+/* mov $dstle,$imm32 */
+ {
+ BPF_INSN_MOVILE, "movile", "mov", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* mov $dstle,$srcle */
+ {
+ BPF_INSN_MOVRLE, "movrle", "mov", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* mov32 $dstle,$imm32 */
+ {
+ BPF_INSN_MOV32ILE, "mov32ile", "mov32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
+/* mov32 $dstle,$srcle */
+ {
+ BPF_INSN_MOV32RLE, "mov32rle", "mov32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ },
/* add $dstbe,$imm32 */
{
BPF_INSN_ADDIBE, "addibe", "add", 64,
@@ -744,26 +744,6 @@ static const CGEN_IBASE bpf_cgen_insn_table[MAX_INSNS] =
BPF_INSN_XOR32RBE, "xor32rbe", "xor32", 64,
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
},
-/* mov $dstbe,$imm32 */
- {
- BPF_INSN_MOVIBE, "movibe", "mov", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
- },
-/* mov $dstbe,$srcbe */
- {
- BPF_INSN_MOVRBE, "movrbe", "mov", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
- },
-/* mov32 $dstbe,$imm32 */
- {
- BPF_INSN_MOV32IBE, "mov32ibe", "mov32", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
- },
-/* mov32 $dstbe,$srcbe */
- {
- BPF_INSN_MOV32RBE, "mov32rbe", "mov32", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
- },
/* arsh $dstbe,$imm32 */
{
BPF_INSN_ARSHIBE, "arshibe", "arsh", 64,
@@ -794,6 +774,26 @@ static const CGEN_IBASE bpf_cgen_insn_table[MAX_INSNS] =
BPF_INSN_NEG32BE, "neg32be", "neg32", 64,
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
},
+/* mov $dstbe,$imm32 */
+ {
+ BPF_INSN_MOVIBE, "movibe", "mov", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* mov $dstbe,$srcbe */
+ {
+ BPF_INSN_MOVRBE, "movrbe", "mov", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* mov32 $dstbe,$imm32 */
+ {
+ BPF_INSN_MOV32IBE, "mov32ibe", "mov32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* mov32 $dstbe,$srcbe */
+ {
+ BPF_INSN_MOV32RBE, "mov32rbe", "mov32", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
/* endle $dstle,$endsize */
{
BPF_INSN_ENDLELE, "endlele", "endle", 64,
@@ -1007,452 +1007,457 @@ static const CGEN_IBASE bpf_cgen_insn_table[MAX_INSNS] =
/* jeq $dstle,$imm32,$disp16 */
{
BPF_INSN_JEQILE, "jeqile", "jeq", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
},
/* jeq $dstle,$srcle,$disp16 */
{
BPF_INSN_JEQRLE, "jeqrle", "jeq", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
},
/* jeq32 $dstle,$imm32,$disp16 */
{
BPF_INSN_JEQ32ILE, "jeq32ile", "jeq32", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
},
/* jeq32 $dstle,$srcle,$disp16 */
{
BPF_INSN_JEQ32RLE, "jeq32rle", "jeq32", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
},
/* jgt $dstle,$imm32,$disp16 */
{
BPF_INSN_JGTILE, "jgtile", "jgt", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
},
/* jgt $dstle,$srcle,$disp16 */
{
BPF_INSN_JGTRLE, "jgtrle", "jgt", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
},
/* jgt32 $dstle,$imm32,$disp16 */
{
BPF_INSN_JGT32ILE, "jgt32ile", "jgt32", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
},
/* jgt32 $dstle,$srcle,$disp16 */
{
BPF_INSN_JGT32RLE, "jgt32rle", "jgt32", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
},
/* jge $dstle,$imm32,$disp16 */
{
BPF_INSN_JGEILE, "jgeile", "jge", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
},
/* jge $dstle,$srcle,$disp16 */
{
BPF_INSN_JGERLE, "jgerle", "jge", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
},
/* jge32 $dstle,$imm32,$disp16 */
{
BPF_INSN_JGE32ILE, "jge32ile", "jge32", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
},
/* jge32 $dstle,$srcle,$disp16 */
{
BPF_INSN_JGE32RLE, "jge32rle", "jge32", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
},
/* jlt $dstle,$imm32,$disp16 */
{
BPF_INSN_JLTILE, "jltile", "jlt", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
},
/* jlt $dstle,$srcle,$disp16 */
{
BPF_INSN_JLTRLE, "jltrle", "jlt", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
},
/* jlt32 $dstle,$imm32,$disp16 */
{
BPF_INSN_JLT32ILE, "jlt32ile", "jlt32", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
},
/* jlt32 $dstle,$srcle,$disp16 */
{
BPF_INSN_JLT32RLE, "jlt32rle", "jlt32", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
},
/* jle $dstle,$imm32,$disp16 */
{
BPF_INSN_JLEILE, "jleile", "jle", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
},
/* jle $dstle,$srcle,$disp16 */
{
BPF_INSN_JLERLE, "jlerle", "jle", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
},
/* jle32 $dstle,$imm32,$disp16 */
{
BPF_INSN_JLE32ILE, "jle32ile", "jle32", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
},
/* jle32 $dstle,$srcle,$disp16 */
{
BPF_INSN_JLE32RLE, "jle32rle", "jle32", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
},
/* jset $dstle,$imm32,$disp16 */
{
BPF_INSN_JSETILE, "jsetile", "jset", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
},
/* jset $dstle,$srcle,$disp16 */
{
BPF_INSN_JSETRLE, "jsetrle", "jset", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
},
/* jset32 $dstle,$imm32,$disp16 */
{
BPF_INSN_JSET32ILE, "jset32ile", "jset32", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
},
/* jset32 $dstle,$srcle,$disp16 */
{
BPF_INSN_JSET32RLE, "jset32rle", "jset32", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
},
/* jne $dstle,$imm32,$disp16 */
{
BPF_INSN_JNEILE, "jneile", "jne", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
},
/* jne $dstle,$srcle,$disp16 */
{
BPF_INSN_JNERLE, "jnerle", "jne", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
},
/* jne32 $dstle,$imm32,$disp16 */
{
BPF_INSN_JNE32ILE, "jne32ile", "jne32", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
},
/* jne32 $dstle,$srcle,$disp16 */
{
BPF_INSN_JNE32RLE, "jne32rle", "jne32", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
},
/* jsgt $dstle,$imm32,$disp16 */
{
BPF_INSN_JSGTILE, "jsgtile", "jsgt", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
},
/* jsgt $dstle,$srcle,$disp16 */
{
BPF_INSN_JSGTRLE, "jsgtrle", "jsgt", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
},
/* jsgt32 $dstle,$imm32,$disp16 */
{
BPF_INSN_JSGT32ILE, "jsgt32ile", "jsgt32", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
},
/* jsgt32 $dstle,$srcle,$disp16 */
{
BPF_INSN_JSGT32RLE, "jsgt32rle", "jsgt32", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
},
/* jsge $dstle,$imm32,$disp16 */
{
BPF_INSN_JSGEILE, "jsgeile", "jsge", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
},
/* jsge $dstle,$srcle,$disp16 */
{
BPF_INSN_JSGERLE, "jsgerle", "jsge", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
},
/* jsge32 $dstle,$imm32,$disp16 */
{
BPF_INSN_JSGE32ILE, "jsge32ile", "jsge32", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
},
/* jsge32 $dstle,$srcle,$disp16 */
{
BPF_INSN_JSGE32RLE, "jsge32rle", "jsge32", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
},
/* jslt $dstle,$imm32,$disp16 */
{
BPF_INSN_JSLTILE, "jsltile", "jslt", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
},
/* jslt $dstle,$srcle,$disp16 */
{
BPF_INSN_JSLTRLE, "jsltrle", "jslt", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
},
/* jslt32 $dstle,$imm32,$disp16 */
{
BPF_INSN_JSLT32ILE, "jslt32ile", "jslt32", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
},
/* jslt32 $dstle,$srcle,$disp16 */
{
BPF_INSN_JSLT32RLE, "jslt32rle", "jslt32", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
},
/* jsle $dstle,$imm32,$disp16 */
{
BPF_INSN_JSLEILE, "jsleile", "jsle", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
},
/* jsle $dstle,$srcle,$disp16 */
{
BPF_INSN_JSLERLE, "jslerle", "jsle", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
},
/* jsle32 $dstle,$imm32,$disp16 */
{
BPF_INSN_JSLE32ILE, "jsle32ile", "jsle32", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
},
/* jsle32 $dstle,$srcle,$disp16 */
{
BPF_INSN_JSLE32RLE, "jsle32rle", "jsle32", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
},
/* jeq $dstbe,$imm32,$disp16 */
{
BPF_INSN_JEQIBE, "jeqibe", "jeq", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
},
/* jeq $dstbe,$srcbe,$disp16 */
{
BPF_INSN_JEQRBE, "jeqrbe", "jeq", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
},
/* jeq32 $dstbe,$imm32,$disp16 */
{
BPF_INSN_JEQ32IBE, "jeq32ibe", "jeq32", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
},
/* jeq32 $dstbe,$srcbe,$disp16 */
{
BPF_INSN_JEQ32RBE, "jeq32rbe", "jeq32", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
},
/* jgt $dstbe,$imm32,$disp16 */
{
BPF_INSN_JGTIBE, "jgtibe", "jgt", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
},
/* jgt $dstbe,$srcbe,$disp16 */
{
BPF_INSN_JGTRBE, "jgtrbe", "jgt", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
},
/* jgt32 $dstbe,$imm32,$disp16 */
{
BPF_INSN_JGT32IBE, "jgt32ibe", "jgt32", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
},
/* jgt32 $dstbe,$srcbe,$disp16 */
{
BPF_INSN_JGT32RBE, "jgt32rbe", "jgt32", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
},
/* jge $dstbe,$imm32,$disp16 */
{
BPF_INSN_JGEIBE, "jgeibe", "jge", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
},
/* jge $dstbe,$srcbe,$disp16 */
{
BPF_INSN_JGERBE, "jgerbe", "jge", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
},
/* jge32 $dstbe,$imm32,$disp16 */
{
BPF_INSN_JGE32IBE, "jge32ibe", "jge32", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
},
/* jge32 $dstbe,$srcbe,$disp16 */
{
BPF_INSN_JGE32RBE, "jge32rbe", "jge32", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
},
/* jlt $dstbe,$imm32,$disp16 */
{
BPF_INSN_JLTIBE, "jltibe", "jlt", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
},
/* jlt $dstbe,$srcbe,$disp16 */
{
BPF_INSN_JLTRBE, "jltrbe", "jlt", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
},
/* jlt32 $dstbe,$imm32,$disp16 */
{
BPF_INSN_JLT32IBE, "jlt32ibe", "jlt32", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
},
/* jlt32 $dstbe,$srcbe,$disp16 */
{
BPF_INSN_JLT32RBE, "jlt32rbe", "jlt32", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
},
/* jle $dstbe,$imm32,$disp16 */
{
BPF_INSN_JLEIBE, "jleibe", "jle", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
},
/* jle $dstbe,$srcbe,$disp16 */
{
BPF_INSN_JLERBE, "jlerbe", "jle", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
},
/* jle32 $dstbe,$imm32,$disp16 */
{
BPF_INSN_JLE32IBE, "jle32ibe", "jle32", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
},
/* jle32 $dstbe,$srcbe,$disp16 */
{
BPF_INSN_JLE32RBE, "jle32rbe", "jle32", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
},
/* jset $dstbe,$imm32,$disp16 */
{
BPF_INSN_JSETIBE, "jsetibe", "jset", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
},
/* jset $dstbe,$srcbe,$disp16 */
{
BPF_INSN_JSETRBE, "jsetrbe", "jset", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
},
/* jset32 $dstbe,$imm32,$disp16 */
{
BPF_INSN_JSET32IBE, "jset32ibe", "jset32", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
},
/* jset32 $dstbe,$srcbe,$disp16 */
{
BPF_INSN_JSET32RBE, "jset32rbe", "jset32", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
},
/* jne $dstbe,$imm32,$disp16 */
{
BPF_INSN_JNEIBE, "jneibe", "jne", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
},
/* jne $dstbe,$srcbe,$disp16 */
{
BPF_INSN_JNERBE, "jnerbe", "jne", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
},
/* jne32 $dstbe,$imm32,$disp16 */
{
BPF_INSN_JNE32IBE, "jne32ibe", "jne32", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
},
/* jne32 $dstbe,$srcbe,$disp16 */
{
BPF_INSN_JNE32RBE, "jne32rbe", "jne32", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
},
/* jsgt $dstbe,$imm32,$disp16 */
{
BPF_INSN_JSGTIBE, "jsgtibe", "jsgt", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
},
/* jsgt $dstbe,$srcbe,$disp16 */
{
BPF_INSN_JSGTRBE, "jsgtrbe", "jsgt", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
},
/* jsgt32 $dstbe,$imm32,$disp16 */
{
BPF_INSN_JSGT32IBE, "jsgt32ibe", "jsgt32", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
},
/* jsgt32 $dstbe,$srcbe,$disp16 */
{
BPF_INSN_JSGT32RBE, "jsgt32rbe", "jsgt32", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
},
/* jsge $dstbe,$imm32,$disp16 */
{
BPF_INSN_JSGEIBE, "jsgeibe", "jsge", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
},
/* jsge $dstbe,$srcbe,$disp16 */
{
BPF_INSN_JSGERBE, "jsgerbe", "jsge", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
},
/* jsge32 $dstbe,$imm32,$disp16 */
{
BPF_INSN_JSGE32IBE, "jsge32ibe", "jsge32", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
},
/* jsge32 $dstbe,$srcbe,$disp16 */
{
BPF_INSN_JSGE32RBE, "jsge32rbe", "jsge32", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
},
/* jslt $dstbe,$imm32,$disp16 */
{
BPF_INSN_JSLTIBE, "jsltibe", "jslt", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
},
/* jslt $dstbe,$srcbe,$disp16 */
{
BPF_INSN_JSLTRBE, "jsltrbe", "jslt", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
},
/* jslt32 $dstbe,$imm32,$disp16 */
{
BPF_INSN_JSLT32IBE, "jslt32ibe", "jslt32", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
},
/* jslt32 $dstbe,$srcbe,$disp16 */
{
BPF_INSN_JSLT32RBE, "jslt32rbe", "jslt32", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
},
/* jsle $dstbe,$imm32,$disp16 */
{
BPF_INSN_JSLEIBE, "jsleibe", "jsle", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
},
/* jsle $dstbe,$srcbe,$disp16 */
{
BPF_INSN_JSLERBE, "jslerbe", "jsle", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
},
/* jsle32 $dstbe,$imm32,$disp16 */
{
BPF_INSN_JSLE32IBE, "jsle32ibe", "jsle32", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
},
/* jsle32 $dstbe,$srcbe,$disp16 */
{
BPF_INSN_JSLE32RBE, "jsle32rbe", "jsle32", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
},
-/* ja $disp16 */
+/* call $disp32 */
{
- BPF_INSN_JA, "ja", "ja", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }
+ BPF_INSN_CALLLE, "callle", "call", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } }
},
/* call $disp32 */
{
- BPF_INSN_CALL, "call", "call", 64,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }
+ BPF_INSN_CALLBE, "callbe", "call", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
+ },
+/* ja $disp16 */
+ {
+ BPF_INSN_JA, "ja", "ja", 64,
+ { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }
},
/* exit */
{
@@ -1479,6 +1484,11 @@ static const CGEN_IBASE bpf_cgen_insn_table[MAX_INSNS] =
BPF_INSN_XADDWBE, "xaddwbe", "xaddw", 64,
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x40" } } } }
},
+/* brkpt */
+ {
+ BPF_INSN_BRKPT, "brkpt", "brkpt", 64,
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } } } }
+ },
};
#undef OP
@@ -1821,10 +1831,18 @@ bpf_cgen_cpu_close (CGEN_CPU_DESC cd)
regfree (CGEN_INSN_RX (insns));
}
- free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
- free ((CGEN_INSN *) cd->insn_table.init_entries);
- free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
- free ((CGEN_HW_ENTRY *) cd->operand_table.entries);
+ if (cd->macro_insn_table.init_entries)
+ free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
+
+ if (cd->insn_table.init_entries)
+ free ((CGEN_INSN *) cd->insn_table.init_entries);
+
+ if (cd->hw_table.entries)
+ free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
+
+ if (cd->operand_table.entries)
+ free ((CGEN_HW_ENTRY *) cd->operand_table.entries);
+
free (cd);
}
diff --git a/opcodes/bpf-dis.c b/opcodes/bpf-dis.c
index 5d0d08b..60e0d96 100644
--- a/opcodes/bpf-dis.c
+++ b/opcodes/bpf-dis.c
@@ -75,6 +75,7 @@ bpf_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
info->bytes_per_chunk = 1;
info->bytes_per_line = 8;
+ info->endian_code = BFD_ENDIAN_BIG;
/* Attempt to read the base part of the insn. */
buflen = cd->base_insn_bitsize / 8;
diff --git a/opcodes/bpf-opc.c b/opcodes/bpf-opc.c
index a64da68..3ecd35d 100644
--- a/opcodes/bpf-opc.c
+++ b/opcodes/bpf-opc.c
@@ -133,11 +133,11 @@ static const CGEN_IFMT ifmt_jeqrbe ATTRIBUTE_UNUSED = {
8, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_DSTBE) }, { F (F_OP_CODE) }, { F (F_SRCBE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
};
-static const CGEN_IFMT ifmt_ja ATTRIBUTE_UNUSED = {
+static const CGEN_IFMT ifmt_callle ATTRIBUTE_UNUSED = {
8, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_REGS) }, { F (F_OP_CODE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
};
-static const CGEN_IFMT ifmt_call ATTRIBUTE_UNUSED = {
+static const CGEN_IFMT ifmt_ja ATTRIBUTE_UNUSED = {
8, 64, 0xff, { { F (F_IMM32) }, { F (F_OFFSET16) }, { F (F_REGS) }, { F (F_OP_CODE) }, { F (F_OP_SRC) }, { F (F_OP_CLASS) }, { 0 } }
};
@@ -400,30 +400,6 @@ static const CGEN_OPCODE bpf_cgen_insn_opcode_table[MAX_INSNS] =
{ { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },
& ifmt_addrle, { 0xac }
},
-/* mov $dstle,$imm32 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },
- & ifmt_addile, { 0xb7 }
- },
-/* mov $dstle,$srcle */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },
- & ifmt_addrle, { 0xbf }
- },
-/* mov32 $dstle,$imm32 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },
- & ifmt_addile, { 0xb4 }
- },
-/* mov32 $dstle,$srcle */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },
- & ifmt_addrle, { 0xbc }
- },
/* arsh $dstle,$imm32 */
{
{ 0, 0, 0, 0 },
@@ -460,6 +436,30 @@ static const CGEN_OPCODE bpf_cgen_insn_opcode_table[MAX_INSNS] =
{ { MNEM, ' ', OP (DSTLE), 0 } },
& ifmt_negle, { 0x84 }
},
+/* mov $dstle,$imm32 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },
+ & ifmt_addile, { 0xb7 }
+ },
+/* mov $dstle,$srcle */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },
+ & ifmt_addrle, { 0xbf }
+ },
+/* mov32 $dstle,$imm32 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), ',', OP (IMM32), 0 } },
+ & ifmt_addile, { 0xb4 }
+ },
+/* mov32 $dstle,$srcle */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTLE), ',', OP (SRCLE), 0 } },
+ & ifmt_addrle, { 0xbc }
+ },
/* add $dstbe,$imm32 */
{
{ 0, 0, 0, 0 },
@@ -700,30 +700,6 @@ static const CGEN_OPCODE bpf_cgen_insn_opcode_table[MAX_INSNS] =
{ { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },
& ifmt_addrbe, { 0xac }
},
-/* mov $dstbe,$imm32 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },
- & ifmt_addibe, { 0xb7 }
- },
-/* mov $dstbe,$srcbe */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },
- & ifmt_addrbe, { 0xbf }
- },
-/* mov32 $dstbe,$imm32 */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },
- & ifmt_addibe, { 0xb4 }
- },
-/* mov32 $dstbe,$srcbe */
- {
- { 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },
- & ifmt_addrbe, { 0xbc }
- },
/* arsh $dstbe,$imm32 */
{
{ 0, 0, 0, 0 },
@@ -760,6 +736,30 @@ static const CGEN_OPCODE bpf_cgen_insn_opcode_table[MAX_INSNS] =
{ { MNEM, ' ', OP (DSTBE), 0 } },
& ifmt_negbe, { 0x84 }
},
+/* mov $dstbe,$imm32 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },
+ & ifmt_addibe, { 0xb7 }
+ },
+/* mov $dstbe,$srcbe */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },
+ & ifmt_addrbe, { 0xbf }
+ },
+/* mov32 $dstbe,$imm32 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), ',', OP (IMM32), 0 } },
+ & ifmt_addibe, { 0xb4 }
+ },
+/* mov32 $dstbe,$srcbe */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), 0 } },
+ & ifmt_addrbe, { 0xbc }
+ },
/* endle $dstle,$endsize */
{
{ 0, 0, 0, 0 },
@@ -1540,17 +1540,23 @@ static const CGEN_OPCODE bpf_cgen_insn_opcode_table[MAX_INSNS] =
{ { MNEM, ' ', OP (DSTBE), ',', OP (SRCBE), ',', OP (DISP16), 0 } },
& ifmt_jeqrbe, { 0xde }
},
-/* ja $disp16 */
+/* call $disp32 */
{
{ 0, 0, 0, 0 },
- { { MNEM, ' ', OP (DISP16), 0 } },
- & ifmt_ja, { 0x5 }
+ { { MNEM, ' ', OP (DISP32), 0 } },
+ & ifmt_callle, { 0x85 }
},
/* call $disp32 */
{
{ 0, 0, 0, 0 },
{ { MNEM, ' ', OP (DISP32), 0 } },
- & ifmt_call, { 0x85 }
+ & ifmt_callle, { 0x85 }
+ },
+/* ja $disp16 */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, ' ', OP (DISP16), 0 } },
+ & ifmt_ja, { 0x5 }
},
/* exit */
{
@@ -1582,6 +1588,12 @@ static const CGEN_OPCODE bpf_cgen_insn_opcode_table[MAX_INSNS] =
{ { MNEM, ' ', '[', OP (DSTBE), '+', OP (OFFSET16), ']', ',', OP (SRCBE), 0 } },
& ifmt_ldxwbe, { 0xc3 }
},
+/* brkpt */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, 0 } },
+ & ifmt_exit, { 0x8c }
+ },
};
#undef A
diff --git a/opcodes/bpf-opc.h b/opcodes/bpf-opc.h
index 2dedae4..ec0c2d3 100644
--- a/opcodes/bpf-opc.h
+++ b/opcodes/bpf-opc.h
@@ -58,9 +58,9 @@ typedef enum cgen_insn_type {
, BPF_INSN_LSH32RLE, BPF_INSN_RSHILE, BPF_INSN_RSHRLE, BPF_INSN_RSH32ILE
, BPF_INSN_RSH32RLE, BPF_INSN_MODILE, BPF_INSN_MODRLE, BPF_INSN_MOD32ILE
, BPF_INSN_MOD32RLE, BPF_INSN_XORILE, BPF_INSN_XORRLE, BPF_INSN_XOR32ILE
- , BPF_INSN_XOR32RLE, BPF_INSN_MOVILE, BPF_INSN_MOVRLE, BPF_INSN_MOV32ILE
- , BPF_INSN_MOV32RLE, BPF_INSN_ARSHILE, BPF_INSN_ARSHRLE, BPF_INSN_ARSH32ILE
- , BPF_INSN_ARSH32RLE, BPF_INSN_NEGLE, BPF_INSN_NEG32LE, BPF_INSN_ADDIBE
+ , BPF_INSN_XOR32RLE, BPF_INSN_ARSHILE, BPF_INSN_ARSHRLE, BPF_INSN_ARSH32ILE
+ , BPF_INSN_ARSH32RLE, BPF_INSN_NEGLE, BPF_INSN_NEG32LE, BPF_INSN_MOVILE
+ , BPF_INSN_MOVRLE, BPF_INSN_MOV32ILE, BPF_INSN_MOV32RLE, BPF_INSN_ADDIBE
, BPF_INSN_ADDRBE, BPF_INSN_ADD32IBE, BPF_INSN_ADD32RBE, BPF_INSN_SUBIBE
, BPF_INSN_SUBRBE, BPF_INSN_SUB32IBE, BPF_INSN_SUB32RBE, BPF_INSN_MULIBE
, BPF_INSN_MULRBE, BPF_INSN_MUL32IBE, BPF_INSN_MUL32RBE, BPF_INSN_DIVIBE
@@ -70,10 +70,10 @@ typedef enum cgen_insn_type {
, BPF_INSN_LSHRBE, BPF_INSN_LSH32IBE, BPF_INSN_LSH32RBE, BPF_INSN_RSHIBE
, BPF_INSN_RSHRBE, BPF_INSN_RSH32IBE, BPF_INSN_RSH32RBE, BPF_INSN_MODIBE
, BPF_INSN_MODRBE, BPF_INSN_MOD32IBE, BPF_INSN_MOD32RBE, BPF_INSN_XORIBE
- , BPF_INSN_XORRBE, BPF_INSN_XOR32IBE, BPF_INSN_XOR32RBE, BPF_INSN_MOVIBE
- , BPF_INSN_MOVRBE, BPF_INSN_MOV32IBE, BPF_INSN_MOV32RBE, BPF_INSN_ARSHIBE
+ , BPF_INSN_XORRBE, BPF_INSN_XOR32IBE, BPF_INSN_XOR32RBE, BPF_INSN_ARSHIBE
, BPF_INSN_ARSHRBE, BPF_INSN_ARSH32IBE, BPF_INSN_ARSH32RBE, BPF_INSN_NEGBE
- , BPF_INSN_NEG32BE, BPF_INSN_ENDLELE, BPF_INSN_ENDBELE, BPF_INSN_ENDLEBE
+ , BPF_INSN_NEG32BE, BPF_INSN_MOVIBE, BPF_INSN_MOVRBE, BPF_INSN_MOV32IBE
+ , BPF_INSN_MOV32RBE, BPF_INSN_ENDLELE, BPF_INSN_ENDBELE, BPF_INSN_ENDLEBE
, BPF_INSN_ENDBEBE, BPF_INSN_LDDWLE, BPF_INSN_LDDWBE, BPF_INSN_LDABSW
, BPF_INSN_LDABSH, BPF_INSN_LDABSB, BPF_INSN_LDABSDW, BPF_INSN_LDINDWLE
, BPF_INSN_LDINDHLE, BPF_INSN_LDINDBLE, BPF_INSN_LDINDDWLE, BPF_INSN_LDINDWBE
@@ -105,16 +105,16 @@ typedef enum cgen_insn_type {
, BPF_INSN_JSGTRBE, BPF_INSN_JSGT32IBE, BPF_INSN_JSGT32RBE, BPF_INSN_JSGEIBE
, BPF_INSN_JSGERBE, BPF_INSN_JSGE32IBE, BPF_INSN_JSGE32RBE, BPF_INSN_JSLTIBE
, BPF_INSN_JSLTRBE, BPF_INSN_JSLT32IBE, BPF_INSN_JSLT32RBE, BPF_INSN_JSLEIBE
- , BPF_INSN_JSLERBE, BPF_INSN_JSLE32IBE, BPF_INSN_JSLE32RBE, BPF_INSN_JA
- , BPF_INSN_CALL, BPF_INSN_EXIT, BPF_INSN_XADDDWLE, BPF_INSN_XADDWLE
- , BPF_INSN_XADDDWBE, BPF_INSN_XADDWBE
+ , BPF_INSN_JSLERBE, BPF_INSN_JSLE32IBE, BPF_INSN_JSLE32RBE, BPF_INSN_CALLLE
+ , BPF_INSN_CALLBE, BPF_INSN_JA, BPF_INSN_EXIT, BPF_INSN_XADDDWLE
+ , BPF_INSN_XADDWLE, BPF_INSN_XADDDWBE, BPF_INSN_XADDWBE, BPF_INSN_BRKPT
} CGEN_INSN_TYPE;
/* Index of `invalid' insn place holder. */
#define CGEN_INSN_INVALID BPF_INSN_INVALID
/* Total number of insns in table. */
-#define MAX_INSNS ((int) BPF_INSN_XADDWBE + 1)
+#define MAX_INSNS ((int) BPF_INSN_BRKPT + 1)
/* This struct records data prior to insertion or after extraction. */
struct cgen_fields
generated by cgit v1.1 at 2024-09-08 07:36:47 +0000