diff options
| -rw-r--r-- | sim/common/ChangeLog | 7 | ||||
| -rw-r--r-- | sim/common/sim-trace.c | 45 | ||||
| -rw-r--r-- | sim/common/sim-trace.h | 16 | ||||
| -rw-r--r-- | sim/igen/ChangeLog | 11 | ||||
| -rw-r--r-- | sim/igen/igen.c | 6 | ||||
| -rw-r--r-- | sim/tic80/.Sanitize | 1 | ||||
| -rw-r--r-- | sim/tic80/ChangeLog | 29 | ||||
| -rw-r--r-- | sim/tic80/Makefile.in | 4 | ||||
| -rw-r--r-- | sim/tic80/alu.h | 2 | ||||
| -rw-r--r-- | sim/tic80/cpu.h | 165 | ||||
| -rw-r--r-- | sim/tic80/insns | 480 | ||||
| -rw-r--r-- | sim/tic80/interp.c | 208 | ||||
| -rw-r--r-- | sim/tic80/misc.c | 412 | ||||
| -rw-r--r-- | sim/tic80/sim-calls.c | 1 | ||||
| -rw-r--r-- | sim/tic80/sim-main.h | 2 |
15 files changed, 928 insertions, 461 deletions
diff --git a/sim/common/ChangeLog b/sim/common/ChangeLog index 6ef6147..4363d41 100644 --- a/sim/common/ChangeLog +++ b/sim/common/ChangeLog @@ -1,3 +1,10 @@ +Wed May 7 15:19:58 1997 Andrew Cagney <cagney@b1.cygnus.com> + + * sim-trace.c (trace_one_insn): Make a va-args function. + + * sim-trace.c (trace_vprintf): New function, va-arg version of + trace_printf. + Tue May 6 16:38:16 1997 Doug Evans <dje@canuck.cygnus.com> * sim-trace.c (trace_uninstall): Don't close a file twice. diff --git a/sim/common/sim-trace.c b/sim/common/sim-trace.c index a2eec25..f617783 100644 --- a/sim/common/sim-trace.c +++ b/sim/common/sim-trace.c @@ -308,21 +308,27 @@ trace_uninstall (SIM_DESC sd) void trace_one_insn (SIM_DESC sd, sim_cpu *cpu, address_word pc, int line_p, const char *filename, int linenum, - const char *phase_wo_colon, const char *name) + const char *phase_wo_colon, const char *fmt, + ...) { + va_list ap; char phase[SIZE_PHASE+2]; strncpy (phase, phase_wo_colon, SIZE_PHASE); strcat (phase, ":"); if (!line_p) - trace_printf(sd, cpu, "%-*s %s:%-*d 0x%.*lx %s\n", - SIZE_PHASE+1, phase, - filename, - SIZE_LINE_NUMBER, linenum, - SIZE_PC, (long)pc, - name); - + { + trace_printf (sd, cpu, "%-*s %s:%-*d 0x%.*lx ", + SIZE_PHASE+1, phase, + filename, + SIZE_LINE_NUMBER, linenum, + SIZE_PC, (long)pc); + va_start (ap, fmt); + trace_vprintf (sd, cpu, fmt, ap); + va_end (ap); + trace_printf (sd, cpu, "\n"); + } else { char buf[256]; @@ -371,15 +377,27 @@ trace_one_insn (SIM_DESC sd, sim_cpu *cpu, address_word pc, } } - trace_printf (sd, cpu, "%-*s 0x%.*x %-*.*s %s\n", + trace_printf (sd, cpu, "%-*s 0x%.*x %-*.*s ", SIZE_PHASE+1, phase, SIZE_PC, (unsigned) pc, - SIZE_LOCATION, SIZE_LOCATION, buf, - name); + SIZE_LOCATION, SIZE_LOCATION, buf); + va_start (ap, fmt); + trace_vprintf (sd, cpu, fmt, ap); + va_end (ap); + trace_printf (sd, cpu, "\n"); } } void +trace_vprintf (SIM_DESC sd, sim_cpu *cpu, const char *fmt, va_list ap) +{ + if (cpu != NULL && TRACE_FILE (CPU_TRACE_DATA (cpu)) != NULL) + vfprintf (TRACE_FILE (CPU_TRACE_DATA (cpu)), fmt, ap); + else + sim_io_evprintf (sd, fmt, ap); +} + +void trace_printf VPARAMS ((SIM_DESC sd, sim_cpu *cpu, const char *fmt, ...)) { #ifndef __STDC__ @@ -396,10 +414,7 @@ trace_printf VPARAMS ((SIM_DESC sd, sim_cpu *cpu, const char *fmt, ...)) fmt = va_arg (ap, const char *); #endif - if (cpu != NULL && TRACE_FILE (CPU_TRACE_DATA (cpu)) != NULL) - vfprintf (TRACE_FILE (CPU_TRACE_DATA (cpu)), fmt, ap); - else - sim_io_evprintf (sd, fmt, ap); + trace_vprintf (sd, cpu, fmt, ap); va_end (ap); } diff --git a/sim/common/sim-trace.h b/sim/common/sim-trace.h index e1cb786..a22da63 100644 --- a/sim/common/sim-trace.h +++ b/sim/common/sim-trace.h @@ -121,14 +121,22 @@ struct _sim_cpu; #define TRACE_FPU_P(cpu) TRACE_P (cpu, TRACE_FPU_IDX) #define TRACE_BRANCH_P(cpu) TRACE_P (cpu, TRACE_BRANCH_IDX) -extern void trace_one_insn PARAMS ((SIM_DESC, sim_cpu *, - address_word, int, - const char *, int, - const char *, const char *)); +extern void trace_one_insn PARAMS ((SIM_DESC sd, + sim_cpu * cpu, + address_word cia, + int print_linenum_p, + const char *file_name, + int line_nr, + const char *unit, + const char *fmt, + ...)) + __attribute__((format (printf, 8, 9))); extern void trace_printf PARAMS ((SIM_DESC, sim_cpu *, const char *, ...)) __attribute__((format (printf, 3, 4))); +extern void trace_vprintf PARAMS ((SIM_DESC, sim_cpu *, const char *, va_list)); + /* Debug support. This is included here because there isn't enough of it to justify a sim-debug.h. */ diff --git a/sim/igen/ChangeLog b/sim/igen/ChangeLog index 6a10b35..df837dc 100644 --- a/sim/igen/ChangeLog +++ b/sim/igen/ChangeLog @@ -1,3 +1,14 @@ +Wed May 7 12:31:30 1997 Andrew Cagney <cagney@b1.cygnus.com> + + * igen.c (print_itrace): Fix so line-nr is passed to trace + function. + + * gen-idecode.c (print_idecode_validate): Correct FP code. + + * gen-support.c (gen_support_h): Always pass MY_INDEX to support + functions. + (print_support_function_name): Ditto. + Tue May 6 06:12:04 1997 Mike Meissner <meissner@cygnus.com> * igen.c (print_itrace): Call trace_one_insn to trace diff --git a/sim/igen/igen.c b/sim/igen/igen.c index 605e1f9..a8475ed 100644 --- a/sim/igen/igen.c +++ b/sim/igen/igen.c @@ -258,9 +258,9 @@ print_itrace(lf *file, lf_printf(file, " trace_one_insn (SD, CPU, %s, TRACE_LINENUM_P (CPU),\n", (code & generate_with_semantic_delayed_branch) ? "cia.ip" : "cia"); - lf_printf(file, " itable[MY_INDEX].file, MY_INDEX, \"%s\",\n", phase_lc); - lf_printf(file, " itable[MY_INDEX].name);\n"); - + lf_printf(file, " itable[MY_INDEX].file, itable[MY_INDEX].line_nr,\n"); + lf_printf(file, " \"%s\", itable[MY_INDEX].name);\n", phase_lc); + lf_printf(file, "}\n"); lf_indent_suppress(file); lf_printf(file, "#endif\n"); diff --git a/sim/tic80/.Sanitize b/sim/tic80/.Sanitize index 8039fb3..1424fbf 100644 --- a/sim/tic80/.Sanitize +++ b/sim/tic80/.Sanitize @@ -34,6 +34,7 @@ dc ic insns interp.c +misc.c sim-calls.c sim-main.h diff --git a/sim/tic80/ChangeLog b/sim/tic80/ChangeLog index fa14ec9..60761ce 100644 --- a/sim/tic80/ChangeLog +++ b/sim/tic80/ChangeLog @@ -1,3 +1,32 @@ +Wed May 7 11:48:55 1997 Andrew Cagney <cagney@b1.cygnus.com> + + * cpu.h (TRACE_FPU2, TRACE_FPU3, TRACE_FPU2I): Add. + * insn: Clean up fpu tracing. + + * sim-calls.c (sim_create_inferior): Start out with interrupts + enabled. + + * cpu.h (TRACE_SINK3), misc.c (tic80_trace_sink3): Three argument + sink + + * insns (rdcr, swcr, wrcr, brcr, rmo, lmo): Implement. + + * insns (do_*): Remove MY_INDEX/indx argument from support functions, + igen now handles this. + + * cpu.h (CR): New macro - access TIc80 control registers. + + * misc.c: New file. + (tic80_cr2index): New function, map control register opcode index + into the internal CR enum. + + * interp.c + (tic80_trace_{alu{2,3},nop,sink{1,2},{,u}cond_br,ldst}): Move from + here + * misc.c: to here. + + * Makefile.in (SIM_OBJS): Add misc.o. + Tue May 6 15:22:58 1997 Mike Meissner <meissner@cygnus.com> * cpu.h ({,v}{S,D}P_FPR): Delete unused macros that won't work on diff --git a/sim/tic80/Makefile.in b/sim/tic80/Makefile.in index 21be037..eb3f943 100644 --- a/sim/tic80/Makefile.in +++ b/sim/tic80/Makefile.in @@ -11,7 +11,7 @@ # List of object files, less common parts. SIM_OBJS = sim-endian.o sim-bits.o sim-config.o interp.o \ - support.o idecode.o semantics.o itable.o \ + support.o idecode.o semantics.o itable.o misc.o \ sim-calls.o \ sim-events.o \ sim-core.o \ @@ -89,6 +89,7 @@ clean-igen: tmp-igen: $(srcdir)/dc $(srcdir)/insns $(srcdir)/ic ../igen/igen cd ../igen && $(MAKE) ../igen/igen \ + -F f \ -G direct-access \ -G delayed-branch \ -F short,emul \ @@ -146,3 +147,4 @@ support.o: $(ENGINE_H) interp.o: interp.c $(ENGINE_H) sim-calls.o: sim-calls.c $(ENGINE_H) cpu.o: cpu.c $(ENGINE_H) +misc.o: $(ENGINE_H)
\ No newline at end of file diff --git a/sim/tic80/alu.h b/sim/tic80/alu.h index d8fb136..1bb4054 100644 --- a/sim/tic80/alu.h +++ b/sim/tic80/alu.h @@ -63,6 +63,8 @@ do { \ /* Floating point support */ +#define IS_FP_AVAILABLE ((CPU)->cr[IE_CR] & IE_CR_IE) + #include "sim-fpu.h" diff --git a/sim/tic80/cpu.h b/sim/tic80/cpu.h index 4ada294..3a4b042 100644 --- a/sim/tic80/cpu.h +++ b/sim/tic80/cpu.h @@ -20,22 +20,156 @@ with this program; if not, write to the Free Software Foundation, Inc., +/* TI C80 control registers */ + +typedef enum { + EPC_CR, + EIP_CR, + CONFIG_CR, + INTPEN_CR, + IE_CR, + FPST_CR, + PPERROR_CR, + PKTREQ_CR, + TCOUNT_CR, + TSCALE_CR, + FLTOP_CR, + FLTADR_CR, + FLTTAG_CR, + FLTDLT_CR, + FLTDTH_CR, + FLT005_CR, + FLT006_CR, + FLT007_CR, + FLT008_CR, + FLT009_CR, + FLT010_CR, + FLT011_CR, + FLT012_CR, + FLT013_CR, + FLT014_CR, + FLT015_CR, + SYSSTK_CR, + SYSTMP_CR, + MPC_CR, + MIP_CR, + ECOMCNTL_CR, + ANASTAT_CR, + BRK1_CR, + BRK2_CR, + ITAG0_CR, + ITAG1_CR, + ITAG2_CR, + ITAG3_CR, + ITAG4_CR, + ITAG5_CR, + ITAG6_CR, + ITAG7_CR, + ITAG8_CR, + ITAG9_CR, + ITAG10_CR, + ITAG11_CR, + ITAG12_CR, + ITAG13_CR, + ITAG14_CR, + ITAG15_CR, + ILRU_CR, + DTAG0_CR, + DTAG1_CR, + DTAG2_CR, + DTAG3_CR, + DTAG4_CR, + DTAG5_CR, + DTAG6_CR, + DTAG7_CR, + DTAG8_CR, + DTAG9_CR, + DTAG10_CR, + DTAG11_CR, + DTAG12_CR, + DTAG13_CR, + DTAG14_CR, + DTAG15_CR, + DLRU_CR, + IN0P_CR, + IN1P_CR, + OUTP_CR, + SCRATCH_CR, + nr_tic80_control_regs, +} tic80_control_regs; + +/* extern int tic80_cr2index (tic80_control_regs reg); */ + +/* Map an instruction CR index onto the corresponding internal cr enum + or SCRATCH_CR if the index is invalid */ + +extern tic80_control_regs tic80_index2cr (int index); + + +/* TIc80 interrupt register bits */ + +enum { + IE_CR_PE = BIT32(31), + IE_CR_X4 = BIT32(30), + IE_CR_X3 = BIT32(29), + IE_CR_BP = BIT32(28), + IE_CR_PB = BIT32(27), + IE_CR_PC = BIT32(26), + IE_CR_MI = BIT32(25), + /**/ + IE_CR_P3 = BIT32(19), + IE_CR_P2 = BIT32(18), + IE_CR_P1 = BIT32(17), + IE_CR_P0 = BIT32(16), + IE_CR_IO = BIT32(15), + IE_CR_MF = BIT32(14), + /**/ + IE_CR_X2 = BIT32(12), + IE_CR_X1 = BIT32(11), + IE_CR_TI = BIT32(10), + IE_CR_F1 = BIT32(9), + IE_CR_F0 = BIT32(8), + IE_CR_FX = BIT32(7), + IE_CR_FU = BIT32(6), + IE_CR_FO = BIT32(5), + /**/ + IE_CR_FZ = BIT32(3), + IE_CR_FI = BIT32(2), + /**/ + IE_CR_IE = BIT32(0), +}; + + + + struct _sim_cpu { unsigned32 reg[32]; unsigned64 acc[4]; + unsigned32 cr[nr_tic80_control_regs]; + int is_user_mode; /* hidden mode latch */ sim_cia cia; sim_cpu_base base; }; #define GPR(N) ((CPU)->reg[N]) #define ACC(N) ((CPU)->acc[N]) +#define CR(N) ((CPU)->cr[tic80_index2cr ((N))]) + + #if defined(WITH_TRACE) extern char *tic80_trace_alu3 PARAMS ((int, unsigned32, unsigned32, unsigned32)); extern char *tic80_trace_alu2 PARAMS ((int, unsigned32, unsigned32)); +extern void tic80_trace_fpu3 PARAMS ((SIM_DESC, sim_cpu *, sim_cia, int, + sim_fpu, sim_fpu, sim_fpu)); +extern void tic80_trace_fpu2 PARAMS ((SIM_DESC, sim_cpu *, sim_cia, int, + sim_fpu, sim_fpu)); +extern void tic80_trace_fpu2i PARAMS ((SIM_DESC, sim_cpu *, sim_cia, int, + unsigned32, sim_fpu, sim_fpu)); extern char *tic80_trace_nop PARAMS ((int)); extern char *tic80_trace_sink1 PARAMS ((int, unsigned32)); extern char *tic80_trace_sink2 PARAMS ((int, unsigned32, unsigned32)); +extern char *tic80_trace_sink3 PARAMS ((int, unsigned32, unsigned32, unsigned32)); extern char *tic80_trace_cond_br PARAMS ((int, int, unsigned32, unsigned32)); extern char *tic80_trace_ucond_br PARAMS ((int, unsigned32)); extern char *tic80_trace_ldst PARAMS ((int, int, int, int, unsigned32, unsigned32, unsigned32)); @@ -58,6 +192,27 @@ do { \ } \ } while (0) +#define TRACE_FPU3(indx, result, input1, input2) \ +do { \ + if (TRACE_FPU_P (CPU)) { \ + tic80_trace_fpu3 (SD, CPU, cia, indx, result, input1, input2); \ + } \ +} while (0) + +#define TRACE_FPU2(indx, result, input) \ +do { \ + if (TRACE_FPU_P (CPU)) { \ + tic80_trace_fpu2 (SD, CPU, cia, indx, result, input); \ + } \ +} while (0) + +#define TRACE_FPU2I(indx, result, input1, input2) \ +do { \ + if (TRACE_FPU_P (CPU)) { \ + tic80_trace_fpu2i (SD, CPU, cia, indx, result, input1, input2); \ + } \ +} while (0) + #define TRACE_NOP(indx) \ do { \ if (TRACE_ALU_P (CPU)) { \ @@ -85,6 +240,15 @@ do { \ } \ } while (0) +#define TRACE_SINK3(indx, input1, input2, input3) \ +do { \ + if (TRACE_ALU_P (CPU)) { \ + trace_one_insn (SD, CPU, cia.ip, 1, itable[indx].file, \ + itable[indx].line_nr, "nop", \ + tic80_trace_sink3 (indx, input1, input2, input3)); \ + } \ +} while (0) + #define TRACE_COND_BR(indx, jump_p, cond, target) \ do { \ if (TRACE_BRANCH_P (CPU)) { \ @@ -129,6 +293,7 @@ do { \ #define TRACE_NOP(indx) #define TRACE_SINK1(indx, input) #define TRACE_SINK2(indx, input1, input2) +#define TRACE_SINK3(indx, input1, input2, input3) #define TRACE_COND_BR(indx, jump_p, cond, target) #define TRACE_UCOND_BR(indx, target) #define TRACE_LD(indx, m, s, result, addr1, addr2) diff --git a/sim/tic80/insns b/sim/tic80/insns index 5ad5d70..437b6c9 100644 --- a/sim/tic80/insns +++ b/sim/tic80/insns @@ -19,90 +19,92 @@ // 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ -// The following is called when ever an illegal instruction is -// encountered +// The following is called when ever an illegal instruction is encountered. ::internal::illegal engine_error (SD, CPU, cia, "illegal instruction at 0x%lx", cia.ip); +// The following is called when ever an FP op is attempted with FPU disabled. +::internal::fp_unavailable + engine_error (SD, CPU, cia, "floating-point unavailable at 0x%lx", cia.ip); // Signed Integer Add - add source1, source2, dest -void::function::do_add:signed32 *rDest, signed32 Source1, signed32 Source2, int indx +void::function::do_add:signed32 *rDest, signed32 Source1, signed32 Source2 ALU_BEGIN (Source1); ALU_ADD (Source2); ALU_END (*rDest); - TRACE_ALU3 (indx, *rDest, Source1, Source2); + TRACE_ALU3 (MY_INDEX, *rDest, Source1, Source2); /* FIXME - a signed add may cause an exception */ 31.Dest,26.Source2,21.0b101100,15.0,14.SignedImmediate::::add i - do_add (_SD, rDest, vSource1, rSource2, MY_INDEX); + do_add (_SD, rDest, vSource1, rSource2); 31.Dest,26.Source2,21.0b11101100,13.0,12.0,11./,4.Source1::::add r - do_add (_SD, rDest, rSource1, rSource2, MY_INDEX); + do_add (_SD, rDest, rSource1, rSource2); 31.Dest,26.Source2,21.0b11101100,13.0,12.1,11./::::add l long_immediate (LongSignedImmediate); - do_add (_SD, rDest, LongSignedImmediate, rSource2, MY_INDEX); + do_add (_SD, rDest, LongSignedImmediate, rSource2); // Unsigned Integer Add - addu source1, source2, dest -void::function::do_addu:unsigned32 *rDest, unsigned32 Source1, unsigned32 Source2, int indx +void::function::do_addu:unsigned32 *rDest, unsigned32 Source1, unsigned32 Source2 unsigned32 result = Source1 + Source2; - TRACE_ALU3 (indx, result, Source1, Source2); + TRACE_ALU3 (MY_INDEX, result, Source1, Source2); *rDest = result; 31.Dest,26.Source2,21.0b101100,15.1,14.SignedImmediate::::addu i - do_addu (_SD, rDest, vSource1, rSource2, MY_INDEX); + do_addu (_SD, rDest, vSource1, rSource2); 31.Dest,26.Source2,21.0b11101100,13.1,12.0,11./,4.Source1::::addu r - do_addu (_SD, rDest, rSource1, rSource2, MY_INDEX); + do_addu (_SD, rDest, rSource1, rSource2); 31.Dest,26.Source2,21.0b11101100,13.1,12.1,11./::::addu l long_immediate (LongSignedImmediate); - do_addu (_SD, rDest, LongSignedImmediate, rSource2, MY_INDEX); + do_addu (_SD, rDest, LongSignedImmediate, rSource2); -void::function::do_and:signed32 *rDest, signed32 Source1, signed32 Source2, int indx +void::function::do_and:signed32 *rDest, signed32 Source1, signed32 Source2 unsigned32 result = Source1 & Source2; - TRACE_ALU3 (indx, result, Source1, Source2); + TRACE_ALU3 (MY_INDEX, result, Source1, Source2); *rDest = result; // and, and.tt 31.Dest,26.Source2,21.0b0010001,14.SignedImmediate::::and.tt i - do_and (_SD, rDest, vSource1, rSource2, MY_INDEX); + do_and (_SD, rDest, vSource1, rSource2); 31.Dest,26.Source2,21.0b110010001,12.0,11./,4.Source1::::and.tt r - do_and (_SD, rDest, rSource1, rSource2, MY_INDEX); + do_and (_SD, rDest, rSource1, rSource2); 31.Dest,26.Source2,21.0b110010001,12.1,11./::::and.tt l long_immediate (LongSignedImmediate); - do_and (_SD, rDest, LongSignedImmediate, rSource2, MY_INDEX); + do_and (_SD, rDest, LongSignedImmediate, rSource2); // and.ff 31.Dest,26.Source2,21.0b0011000,14.SignedImmediate::::and.ff i - do_and (_SD, rDest, ~vSource1, ~rSource2, MY_INDEX); + do_and (_SD, rDest, ~vSource1, ~rSource2); 31.Dest,26.Source2,21.0b110011000,12.0,11./,4.Source1::::and.ff r - do_and (_SD, rDest, ~rSource1, ~rSource2, MY_INDEX); + do_and (_SD, rDest, ~rSource1, ~rSource2); 31.Dest,26.Source2,21.0b110011000,12.1,11./::::and.ff l long_immediate (LongSignedImmediate); - do_and (_SD, rDest, ~LongSignedImmediate, ~rSource2, MY_INDEX); + do_and (_SD, rDest, ~LongSignedImmediate, ~rSource2); // and.ft 31.Dest,26.Source2,21.0b0010100,14.SignedImmediate::::and.ft i - do_and (_SD, rDest, ~vSource1, rSource2, MY_INDEX); + do_and (_SD, rDest, ~vSource1, rSource2); 31.Dest,26.Source2,21.0b110010100,12.0,11./,4.Source1::::and.ft r - do_and (_SD, rDest, ~rSource1, rSource2, MY_INDEX); + do_and (_SD, rDest, ~rSource1, rSource2); 31.Dest,26.Source2,21.0b110010100,12.1,11./::::and.ft l long_immediate (LongSignedImmediate); - do_and (_SD, rDest, ~LongSignedImmediate, rSource2, MY_INDEX); + do_and (_SD, rDest, ~LongSignedImmediate, rSource2); // and.tf 31.Dest,26.Source2,21.0b0010010,14.SignedImmediate::::and.tf i - do_and (_SD, rDest, vSource1, ~rSource2, MY_INDEX); + do_and (_SD, rDest, vSource1, ~rSource2); 31.Dest,26.Source2,21.0b110010010,12.0,11./,4.Source1::::and.tf r - do_and (_SD, rDest, rSource1, ~rSource2, MY_INDEX); + do_and (_SD, rDest, rSource1, ~rSource2); 31.Dest,26.Source2,21.0b110010010,12.1,11./::::and.tf l long_immediate (LongSignedImmediate); - do_and (_SD, rDest, LongSignedImmediate, ~rSource2, MY_INDEX); + do_and (_SD, rDest, LongSignedImmediate, ~rSource2); // bbo.[a] -instruction_address::function::do_bbo:instruction_address nia, int bitnum, unsigned32 source, int annul, unsigned32 offset, int indx +instruction_address::function::do_bbo:instruction_address nia, int bitnum, unsigned32 source, int annul, unsigned32 offset int jump_p; unsigned32 target = cia.ip + 4 * offset; if (MASKED32 (source, bitnum, bitnum)) @@ -114,19 +116,19 @@ instruction_address::function::do_bbo:instruction_address nia, int bitnum, unsig } else jump_p = 0; - TRACE_COND_BR(indx, jump_p, bitnum, target); + TRACE_COND_BR(MY_INDEX, jump_p, bitnum, target); return nia; 31.BITNUM,26.Source,21.0b100101,15.A,14.SignedOffset::::bbo i - nia = do_bbo (_SD, nia, BITNUM, rSource, A, vSignedOffset, MY_INDEX); + nia = do_bbo (_SD, nia, BITNUM, rSource, A, vSignedOffset); 31.BITNUM,26.Source,21.0b11100101,13.A,12.0,11./,4.IndOff::::bbo r - nia = do_bbo (_SD, nia, BITNUM, rSource, A, rIndOff, MY_INDEX); + nia = do_bbo (_SD, nia, BITNUM, rSource, A, rIndOff); 31.BITNUM,26.Source,21.0b11100101,13.A,12.1,11./::::bbo l long_immediate (LongSignedImmediate); - nia = do_bbo (_SD, nia, BITNUM, rSource, A, LongSignedImmediate, MY_INDEX); + nia = do_bbo (_SD, nia, BITNUM, rSource, A, LongSignedImmediate); // bbz[.a] -instruction_address::function::do_bbz:instruction_address nia, int bitnum, unsigned32 source, int annul, unsigned32 offset, int indx +instruction_address::function::do_bbz:instruction_address nia, int bitnum, unsigned32 source, int annul, unsigned32 offset int jump_p; unsigned32 target = cia.ip + 4 * offset; if (!MASKED32 (source, bitnum, bitnum)) @@ -138,19 +140,19 @@ instruction_address::function::do_bbz:instruction_address nia, int bitnum, unsig } else jump_p = 0; - TRACE_COND_BR(indx, jump_p, bitnum, target); + TRACE_COND_BR(MY_INDEX, jump_p, bitnum, target); return nia; 31.BITNUM,26.Source,21.0b100100,15.A,14.SignedOffset::::bbz i - nia = do_bbz (_SD, nia, BITNUM, rSource, A, vSignedOffset, MY_INDEX); + nia = do_bbz (_SD, nia, BITNUM, rSource, A, vSignedOffset); 31.BITNUM,26.Source,21.0b11100100,13.A,12.0,11./,4.IndOff::::bbz r - nia = do_bbz (_SD, nia, BITNUM, rSource, A, rIndOff, MY_INDEX); + nia = do_bbz (_SD, nia, BITNUM, rSource, A, rIndOff); 31.BITNUM,26.Source,21.0b11100100,13.A,12.1,11./::::bbz l long_immediate (LongSignedImmediate); - nia = do_bbz (_SD, nia, BITNUM, rSource, A, LongSignedImmediate, MY_INDEX); + nia = do_bbz (_SD, nia, BITNUM, rSource, A, LongSignedImmediate); // bcnd[.a] -instruction_address::function::do_bcnd:instruction_address nia, int Cond, unsigned32 source, int annul, unsigned32 offset, int indx +instruction_address::function::do_bcnd:instruction_address nia, int Cond, unsigned32 source, int annul, unsigned32 offset int condition; int size = EXTRACTED32 (Cond, 31 - 27, 30 - 27); int code = EXTRACTED32 (Cond, 29 - 27, 27 - 27); @@ -180,33 +182,48 @@ instruction_address::function::do_bcnd:instruction_address nia, int Cond, unsign nia.ip = -1; nia.dp = target; } - TRACE_COND_BR(indx, condition, source, target); + TRACE_COND_BR(MY_INDEX, condition, source, target); return nia; 31.Code,26.Source,21.0b100110,15.A,14.SignedOffset::::bcnd i - nia = do_bcnd (_SD, nia, Code, rSource, A, vSignedOffset, MY_INDEX); + nia = do_bcnd (_SD, nia, Code, rSource, A, vSignedOffset); 31.Code,26.Source,21.0b11100110,13.A,12.0,11./,4.IndOff::::bcnd r - nia = do_bcnd (_SD, nia, Code, rSource, A, rIndOff, MY_INDEX); + nia = do_bcnd (_SD, nia, Code, rSource, A, rIndOff); 31.Code,26.Source,21.0b11100110,13.A,12.1,11./::::bcnd l long_immediate (LongSignedImmediate); - nia = do_bcnd (_SD, nia, Code, rSource, A, LongSignedImmediate, MY_INDEX); + nia = do_bcnd (_SD, nia, Code, rSource, A, LongSignedImmediate); // br[.a] - see bbz[.a] // brcr -#void::function::do_brcr:unsigned32 offset -# sim_io_error ("brcr"); -31.//,27.0,26.//,21.0b0000110,14.CRN::::brcr i -# nia = do_brcr (_SD, rCRN_val); -31.//,27.0,26.//,21.0b110000110,12.0,11./,4.Source1::::brcr r -# nia = do_brcr (_SD, CRN[rSource1]); +sim_cia::function::do_brcr:instruction_address nia, int cr + if (cr >= 0x4000 || !(CPU)->is_user_mode) + { + unsigned32 control = CR (cr); + unsigned32 ie = control & 0x00000001; + unsigned32 pc = control & 0xfffffffc; + unsigned32 is_user_mode = control & 0x00000002; + (CPU)->is_user_mode = is_user_mode; + nia.dp = pc; + if (ie) + (CPU)->cr[IE_CR] |= IE_CR_IE; + else + (CPU)->cr[IE_CR] &= ~IE_CR_IE; + } + TRACE_UCOND_BR (MY_INDEX, nia.dp); + return nia; +31.//,27.0,26.//,21.0b0000110,14.UCRN::::brcr i + nia = do_brcr (_SD, nia, UCRN); +31.//,27.0,26.//,21.0b110000110,12.0,11./,4.INDCR::::brcr r + nia = do_brcr (_SD, nia, UCRN); 31.//,27.0,26.//,21.0b110000110,12.1,11./::::brcr l -# nia = do_brcr (_SD, CRN[SL]); + long_immediate (UnsignedControlRegisterNumber) + nia = do_brcr (_SD, nia, UnsignedControlRegisterNumber); // bsr[.a] -instruction_address::function::do_bsr:instruction_address nia, signed32 *rLink, int annul, unsigned32 offset, int indx +instruction_address::function::do_bsr:instruction_address nia, signed32 *rLink, int annul, unsigned32 offset if (annul) { *rLink = nia.ip; @@ -215,19 +232,19 @@ instruction_address::function::do_bsr:instruction_address nia, signed32 *rLink, else *rLink = cia.dp + sizeof (instruction_word); nia.dp = cia.ip + 4 * offset; - TRACE_UCOND_BR (indx, nia.dp); + TRACE_UCOND_BR (MY_INDEX, nia.dp); return nia; 31.Link,26./,21.0b100000,15.A,14.SignedOffset::::bsr i - nia = do_bsr (_SD, nia, rLink, A, vSignedOffset, MY_INDEX); + nia = do_bsr (_SD, nia, rLink, A, vSignedOffset); 31.Link,26./,21.0b11100000,13.A,12.0,11./,4.IndOff::::bsr r - nia = do_bsr (_SD, nia, rLink, A, rIndOff, MY_INDEX); + nia = do_bsr (_SD, nia, rLink, A, rIndOff); 31.Link,26./,21.0b11100000,13.A,12.1,11./::::bsr l long_immediate (LongSignedImmediate); - nia = do_bsr (_SD, nia, rLink, A, LongSignedImmediate, MY_INDEX); + nia = do_bsr (_SD, nia, rLink, A, LongSignedImmediate); // cmnd -void::function::do_cmnd:signed32 source, int indx +void::function::do_cmnd:signed32 source int Reset = EXTRACTED32 (source, 31, 31); int Halt = EXTRACTED32 (source, 30, 30); int Unhalt = EXTRACTED32 (source, 29, 29); @@ -264,14 +281,14 @@ void::function::do_cmnd:signed32 source, int indx engine_error (SD, CPU, cia, "0x%lx: cmnd - Msg to MP not suported", (unsigned long) cia.ip); } - TRACE_SINK1 (indx, source); + TRACE_SINK1 (MY_INDEX, source); 31./,21.0b0000010,14.UI::::cmnd i - do_cmnd (_SD, UI, MY_INDEX); + do_cmnd (_SD, UI); 31./,21.0b110000010,12.0,11./,4.Source::::cmnd r - do_cmnd (_SD, rSource, MY_INDEX); + do_cmnd (_SD, rSource); 31./,21.0b110000010,12.1,11./::::cmnd l long_immediate (LongUnsignedImmediate); - do_cmnd (_SD, LongUnsignedImmediate, MY_INDEX); + do_cmnd (_SD, LongUnsignedImmediate); // cmp unsigned32::function::cmp_vals:signed32 s1, unsigned32 u1, signed32 s2, unsigned32 u2 @@ -287,7 +304,7 @@ unsigned32::function::cmp_vals:signed32 s1, unsigned32 u1, signed32 s2, unsigned if (u1 < u2) field |= BIT32 (8); if (u1 >= u2) field |= BIT32 (9); return field; -void::function::do_cmp:unsigned32 *rDest, unsigned32 Source1, unsigned32 Source2, int indx +void::function::do_cmp:unsigned32 *rDest, unsigned32 Source1, unsigned32 Source2 unsigned32 field = 0; field |= INSERTED32 (cmp_vals (_SD, Source2, Source1, Source2, Source2), 29, 20); @@ -297,15 +314,15 @@ void::function::do_cmp:unsigned32 *rDest, unsigned32 Source1, unsigned32 Source2 field |= INSERTED32 (cmp_vals (_SD, (signed8)Source1, (unsigned8)Source1, (signed8)Source2, (unsigned8)Source2), 9, 0); - TRACE_ALU3 (indx, field, Source1, Source2); + TRACE_ALU3 (MY_INDEX, field, Source1, Source2); *rDest = field; 31.Dest,26.Source2,21.0b1010000,14.SignedImmediate::::cmp i - do_cmp (_SD, rDest, vSource1, rSource2, MY_INDEX); + do_cmp (_SD, rDest, vSource1, rSource2); 31.Dest,26.Source2,21.0b111010000,12.0,11./,4.Source1::::cmp r - do_cmp (_SD, rDest, rSource1, rSource2, MY_INDEX); + do_cmp (_SD, rDest, rSource1, rSource2); 31.Dest,26.Source2,21.0b111010000,12.1,11./::::cmp l long_immediate (LongSignedImmediate); - do_cmp (_SD, rDest, LongSignedImmediate, rSource2, MY_INDEX); + do_cmp (_SD, rDest, LongSignedImmediate, rSource2); // dcache @@ -323,33 +340,33 @@ void::function::do_cmp:unsigned32 *rDest, unsigned32 Source1, unsigned32 Source2 // dld[{.b|.h|.d}] -void::function::do_dld:int Dest, unsigned32 Base, unsigned32 *rBase, int m , int sz, int S, unsigned32 Offset, int indx - do_ld (_SD, Dest, Base, rBase, m, sz, S, Offset, indx); +void::function::do_dld:int Dest, unsigned32 Base, unsigned32 *rBase, int m , int sz, int S, unsigned32 Offset + do_ld (_SD, Dest, Base, rBase, m, sz, S, Offset); 31.Dest,26.Base,21.0b110100,15.m,14.sz,12.0,11.S,10.1,9./,4.IndOff::::dld r - do_dld (_SD, Dest, rBase, &GPR(Base), m, sz, S, rIndOff, MY_INDEX); + do_dld (_SD, Dest, rBase, &GPR(Base), m, sz, S, rIndOff); 31.Dest,26.Base,21.0b110100,15.m,14.sz,12.1,11.S,10.1,9./::::dld l long_immediate (LongSignedImmediateOffset); - do_dld (_SD, Dest, rBase, &GPR(Base), m, sz, S, LongSignedImmediateOffset, MY_INDEX); + do_dld (_SD, Dest, rBase, &GPR(Base), m, sz, S, LongSignedImmediateOffset); // dld.u[{.b|.h|.d}] -void::function::do_dld_u:unsigned32 *rDest, unsigned32 Base, unsigned32 *rBase, int m , int sz, int S, unsigned32 Offset, int indx - do_ld_u (_SD, rDest, Base, rBase, m, sz, S, Offset, indx); +void::function::do_dld_u:unsigned32 *rDest, unsigned32 Base, unsigned32 *rBase, int m , int sz, int S, unsigned32 Offset + do_ld_u (_SD, rDest, Base, rBase, m, sz, S, Offset); 31.Dest,26.Base,21.0b110101,15.m,14.sz,12.0,11.S,10.1,9./,4.IndOff::::dld.u r - do_dld_u (_SD, rDest, rBase, &GPR(Base), m, sz, S, rIndOff, MY_INDEX); + do_dld_u (_SD, rDest, rBase, &GPR(Base), m, sz, S, rIndOff); 31.Dest,26.Base,21.0b110101,15.m,14.sz,12.1,11.S,10.1,9./::::dld.u l long_immediate (LongSignedImmediateOffset); - do_dld_u (_SD, rDest, rBase, &GPR(Base), m, sz, S, LongSignedImmediateOffset, MY_INDEX); + do_dld_u (_SD, rDest, rBase, &GPR(Base), m, sz, S, LongSignedImmediateOffset); // dst[{.b|.h|.d}] -void::function::do_dst:int Source, unsigned32 Base, unsigned32 *rBase, int m , int sz, int S, unsigned32 Offset, int indx - do_st (_SD, Source, Base, rBase, m, sz, S, Offset, indx); +void::function::do_dst:int Source, unsigned32 Base, unsigned32 *rBase, int m , int sz, int S, unsigned32 Offset + do_st (_SD, Source, Base, rBase, m, sz, S, Offset); 31.Source,26.Base,21.0b110110,15.m,14.sz,12.0,11.S,10.1,9./,4.IndOff::::dst r - do_dst (_SD, Source, rBase, &GPR(Base), m, sz, S, rIndOff, MY_INDEX); + do_dst (_SD, Source, rBase, &GPR(Base), m, sz, S, rIndOff); 31.Source,26.Base,21.0b110110,15.m,14.sz,12.1,11.S,10.1,9./::::dst l long_immediate (LongSignedImmediateOffset); - do_dst (_SD, Source, rBase, &GPR(Base), m, sz, S, LongSignedImmediateOffset, MY_INDEX); + do_dst (_SD, Source, rBase, &GPR(Base), m, sz, S, LongSignedImmediateOffset); // estop @@ -432,17 +449,13 @@ void::function::set_fp_reg:int Dest, sim_fpu val, int PD // fadd.{s|d}{s|d}{s|d} void::function::do_fadd:int Dest, int PD, sim_fpu s1, sim_fpu s2 sim_fpu ans = sim_fpu_add (s1, s2); - if (TRACE_FPU_P(CPU)) - trace_printf (SD, CPU, "0x%lx: fadd - %f + %f = %f\n", - (unsigned long) cia.ip, - sim_fpu_2d (s1), sim_fpu_2d (s2), - sim_fpu_2d (ans)); + TRACE_FPU3 (MY_INDEX, ans, s1, s2); set_fp_reg (_SD, Dest, ans, PD); -31.Dest,26.Source2,21.0b111110000,12.0,11.r,10.PD,8.P2,6.P1,4.Source1::::fadd r +31.Dest,26.Source2,21.0b111110000,12.0,11.r,10.PD,8.P2,6.P1,4.Source1::f::fadd r do_fadd (_SD, Dest, PD, get_fp_reg (_SD, Source1, rSource1, P1), get_fp_reg (_SD, Source2, rSource2, P2)); -31.Dest,26.Source2,21.0b111110000,12.1,11.r,10.PD,8.P2,6.P1,4./::::fadd l +31.Dest,26.Source2,21.0b111110000,12.1,11.r,10.PD,8.P2,6.P1,4./::f::fadd l long_immediate (SinglePrecisionFloatingPoint); do_fadd (_SD, Dest, PD, get_fp_reg (_SD, -1, SinglePrecisionFloatingPoint, P1), @@ -472,16 +485,12 @@ void::function::do_fcmp:unsigned32 *rDest, sim_fpu s1, sim_fpu s2 if (sim_fpu_cmp (s1, sim_fpu_32to (0)) <= 0 || sim_fpu_cmp (s1, s2) >= 0) *rDest |= BIT32(29); } - if (TRACE_FPU_P (CPU)) - trace_printf (SD, CPU, "0x%lx: fcmp - %f >=< %f - 0x%08x\n", - (unsigned long) cia.ip, - sim_fpu_2d (s1), sim_fpu_2d (s2), - (unsigned long) *rDest); -31.Dest,26.Source2,21.0b111110101,12.0,11./,10.0,8.P2,6.P1,4.Source1::::fcmp r + TRACE_FPU2I (MY_INDEX, *rDest, s1, s2); +31.Dest,26.Source2,21.0b111110101,12.0,11./,10.0,8.P2,6.P1,4.Source1::f::fcmp r do_fcmp (_SD, rDest, get_fp_reg (_SD, Source1, rSource1, P1), get_fp_reg (_SD, Source2, rSource2, P2)); -31.Dest,26.Source2,21.0b111110101,12.1,11./,10.0,8.P2,6.P1,4./::::fcmp l +31.Dest,26.Source2,21.0b111110101,12.1,11./,10.0,8.P2,6.P1,4./::f::fcmp l long_immediate (SinglePrecisionFloatingPoint); do_fcmp (_SD, rDest, get_fp_reg (_SD, -1, SinglePrecisionFloatingPoint, P1), @@ -492,17 +501,13 @@ void::function::do_fcmp:unsigned32 *rDest, sim_fpu s1, sim_fpu s2 // fdiv.{s|d}{s|d}{s|d} void::function::do_fdiv:int Dest, int PD, sim_fpu s1, sim_fpu s2 sim_fpu ans = sim_fpu_div (s1, s2); - if (TRACE_FPU_P(CPU)) - trace_printf (SD, CPU, "0x%lx: fdiv - %f / %f = %f\n", - (unsigned long) cia.ip, - sim_fpu_2d (s1), sim_fpu_2d (s2), - sim_fpu_2d (ans)); + TRACE_FPU3 (MY_INDEX, ans, s1, s2); set_fp_reg (_SD, Dest, ans, PD); -31.Dest,26.Source2,21.0b111110011,12.0,11./,10.PD,8.P2,6.P1,4.Source1::::fdiv r +31.Dest,26.Source2,21.0b111110011,12.0,11./,10.PD,8.P2,6.P1,4.Source1::f::fdiv r do_fdiv (_SD, Dest, PD, get_fp_reg (_SD, Source1, rSource1, P1), get_fp_reg (_SD, Source2, rSource2, P2)); -31.Dest,26.Source2,21.0b111110011,12.1,11./,10.PD,8.P2,6.P1,4./::::fdiv l +31.Dest,26.Source2,21.0b111110011,12.1,11./,10.PD,8.P2,6.P1,4./::f::fdiv l long_immediate (SinglePrecisionFloatingPoint); do_fdiv (_SD, Dest, PD, get_fp_reg (_SD, -1, SinglePrecisionFloatingPoint, P1), @@ -512,17 +517,13 @@ void::function::do_fdiv:int Dest, int PD, sim_fpu s1, sim_fpu s2 // fmpy.{s|d|i|u}{s|d|i|u}{s|d|i|u} void::function::do_fmpy:int Dest, int PD, sim_fpu s1, sim_fpu s2 sim_fpu ans = sim_fpu_mul (s1, s2); - if (TRACE_FPU_P(CPU)) - trace_printf (SD, CPU, "0x%lx: fmpy - %f * %f = %f\n", - (unsigned long) cia.ip, - sim_fpu_2d (s1), sim_fpu_2d (s2), - sim_fpu_2d (ans)); + TRACE_FPU3 (MY_INDEX, ans, s1, s2); set_fp_reg (_SD, Dest, ans, PD); -31.Dest,26.Source2,21.0b111110010,12.0,11./,10.PD,8.P2,6.P1,4.Source1::::fmpy r +31.Dest,26.Source2,21.0b111110010,12.0,11./,10.PD,8.P2,6.P1,4.Source1::f::fmpy r do_fmpy (_SD, Dest, PD, get_fp_reg (_SD, Source1, rSource1, P1), get_fp_reg (_SD, Source2, rSource2, P2)); -31.Dest,26.Source2,21.0b111110010,12.1,11./,10.PD,8.P2,6.P1,4./::::fmpy l +31.Dest,26.Source2,21.0b111110010,12.1,11./,10.PD,8.P2,6.P1,4./::f::fmpy l long_immediate (SinglePrecisionFloatingPoint); do_fmpy (_SD, Dest, PD, get_fp_reg (_SD, -1, SinglePrecisionFloatingPoint, P1), @@ -532,40 +533,40 @@ void::function::do_fmpy:int Dest, int PD, sim_fpu s1, sim_fpu s2 // frndm.{s|d|i|u}{s|d|i|u}{s|d|i|u} void::function::do_frnd:int Dest, int PD, sim_fpu s1 set_fp_reg (_SD, Dest, s1, PD); -31.Dest,26.Source2,21.0b111110100,12.0,11.r,10.PD,8.0b11,6.P1,4.Source::::frndm r +31.Dest,26.Source2,21.0b111110100,12.0,11.r,10.PD,8.0b11,6.P1,4.Source::f::frndm r do_frnd (_SD, Dest, PD, get_fp_reg (_SD, Source, rSource, P1)); -31.Dest,26.Source2,21.0b111110100,12.1,11.r,10.PD,8.0b11,6.P1,4./::::frndm l +31.Dest,26.Source2,21.0b111110100,12.1,11.r,10.PD,8.0b11,6.P1,4./::f::frndm l long_immediate (SinglePrecisionFloatingPoint); do_frnd (_SD, Dest, PD, get_fp_reg (_SD, -1, SinglePrecisionFloatingPoint, P1)); // frndn.{s|d|i|u}{s|d|i|u}{s|d|i|u} -31.Dest,26.Source2,21.0b111110100,12.0,11.r,10.PD,8.0b00,6.P1,4.Source::::frndn r +31.Dest,26.Source2,21.0b111110100,12.0,11.r,10.PD,8.0b00,6.P1,4.Source::f::frndn r do_frnd (_SD, Dest, PD, get_fp_reg (_SD, Source, rSource, P1)); -31.Dest,26.Source2,21.0b111110100,12.1,11.r,10.PD,8.0b00,6.P1,4./::::frndn l +31.Dest,26.Source2,21.0b111110100,12.1,11.r,10.PD,8.0b00,6.P1,4./::f::frndn l long_immediate (SinglePrecisionFloatingPoint); do_frnd (_SD, Dest, PD, get_fp_reg (_SD, -1, SinglePrecisionFloatingPoint, P1)); // frndp.{s|d|i|u}{s|d|i|u}{s|d|i|u} -31.Dest,26.Source2,21.0b111110100,12.0,11.r,10.PD,8.0b10,6.P1,4.Source::::frndp r +31.Dest,26.Source2,21.0b111110100,12.0,11.r,10.PD,8.0b10,6.P1,4.Source::f::frndp r do_frnd (_SD, Dest, PD, get_fp_reg (_SD, Source, rSource, P1)); -31.Dest,26.Source2,21.0b111110100,12.1,11.r,10.PD,8.0b10,6.P1,4./::::frndp l +31.Dest,26.Source2,21.0b111110100,12.1,11.r,10.PD,8.0b10,6.P1,4./::f::frndp l long_immediate (SinglePrecisionFloatingPoint); do_frnd (_SD, Dest, PD, get_fp_reg (_SD, -1, SinglePrecisionFloatingPoint, P1)); // frndz.{s|d|i|u}{s|d|i|u}{s|d|i|u} -31.Dest,26.Source2,21.0b111110100,12.0,11.r,10.PD,8.0b01,6.P1,4.Source::::frndz r +31.Dest,26.Source2,21.0b111110100,12.0,11.r,10.PD,8.0b01,6.P1,4.Source::f::frndz r do_frnd (_SD, Dest, PD, get_fp_reg (_SD, Source, rSource, P1)); -31.Dest,26.Source2,21.0b111110100,12.1,11.r,10.PD,8.0b01,6.P1,4./::::frndz l +31.Dest,26.Source2,21.0b111110100,12.1,11.r,10.PD,8.0b01,6.P1,4./::f::frndz l long_immediate (SinglePrecisionFloatingPoint); do_frnd (_SD, Dest, PD, get_fp_reg (_SD, -1, SinglePrecisionFloatingPoint, P1)); @@ -574,26 +575,22 @@ void::function::do_frnd:int Dest, int PD, sim_fpu s1 // fsqrt.{s|d}{s|d}{s|d} #void::function::do_fsqrt:unsigned32 *rDest, unsigned32 Source1, unsigned32 Source2 # sim_io_error ("fsqrt"); -31.Dest,26.Source2,21.0b111110111,12.0,11./,10.PD,8.//,6.P1,4.Source1::::fsqrt r +31.Dest,26.Source2,21.0b111110111,12.0,11./,10.PD,8.//,6.P1,4.Source1::f::fsqrt r # do_fsqrt (_SD, rDest, rSource1, rSource2); -31.Dest,26.Source2,21.0b111110111,12.1,11./,10.PD,8.//,6.P1,4./::::fsqrt l +31.Dest,26.Source2,21.0b111110111,12.1,11./,10.PD,8.//,6.P1,4./::f::fsqrt l # do_fsqrt (_SD, rDest, LongSignedImmediate, rSource2); // fsub.{s|d}{s|d}{s|d} void::function::do_fsub:int Dest, int PD, sim_fpu s1, sim_fpu s2 sim_fpu ans = sim_fpu_sub (s1, s2); - if (TRACE_FPU_P(CPU)) - trace_printf (SD, CPU, "0x%lx: fsub - %f + %f = %f\n", - (unsigned long) cia.ip, - sim_fpu_2d (s1), sim_fpu_2d (s2), - sim_fpu_2d (ans)); + TRACE_FPU3 (MY_INDEX, ans, s1, s2); set_fp_reg (_SD, Dest, ans, PD); -31.Dest,26.Source2,21.0b111110001,12.0,11.r,10.PD,8.P2,6.P1,4.Source1::::fsub r +31.Dest,26.Source2,21.0b111110001,12.0,11.r,10.PD,8.P2,6.P1,4.Source1::f::fsub r do_fsub (_SD, Dest, PD, get_fp_reg (_SD, Source1, rSource1, P1), get_fp_reg (_SD, Source2, rSource2, P2)); -31.Dest,26.Source2,21.0b111110001,12.1,11.r,10.PD,8.P2,6.P1,4./::::fsub l +31.Dest,26.Source2,21.0b111110001,12.1,11.r,10.PD,8.P2,6.P1,4./::f::fsub l long_immediate (SinglePrecisionFloatingPoint); do_fsub (_SD, Dest, PD, get_fp_reg (_SD, -1, SinglePrecisionFloatingPoint, P1), @@ -609,8 +606,8 @@ void::function::do_fsub:int Dest, int PD, sim_fpu s1, sim_fpu s2 // jsr[.a] -instruction_address::function::do_jsr:instruction_address nia, signed32 *rLink, int annul, unsigned32 offset, unsigned32 base, int indx - TRACE_UCOND_BR (indx, nia.ip); +instruction_address::function::do_jsr:instruction_address nia, signed32 *rLink, int annul, unsigned32 offset, unsigned32 base + TRACE_UCOND_BR (MY_INDEX, nia.ip); if (annul) { *rLink = nia.ip; @@ -626,16 +623,16 @@ instruction_address::function::do_jsr:instruction_address nia, signed32 *rLink, (unsigned long) nia.dp); return nia; 31.Link,26.Base,21.0b100010,15.A,14.SignedOffset::::jsr i - nia = do_jsr (_SD, nia, rLink, A, vSignedOffset, rBase, MY_INDEX); + nia = do_jsr (_SD, nia, rLink, A, vSignedOffset, rBase); 31.Link,26.Base,21.0b11100010,13.A,12.0,11./,4.Source1::::jsr r - nia = do_jsr (_SD, nia, rLink, A, rSource1, rBase, MY_INDEX); + nia = do_jsr (_SD, nia, rLink, A, rSource1, rBase); 31.Link,26.Base,21.0b11100010,13.A,12.1,11./::::jsr l long_immediate (LongSignedImmediate); - nia = do_jsr (_SD, nia, rLink, A, LongSignedImmediate, rBase, MY_INDEX); + nia = do_jsr (_SD, nia, rLink, A, LongSignedImmediate, rBase); // ld[{.b.h.d}] -void::function::do_ld:int Dest, unsigned32 Base, unsigned32 *rBase, int m , int sz, int S, unsigned32 Offset, int indx +void::function::do_ld:int Dest, unsigned32 Base, unsigned32 *rBase, int m , int sz, int S, unsigned32 Offset unsigned32 addr; switch (sz) { @@ -670,18 +667,18 @@ void::function::do_ld:int Dest, unsigned32 Base, unsigned32 *rBase, int m , int addr = -1; engine_error (SD, CPU, cia, "ld - invalid sz %d", sz); } - TRACE_LD (indx, m, S, GPR(Dest), Base, Offset); + TRACE_LD (MY_INDEX, m, S, GPR(Dest), Base, Offset); 31.Dest,26.Base,21.0b0100,17.m,16.sz,14.SignedOffset::::ld i - do_ld (_SD, Dest, rBase, &GPR(Base), m, sz, 0, vSignedOffset, MY_INDEX); + do_ld (_SD, Dest, rBase, &GPR(Base), m, sz, 0, vSignedOffset); 31.Dest,26.Base,21.0b110100,15.m,14.sz,12.0,11.S,10.0,9./,4.IndOff::::ld r - do_ld (_SD, Dest, rBase, &GPR(Base), m, sz, S, rIndOff, MY_INDEX); + do_ld (_SD, Dest, rBase, &GPR(Base), m, sz, S, rIndOff); 31.Dest,26.Base,21.0b110100,15.m,14.sz,12.1,11.S,10.0,9./::::ld l long_immediate (LongSignedImmediateOffset); - do_ld (_SD, Dest, rBase, &GPR(Base), m, sz, S, LongSignedImmediateOffset, MY_INDEX); + do_ld (_SD, Dest, rBase, &GPR(Base), m, sz, S, LongSignedImmediateOffset); // ld.u[{.b.h.d}] -void::function::do_ld_u:unsigned32 *rDest, unsigned32 Base, unsigned32 *rBase, int m , int sz, int S, unsigned32 Offset, int indx +void::function::do_ld_u:unsigned32 *rDest, unsigned32 Base, unsigned32 *rBase, int m , int sz, int S, unsigned32 Offset unsigned32 addr; switch (sz) { @@ -699,98 +696,111 @@ void::function::do_ld_u:unsigned32 *rDest, unsigned32 Base, unsigned32 *rBase, i } if (m) *rBase = addr; - TRACE_LD (indx, m, S, *rDest, Base, Offset); + TRACE_LD (MY_INDEX, m, S, *rDest, Base, Offset); 31.Dest,26.Base,21.0b0101,17.m,16.sz,14.SignedOffset::::ld.u i - do_ld_u (_SD, rDest, rBase, &GPR(Base), m, sz, 0, vSignedOffset, MY_INDEX); + do_ld_u (_SD, rDest, rBase, &GPR(Base), m, sz, 0, vSignedOffset); 31.Dest,26.Base,21.0b110101,15.m,14.sz,12.0,11.S,10.0,9./,4.IndOff::::ld.u r - do_ld_u (_SD, rDest, rBase, &GPR(Base), m, sz, S, rIndOff, MY_INDEX); + do_ld_u (_SD, rDest, rBase, &GPR(Base), m, sz, S, rIndOff); 31.Dest,26.Base,21.0b110101,15.m,14.sz,12.1,11.S,10.0,9./::::ld.u l long_immediate (LongSignedImmediateOffset); - do_ld_u (_SD, rDest, rBase, &GPR(Base), m, sz, S, LongSignedImmediateOffset, MY_INDEX); + do_ld_u (_SD, rDest, rBase, &GPR(Base), m, sz, S, LongSignedImmediateOffset); // lmo 31.Dest,26.Source,21.111111000,12.0,11./::::lmo - + int b; + for (b = 0; b < 32; b++) + if (rSource & BIT32 (31 - b)) + break; + TRACE_ALU2 (MY_INDEX, b, rSource); + *rDest = b; + // nop - see rdcr 0, r0 -void::function::do_or:unsigned32 *rDest, unsigned32 Source1, unsigned32 Source2, int indx +void::function::do_or:unsigned32 *rDest, unsigned32 Source1, unsigned32 Source2 unsigned32 result = Source1 | Source2; - TRACE_ALU3 (indx, result, Source1, Source2); + TRACE_ALU3 (MY_INDEX, result, Source1, Source2); *rDest = result; // or, or.tt 31.Dest,26.Source2,21.0b0010111,14.UnsignedImmediate::::or.tt i - do_or (_SD, rDest, vSource1, rSource2, MY_INDEX); + do_or (_SD, rDest, vSource1, rSource2); 31.Dest,26.Source2,21.0b110010111,12.0,11./,4.Source1::::or.tt r - do_or (_SD, rDest, rSource1, rSource2, MY_INDEX); + do_or (_SD, rDest, rSource1, rSource2); 31.Dest,26.Source2,21.0b110010111,12.1,11./::::or.tt l long_immediate (LongUnsignedImmediate); - do_or (_SD, rDest, LongUnsignedImmediate, rSource2, MY_INDEX); + do_or (_SD, rDest, LongUnsignedImmediate, rSource2); // or.ff 31.Dest,26.Source2,21.0b0011110,14.UnsignedImmediate::::or.ff i - do_or (_SD, rDest, ~vSource1, ~rSource2, MY_INDEX); + do_or (_SD, rDest, ~vSource1, ~rSource2); 31.Dest,26.Source2,21.0b110011110,12.0,11./,4.Source1::::or.ff r - do_or (_SD, rDest, ~rSource1, ~rSource2, MY_INDEX); + do_or (_SD, rDest, ~rSource1, ~rSource2); 31.Dest,26.Source2,21.0b110011110,12.1,11./::::or.ff l long_immediate (LongUnsignedImmediate); - do_or (_SD, rDest, ~LongUnsignedImmediate, ~rSource2, MY_INDEX); + do_or (_SD, rDest, ~LongUnsignedImmediate, ~rSource2); // or.ft 31.Dest,26.Source2,21.0b0011101,14.UnsignedImmediate::::or.ft i - do_or (_SD, rDest, ~vSource1, rSource2, MY_INDEX); + do_or (_SD, rDest, ~vSource1, rSource2); 31.Dest,26.Source2,21.0b110011101,12.0,11./,4.Source1::::or.ft r - do_or (_SD, rDest, ~rSource1, rSource2, MY_INDEX); + do_or (_SD, rDest, ~rSource1, rSource2); 31.Dest,26.Source2,21.0b110011101,12.1,11./::::or.ft l long_immediate (LongUnsignedImmediate); - do_or (_SD, rDest, ~LongUnsignedImmediate, rSource2, MY_INDEX); + do_or (_SD, rDest, ~LongUnsignedImmediate, rSource2); // or.tf 31.Dest,26.Source2,21.0b0011011,14.UnsignedImmediate::::or.tf i - do_or (_SD, rDest, vSource1, ~rSource2, MY_INDEX); + do_or (_SD, rDest, vSource1, ~rSource2); 31.Dest,26.Source2,21.0b110011011,12.0,11./,4.Source1::::or.tf r - do_or (_SD, rDest, rSource1, ~rSource2, MY_INDEX); + do_or (_SD, rDest, rSource1, ~rSource2); 31.Dest,26.Source2,21.0b110011011,12.1,11./::::or.tf l long_immediate (LongUnsignedImmediate); - do_or (_SD, rDest, LongUnsignedImmediate, ~rSource2, MY_INDEX); + do_or (_SD, rDest, LongUnsignedImmediate, ~rSource2); // rdcr -void::function::do_rdcr:unsigned32 Dest, int cr, int indx - TRACE_SINK2 (indx, Dest, cr); - if (Dest != 0) - engine_error (SD, CPU, cia, "rdcr unimplement"); +void::function::do_rdcr:unsigned32 Dest, int cr + TRACE_SINK2 (MY_INDEX, Dest, cr); + GPR (Dest) = CR (cr); 31.Dest,26.0,21.0b0000100,14.UCRN::::rdcr i - do_rdcr (_SD, Dest, UCRN, MY_INDEX); + do_rdcr (_SD, Dest, UCRN); 31.Dest,26.0,21.0b110000100,12.0,11./,4.INDCR::::rdcr r - do_rdcr (_SD, Dest, UCRN, MY_INDEX); + do_rdcr (_SD, Dest, UCRN); 31.Dest,26.0,21.0b110000100,12.1,11./::::rdcr l long_immediate (UnsignedControlRegisterNumber); - do_rdcr (_SD, Dest, UnsignedControlRegisterNumber, MY_INDEX); + do_rdcr (_SD, Dest, UnsignedControlRegisterNumber); // rmo 31.Dest,26.Source,21.0b111111001,12.0,11./::::rmo + int b; + for (b = 0; b < 32; b++) + if (rSource & BIT32 (b)) + break; + if (b < 32) + b = 31 - b; + TRACE_ALU2 (MY_INDEX, b, rSource); + *rDest = b; // rotl - see sl.dz -//rotr - see sl.dz +// rotr - see sl.dz // shl - see sl.iz // sl.{d|e|i}{m|s|z} -void::function::do_shift:int Dest, int Source, int Merge, int i, int n, int EndMask, int Rotate, int indx +void::function::do_shift:int Dest, int Source, int Merge, int i, int n, int EndMask, int Rotate /* see 10-30 for a reasonable description */ unsigned32 input = GPR (Source); unsigned32 rotated; @@ -861,9 +871,9 @@ void::function::do_shift:int Dest, int Source, int Merge, int i, int n, int EndM cia.ip, Source); } - TRACE_ALU2 (indx, GPR (Dest), input); + TRACE_ALU2 (MY_INDEX, GPR (Dest), input); 31.Dest,26.Source,21.0b0001,17.Merge,14./,11.i,10.n,9.EndMask,4.Rotate::::sl i - do_shift (_SD, Dest, Source, Merge, i, n, EndMask, Rotate, MY_INDEX); + do_shift (_SD, Dest, Source, Merge, i, n, EndMask, Rotate); 31.Dest,26.Source,21.0b110001,15.Merge,12.0,11.i,10.n,9.EndMask,4.RotReg::::sl r int endmask; if (EndMask == 0) @@ -876,32 +886,26 @@ void::function::do_shift:int Dest, int Source, int Merge, int i, int n, int EndM cia.ip, Source); endmask = GPR (Source + 1) & 31; } - do_shift (_SD, Dest, Source, Merge, i, n, endmask, GPR (RotReg) & 31, MY_INDEX); + do_shift (_SD, Dest, Source, Merge, i, n, endmask, GPR (RotReg) & 31); -// sli.{d|e|i}{m|s|z} -#31.Dest,26.Source,21.0b0001,17.Merge,14./,11.1,10.0,9.EndMask,4.Rotate::::sli i -#31.Dest,26.Source,21.0b110001,15.Merge,12.0,11.1,10.0,9.EndMask,4.RotReg::::sli r +// sli.{d|e|i}{m|s|z} - see shift -// sr.{d|e|i}{m|s|z} -#31.Dest,26.Source,21.0b0001,17.Merge,14./,11.0,10.1,9.EndMask,4.Rotate::::sr i -#31.Dest,26.Source,21.0b110001,15.Merge,12.0,11.0,10.1,9.EndMask,4.RotReg::::sr r +// sr.{d|e|i}{m|s|z} - see shift -// sra - see sr.es +// sra - see sr.es - see shift -// sri.{d|e|i}{m|s|z} -#31.Dest,26.Source,21.0b0001,17.Merge,14./,11.1,10.1,9.EndMask,4.Rotate::::sri i -#31.Dest,26.Source,21.0b110001,15.Merge,12.0,11.1,10.1,9.EndMask,4.RotReg::::sri r +// sri.{d|e|i}{m|s|z} - see shift // srl - see sr.ez // st[{.b|.h|.d}] -void::function::do_st:int Source, unsigned32 Base, unsigned32 *rBase, int m , int sz, int S, unsigned32 Offset, int indx +void::function::do_st:int Source, unsigned32 Base, unsigned32 *rBase, int m , int sz, int S, unsigned32 Offset unsigned32 addr; switch (sz) { @@ -930,59 +934,77 @@ void::function::do_st:int Source, unsigned32 Base, unsigned32 *rBase, int m , in } if (m) *rBase = addr; - TRACE_ST (indx, m, S, Source, Base, Offset); + TRACE_ST (MY_INDEX, m, S, Source, Base, Offset); 31.Source,26.Base,21.0b0110,17.m,16.sz,14.SignedOffset::::st i - do_st (_SD, Source, rBase, &GPR(Base), m, sz, 0, vSignedOffset, MY_INDEX); + do_st (_SD, Source, rBase, &GPR(Base), m, sz, 0, vSignedOffset); 31.Source,26.Base,21.0b110110,15.m,14.sz,12.0,11.S,10.0,9./,4.IndOff::::st r - do_st (_SD, Source, rBase, &GPR(Base), m, sz, S, rIndOff, MY_INDEX); + do_st (_SD, Source, rBase, &GPR(Base), m, sz, S, rIndOff); 31.Source,26.Base,21.0b110110,15.m,14.sz,12.1,11.S,10.0,9./::::st l long_immediate (LongSignedImmediateOffset); - do_st (_SD, Source, rBase, &GPR(Base), m, sz, S, LongSignedImmediateOffset, MY_INDEX); + do_st (_SD, Source, rBase, &GPR(Base), m, sz, S, LongSignedImmediateOffset); // sub -void::function::do_sub:signed32 *rDest, signed32 Source1, signed32 Source2, int indx +void::function::do_sub:signed32 *rDest, signed32 Source1, signed32 Source2 ALU_BEGIN (Source1); ALU_SUB (Source2); ALU_END (*rDest); - TRACE_ALU3 (indx, *rDest, Source1, Source2); + TRACE_ALU3 (MY_INDEX, *rDest, Source1, Source2); 31.Dest,26.Source2,21.0b101101,15.0,14.SignedImmediate::::sub i - do_sub (_SD, rDest, vSource1, rSource2, MY_INDEX); + do_sub (_SD, rDest, vSource1, rSource2); 31.Dest,26.Source2,21.0b11101101,13.0,12.0,11./,4.Source1::::sub r - do_sub (_SD, rDest, rSource1, rSource2, MY_INDEX); + do_sub (_SD, rDest, rSource1, rSource2); 31.Dest,26.Source2,21.0b11101101,13.0,12.1,11./::::sub l long_immediate (LongSignedImmediate); - do_sub (_SD, rDest, LongSignedImmediate, rSource2, MY_INDEX); + do_sub (_SD, rDest, LongSignedImmediate, rSource2); // subu -void::function::do_subu:signed32 *rDest, signed32 Source1, signed32 Source2, int indx +void::function::do_subu:signed32 *rDest, signed32 Source1, signed32 Source2 unsigned32 result = Source1 - Source2; - TRACE_ALU3 (indx, result, Source1, Source2); + TRACE_ALU3 (MY_INDEX, result, Source1, Source2); *rDest = result; // NOTE - the book has 15.1 which conflicts with subu. 31.Dest,26.Source2,21.0b101101,15.1,14.SignedImmediate::::subu i - do_subu (_SD, rDest, vSource1, rSource2, MY_INDEX); + do_subu (_SD, rDest, vSource1, rSource2); 31.Dest,26.Source2,21.0b11101101,13.1,12.0,11./,4.Source1::::subu r - do_subu (_SD, rDest, rSource1, rSource2, MY_INDEX); + do_subu (_SD, rDest, rSource1, rSource2); 31.Dest,26.Source2,21.0b11101101,13.1,12.1,11./::::subu l long_immediate (LongSignedImmediate); - do_subu (_SD, rDest, LongSignedImmediate, rSource2, MY_INDEX); + do_subu (_SD, rDest, LongSignedImmediate, rSource2); // swcr -#void::function::do_swcr:signed32 *rDest, signed32 Source1, signed32 Source2, int indx -31.Dest,26.Source,21.0b000010,15.1,14.SignedImmediate::::swcr i -# do_swcr (_SD, rDest, SI, rSource2, MY_INDEX); +void::function::do_swcr:int Dest, signed32 rSource, signed32 cr + tic80_control_regs reg = tic80_index2cr (cr); + /* cache the old CR value */ + unsigned32 old_cr = CR (cr); + /* Handle the write if allowed */ + if (cr >= 0x4000 || !(CPU)->is_user_mode) + switch (reg) + { + case INTPEN_CR: + CR (cr) &= ~rSource; + break; + default: + CR (cr) = rSource; + break; + } + /* Finish off the read */ + GPR (Dest) = old_cr; + TRACE_SINK3 (MY_INDEX, rSource, cr, Dest); +31.Dest,26.Source,21.0b000010,15.1,14.UCRN::::swcr i + do_swcr (_SD, Dest, rSource, UCRN); 31.Dest,26.Source,21.0b11000010,13.1,12.0,11./,4.INDCR::::swcr r -# do_swcr (_SD, rDest, rSource1, rSource2, MY_INDEX); + do_swcr (_SD, Dest, rSource, UCRN); 31.Dest,26.Source,21.0b11000010,13.1,12.1,11./::::swcr l -# do_swcr (_SD, rDest, LongSignedImmediate, rSource2, MY_INDEX); + long_immediate (LongUnsignedControlRegister); + do_swcr (_SD, Dest, rSource, LongUnsignedControlRegister); // trap -void::function::do_trap:unsigned32 trap_number, int indx - TRACE_SINK1 (indx, trap_number); +void::function::do_trap:unsigned32 trap_number + TRACE_SINK1 (MY_INDEX, trap_number); switch (trap_number) { case 72: @@ -1031,92 +1053,92 @@ void::function::do_trap:unsigned32 trap_number, int indx (unsigned long) cia.ip, trap_number); } 31./,27.0,26./,21.0b0000001,14.UTN::::trap i - do_trap (_SD, UTN, MY_INDEX); + do_trap (_SD, UTN); 31./,27.0,26./,21.0b110000001,12.0,11./,4.INDTR::::trap r - do_trap (_SD, UTN, MY_INDEX); + do_trap (_SD, UTN); 31./,27.0,26./,21.0b110000001,12.1,11./::::trap l long_immediate (UTN); - do_trap (_SD, UTN, MY_INDEX); + do_trap (_SD, UTN); // vadd.{s|d}{s|d} -31.*,26.Dest,21.0b11110,16./,15.0b000,12.0,11./,10.*,9.*,7.PD,6.*,5.P1,4.Source::::vadd r -31.*,26.Dest,21.0b11110,16./,15.0b000,12.1,11./,10.*,9.*,7.PD,6.*,5.P1,4.Source::::vadd l +31.*,26.Dest,21.0b11110,16./,15.0b000,12.0,11./,10.*,9.*,7.PD,6.*,5.P1,4.Source::f::vadd r +31.*,26.Dest,21.0b11110,16./,15.0b000,12.1,11./,10.*,9.*,7.PD,6.*,5.P1,4.Source::f::vadd l // vld{0|1}.{s|d} - see above - same instruction -#31.Dest,26.*,21.0b11110,16.*,10.1,9.S,8.*,6.p,7.******::::vld +#31.Dest,26.*,21.0b11110,16.*,10.1,9.S,8.*,6.p,7.******::f::vld // vmac.ss{s|d} -#31.*, 26.Source2,21.0b11110,16.a0,15.0b110,12.0,11.a1,10.*,9.*, 8.Z,7./,6.*,5./,4.Source1::::vmac.ss ra -31.Dest,26.Source2,21.0b11110,16.a0,15.0b110,12.0,11.a1,10.0,9.PD,8.Z,7./,6.0,5./,4.Source1::::vmac.ss rr -#31.*, 26.Source2,21.0b11110,16.a0,15.0b110,12.1,11.a1,10.*,9.*, 8.Z,7./,6.*,5./,4./::::vmac.ss ia -31.Dest,26.Source2,21.0b11110,16.a0,15.0b110,12.1,11.a1,10.0,9.PD,8.Z,7./,6.0,5./,4./::::vmac.ss ir +#31.*, 26.Source2,21.0b11110,16.a0,15.0b110,12.0,11.a1,10.*,9.*, 8.Z,7./,6.*,5./,4.Source1::f::vmac.ss ra +31.Dest,26.Source2,21.0b11110,16.a0,15.0b110,12.0,11.a1,10.0,9.PD,8.Z,7./,6.0,5./,4.Source1::f::vmac.ss rr +#31.*, 26.Source2,21.0b11110,16.a0,15.0b110,12.1,11.a1,10.*,9.*, 8.Z,7./,6.*,5./,4./::f::vmac.ss ia +31.Dest,26.Source2,21.0b11110,16.a0,15.0b110,12.1,11.a1,10.0,9.PD,8.Z,7./,6.0,5./,4./::f::vmac.ss ir // vmpy.{s|d}{s|d} -31.*,26.Dest,21.0b11110,16./,15.0b010,12.0,11./,10.*,8.*,7.PD,6.*,5.P1,4.Source::::vmpy r -31.*,26.Dest,21.0b11110,16./,15.0b010,12.1,11./,10.*,8.*,7.PD,6.*,5.P1,4./::::vmpy l +31.*,26.Dest,21.0b11110,16./,15.0b010,12.0,11./,10.*,8.*,7.PD,6.*,5.P1,4.Source::f::vmpy r +31.*,26.Dest,21.0b11110,16./,15.0b010,12.1,11./,10.*,8.*,7.PD,6.*,5.P1,4./::f::vmpy l // vmsc.ss{s|d} -#31.*, 26.Source2,21.0b11110,16.a0,15.0b111,12.0,11.a1,10.*,9.*, 8.Z,7./,6.*,5./,4.Source1::::vmsc.ss ra -31.Dest,26.Source2,21.0b11110,16.a0,15.0b111,12.0,11.a1,10.0,9.PD,8.Z,7./,6.0,5./,4.Source1::::vmsc.ss rr -#31.*, 26.Source2,21.0b11110,16.a0,15.0b111,12.1,11.a1,10.*,9.*, 8.Z,7./,6.*,5./,4./::::vmsc.ss ia -31.Dest,26.Source2,21.0b11110,16.a0,15.0b111,12.1,11.a1,10.0,9.PD,8.Z,7./,6.0,5./,4./::::vmsc.ss ir +#31.*, 26.Source2,21.0b11110,16.a0,15.0b111,12.0,11.a1,10.*,9.*, 8.Z,7./,6.*,5./,4.Source1::f::vmsc.ss ra +31.Dest,26.Source2,21.0b11110,16.a0,15.0b111,12.0,11.a1,10.0,9.PD,8.Z,7./,6.0,5./,4.Source1::f::vmsc.ss rr +#31.*, 26.Source2,21.0b11110,16.a0,15.0b111,12.1,11.a1,10.*,9.*, 8.Z,7./,6.*,5./,4./::f::vmsc.ss ia +31.Dest,26.Source2,21.0b11110,16.a0,15.0b111,12.1,11.a1,10.0,9.PD,8.Z,7./,6.0,5./,4./::f::vmsc.ss ir // vmsub.{s|d}{s|d} -31.*,26.Dest,21.0b11110,16.a0,15.0b011,12.0,11.a1,10.*,8.Z,7.PD,6.*,5./,4.Source::::vmsub r -31.*,26.Dest,21.0b11110,16.a0,15.0b011,12.1,11.a1,10.*,8.Z,7.PD,6.*,5./,4./::::vmsub l +31.*,26.Dest,21.0b11110,16.a0,15.0b011,12.0,11.a1,10.*,8.Z,7.PD,6.*,5./,4.Source::f::vmsub r +31.*,26.Dest,21.0b11110,16.a0,15.0b011,12.1,11.a1,10.*,8.Z,7.PD,6.*,5./,4./::f::vmsub l // vrnd.{s|d}{s|d} -31.*,26.Dest,21.0b11110,16.a0,15.0b100,12.0,11.a1,10.*,8.PD,6.*,5.P1,4.Source::::vrnd f r -31.*,26.Dest,21.0b11110,16.a0,15.0b100,12.1,11.a1,10.*,8.PD,6.*,5.P1,4./::::vrnd f l +31.*,26.Dest,21.0b11110,16.a0,15.0b100,12.0,11.a1,10.*,8.PD,6.*,5.P1,4.Source::f::vrnd f r +31.*,26.Dest,21.0b11110,16.a0,15.0b100,12.1,11.a1,10.*,8.PD,6.*,5.P1,4./::f::vrnd f l // vrnd.{i|u}{s|d} -31.*,26.Dest,21.0b11110,16./,15.0b101,12.0,11./,10.*,8./,7.PD,6.*,5.P1,4.Source::::vrnd i r -31.*,26.Dest,21.0b11110,16./,15.0b101,12.1,11./,10.*,8./,7.PD,6.*,5.P1,4./::::vrnd i l +31.*,26.Dest,21.0b11110,16./,15.0b101,12.0,11./,10.*,8./,7.PD,6.*,5.P1,4.Source::f::vrnd i r +31.*,26.Dest,21.0b11110,16./,15.0b101,12.1,11./,10.*,8./,7.PD,6.*,5.P1,4./::f::vrnd i l // vst.{s|d} - see above - same instruction -#31.Source,26.*,21.0b11110,16.*,10.0,9.S,8.*,6.1,5.*::::vst +#31.Source,26.*,21.0b11110,16.*,10.0,9.S,8.*,6.1,5.*::f::vst // vsub.{i|u}{s|d} -31.*,26.Dest,21.0b11110,16./,15.0b001,12.0,11./,10.*,8./,7.PD,6.*,5.P1,4.Source::::vsub r -31.*,26.Dest,21.0b11110,16./,15.0b001,12.1,11./,10.*,8./,7.PD,6.*,5.P1,4./::::vsub l +31.*,26.Dest,21.0b11110,16./,15.0b001,12.0,11./,10.*,8./,7.PD,6.*,5.P1,4.Source::f::vsub r +31.*,26.Dest,21.0b11110,16./,15.0b001,12.1,11./,10.*,8./,7.PD,6.*,5.P1,4./::f::vsub l // wrcr - see swcr, creg, source, r0 // xnor -void::function::do_xnor:signed32 *rDest, signed32 Source1, signed32 Source2, int indx +void::function::do_xnor:signed32 *rDest, signed32 Source1, signed32 Source2 unsigned32 result = ~ (Source1 ^ Source2); - TRACE_ALU3 (indx, result, Source1, Source2); + TRACE_ALU3 (MY_INDEX, result, Source1, Source2); *rDest = result; 31.Dest,26.Source2,21.0b0011001,14.UnsignedImmediate::::xnor i - do_xnor (_SD, rDest, vSource1, rSource2, MY_INDEX); + do_xnor (_SD, rDest, vSource1, rSource2); 31.Dest,26.Source2,21.0b110011001,12.0,11./,4.Source1::::xnor r - do_xnor (_SD, rDest, rSource1, rSource2, MY_INDEX); + do_xnor (_SD, rDest, rSource1, rSource2); 31.Dest,26.Source2,21.0b110011001,12.1,11./::::xnor l long_immediate (LongUnsignedImmediate); - do_xnor (_SD, rDest, LongUnsignedImmediate, rSource2, MY_INDEX); + do_xnor (_SD, rDest, LongUnsignedImmediate, rSource2); // xor -void::function::do_xor:signed32 *rDest, signed32 Source1, signed32 Source2, int indx +void::function::do_xor:signed32 *rDest, signed32 Source1, signed32 Source2 unsigned32 result = Source1 ^ Source2; - TRACE_ALU3 (indx, result, Source1, Source2); + TRACE_ALU3 (MY_INDEX, result, Source1, Source2); *rDest = result; 31.Dest,26.Source2,21.0b0010110,14.UnsignedImmediate::::xor i - do_xor (_SD, rDest, vSource1, rSource2, MY_INDEX); + do_xor (_SD, rDest, vSource1, rSource2); 31.Dest,26.Source2,21.0b110010110,13.0,12.0,11./,4.Source1::::xor r - do_xor (_SD, rDest, rSource1, rSource2, MY_INDEX); + do_xor (_SD, rDest, rSource1, rSource2); 31.Dest,26.Source2,21.0b110010110,13.0,12.1,11./::::xor l long_immediate (LongUnsignedImmediate); - do_xor (_SD, rDest, LongUnsignedImmediate, rSource2, MY_INDEX); + do_xor (_SD, rDest, LongUnsignedImmediate, rSource2); diff --git a/sim/tic80/interp.c b/sim/tic80/interp.c index 6d03d61..b8ba567 100644 --- a/sim/tic80/interp.c +++ b/sim/tic80/interp.c @@ -129,211 +129,3 @@ engine_run_until_stop (SIM_DESC sd, engine_halt (sd, cpu, cia, sim_stopped, SIGINT); } } - - -#if defined(WITH_TRACE) -/* Tracing support routines */ - -static char tic80_trace_buffer[1024]; -static int tic80_size_name; - -#define SIZE_HEX 8 -#define SIZE_DECIMAL 12 - -/* Initialize tracing by calculating the maximum name size */ -static void -tic80_init_trace (void) -{ - int i; - int len, max_len = 0; - - for (i = 0; i < (int)nr_itable_entries; i++) { - len = strlen (itable[i].name); - if (len > max_len) - max_len = len; - } - - tic80_size_name = max_len + sizeof(":m") - 1 + sizeof (":s") - 1; -} - -/* Trace the result of an ALU operation with 2 integer inputs and an integer output */ -char * -tic80_trace_alu3 (int indx, - unsigned32 result, - unsigned32 input1, - unsigned32 input2) -{ - char buf1[SIZE_DECIMAL+10], buf2[SIZE_DECIMAL+10], bufr[SIZE_DECIMAL+10]; - - if (!tic80_size_name) - tic80_init_trace (); - - sprintf (bufr, "(%ld)", (long) (signed32) result); - sprintf (buf1, "(%ld)", (long) (signed32) input1); - sprintf (buf2, "(%ld)", (long) (signed32) input2); - - sprintf (tic80_trace_buffer, "%-*s 0x%.*lx %-*s 0x%.*lx %-*s => 0x%.*lx %-*s", - tic80_size_name, itable[indx].name, - SIZE_HEX, input1, SIZE_DECIMAL, buf1, - SIZE_HEX, input2, SIZE_DECIMAL, buf2, - SIZE_HEX, result, SIZE_DECIMAL, bufr); - - return tic80_trace_buffer; -} - -/* Trace the result of an ALU operation with 1 integer input and an integer output */ -char * -tic80_trace_alu2 (int indx, - unsigned32 result, - unsigned32 input) -{ - char bufi[SIZE_DECIMAL+10], bufr[SIZE_DECIMAL+10]; - - if (!tic80_size_name) - tic80_init_trace (); - - sprintf (bufr, "(%ld)", (long) (signed32) result); - sprintf (bufi, "(%ld)", (long) (signed32) input); - - sprintf (tic80_trace_buffer, "%-*s 0x%.*lx %-*s %*s => 0x%.*lx %-*s", - tic80_size_name, itable[indx].name, - SIZE_HEX, input, SIZE_DECIMAL, bufi, - SIZE_HEX + SIZE_DECIMAL + 3, "", - SIZE_HEX, result, SIZE_DECIMAL, bufr); - - return tic80_trace_buffer; -} - -/* Trace the result of a NOP operation */ -char * -tic80_trace_nop (int indx) -{ - if (!tic80_size_name) - tic80_init_trace (); - - sprintf (tic80_trace_buffer, "%s", itable[indx].name); - return tic80_trace_buffer; -} - -/* Trace the result of a data sink with one input */ -char * -tic80_trace_sink1 (int indx, unsigned32 input) -{ - char buf[SIZE_DECIMAL+10]; - - if (!tic80_size_name) - tic80_init_trace (); - - sprintf (buf, "(%ld)", (long) (signed32) input); - sprintf (tic80_trace_buffer, "%-*s 0x%.*lx %-*s", - tic80_size_name, itable[indx].name, - SIZE_HEX, input, SIZE_DECIMAL, buf); - - return tic80_trace_buffer; -} - -/* Trace the result of a data sink with two inputs */ -char * -tic80_trace_sink2 (int indx, unsigned32 input1, unsigned32 input2) -{ - char buf1[SIZE_DECIMAL+10], buf2[SIZE_DECIMAL+10]; - - if (!tic80_size_name) - tic80_init_trace (); - - sprintf (buf1, "(%ld)", (long) (signed32) input1); - sprintf (buf2, "(%ld)", (long) (signed32) input2); - sprintf (tic80_trace_buffer, "%-*s 0x%.*lx %-*s 0x%.*lx %-*s", - tic80_size_name, itable[indx].name, - SIZE_HEX, input1, SIZE_DECIMAL, buf1, - SIZE_HEX, input2, SIZE_DECIMAL, buf2); - - return tic80_trace_buffer; -} - -/* Trace the result of a conditional branch operation */ -char * -tic80_trace_cond_br (int indx, - int jump_p, - unsigned32 cond, - unsigned32 target) -{ - char buf[SIZE_DECIMAL+10]; - - if (!tic80_size_name) - tic80_init_trace (); - - sprintf (buf, "(%ld)", (long) (signed32) cond); - - if (jump_p) - sprintf (tic80_trace_buffer, - "%-*s 0x%.*lx %*s 0x%.*lx %-*s => 0x%.*lx", - tic80_size_name, itable[indx].name, - SIZE_HEX, target, SIZE_DECIMAL, "", - SIZE_HEX, cond, SIZE_DECIMAL, buf, - SIZE_HEX, target); - else - sprintf (tic80_trace_buffer, - "%-*s 0x%.*lx %*s 0x%.*lx %-*s => [fallthrough]", - tic80_size_name, itable[indx].name, - SIZE_HEX, target, SIZE_DECIMAL, "", - SIZE_HEX, cond, SIZE_DECIMAL, buf); - - return tic80_trace_buffer; -} - -/* Trace the result of a unconditional branch operation */ -char * -tic80_trace_ucond_br (int indx, - unsigned32 target) -{ - if (!tic80_size_name) - tic80_init_trace (); - - sprintf (tic80_trace_buffer, - "%-*s 0x%.*lx %*s => 0x%.*lx", - tic80_size_name, itable[indx].name, - SIZE_HEX, target, (SIZE_DECIMAL*2) + SIZE_HEX + 4, "", - SIZE_HEX, target); - - return tic80_trace_buffer; -} - -/* Trace the result of a load or store operation with 2 integer addresses - and an integer output or input */ -char * -tic80_trace_ldst (int indx, - int st_p, - int m_p, - int s_p, - unsigned32 value, - unsigned32 input1, - unsigned32 input2) -{ - char buf1[SIZE_DECIMAL+10], buf2[SIZE_DECIMAL+10], bufr[SIZE_DECIMAL+10]; - char name[40]; - - if (!tic80_size_name) - tic80_init_trace (); - - strcpy (name, itable[indx].name); - if (m_p) - strcat (name, ":m"); - - if (s_p) - strcat (name, ":s"); - - sprintf (bufr, "(%ld)", (long) (signed32) value); - sprintf (buf1, "(%ld)", (long) (signed32) input1); - sprintf (buf2, "(%ld)", (long) (signed32) input2); - - sprintf (tic80_trace_buffer, "%-*s 0x%.*lx %-*s 0x%.*lx %-*s %s 0x%.*lx %-*s", - tic80_size_name, name, - SIZE_HEX, input1, SIZE_DECIMAL, buf1, - SIZE_HEX, input2, SIZE_DECIMAL, buf2, - (!st_p) ? "=>" : "<=", - SIZE_HEX, value, SIZE_DECIMAL, bufr); - - return tic80_trace_buffer; -} -#endif /* WITH_TRACE */ diff --git a/sim/tic80/misc.c b/sim/tic80/misc.c new file mode 100644 index 0000000..efadbae --- /dev/null +++ b/sim/tic80/misc.c @@ -0,0 +1,412 @@ +/* TIc80 Simulator. + Copyright (C) 1997 Free Software Foundation, Inc. + Contributed by Cygnus Support. + +This file is part of GDB, the GNU debugger. + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2, or (at your option) +any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License along +with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + + +#include "sim-main.h" + +#ifdef HAVE_STRING_H +#include <string.h> +#else +#ifdef HAVE_STRINGS_H +#include <strings.h> +#endif +#endif + + +tic80_control_regs +tic80_index2cr (int index) +{ + switch (index) + { + case 0x0000: return EPC_CR; + case 0x0001: return EIP_CR; + case 0x0002: return CONFIG_CR; + case 0x0004: return INTPEN_CR; + case 0x0006: return IE_CR; + case 0x0008: return FPST_CR; + case 0x000A: return PPERROR_CR; + case 0x000D: return PKTREQ_CR; + case 0x000E: return TCOUNT_CR; + case 0x000F: return TSCALE_CR; + case 0x0010: return FLTOP_CR; + case 0x0011: return FLTADR_CR; + case 0x0012: return FLTTAG_CR; + case 0x0013: return FLTDLT_CR; + case 0x0014: return FLTDTH_CR; + case 0x0015: return FLT005_CR; + case 0x0016: return FLT006_CR; + case 0x0017: return FLT007_CR; + case 0x0018: return FLT008_CR; + case 0x0019: return FLT009_CR; + case 0x001a: return FLT010_CR; + case 0x001b: return FLT011_CR; + case 0x001c: return FLT012_CR; + case 0x001d: return FLT013_CR; + case 0x001e: return FLT014_CR; + case 0x001f: return FLT015_CR; + case 0x0020: return SYSSTK_CR; + case 0x0021: return SYSTMP_CR; + case 0x0030: return MPC_CR; + case 0x0031: return MIP_CR; + case 0x0033: return ECOMCNTL_CR; + case 0x0034: return ANASTAT_CR; + case 0x0039: return BRK1_CR; + case 0x003A: return BRK2_CR; + case 0x0200: return ITAG0_CR; + case 0x0201: return ITAG1_CR; + case 0x0202: return ITAG2_CR; + case 0x0203: return ITAG3_CR; + case 0x0204: return ITAG4_CR; + case 0x0205: return ITAG5_CR; + case 0x0206: return ITAG6_CR; + case 0x0207: return ITAG7_CR; + case 0x0208: return ITAG8_CR; + case 0x0209: return ITAG9_CR; + case 0x020a: return ITAG10_CR; + case 0x020b: return ITAG11_CR; + case 0x020c: return ITAG12_CR; + case 0x020d: return ITAG13_CR; + case 0x020e: return ITAG14_CR; + case 0x020f: return ITAG15_CR; + case 0x0300: return ILRU_CR; + case 0x0400: return DTAG0_CR; + case 0x0401: return DTAG1_CR; + case 0x0402: return DTAG2_CR; + case 0x0403: return DTAG3_CR; + case 0x0404: return DTAG4_CR; + case 0x0405: return DTAG5_CR; + case 0x0406: return DTAG6_CR; + case 0x0407: return DTAG7_CR; + case 0x0408: return DTAG8_CR; + case 0x0409: return DTAG9_CR; + case 0x040a: return DTAG10_CR; + case 0x040b: return DTAG11_CR; + case 0x040c: return DTAG12_CR; + case 0x040d: return DTAG13_CR; + case 0x040e: return DTAG14_CR; + case 0x040f: return DTAG15_CR; + case 0x0500: return DLRU_CR; + case 0x4000: return IN0P_CR; + case 0x4001: return IN1P_CR; + case 0x4002: return OUTP_CR; + default: return SCRATCH_CR; + } +} + + + +#if defined(WITH_TRACE) +/* Tracing support routines */ + +static char tic80_trace_buffer[1024]; +static int tic80_size_name; + +#define SIZE_HEX 8 +#define SIZE_DECIMAL 12 + +/* Initialize tracing by calculating the maximum name size */ +static void +tic80_init_trace (void) +{ + int i; + int len, max_len = 0; + + for (i = 0; i < (int)nr_itable_entries; i++) { + len = strlen (itable[i].name); + if (len > max_len) + max_len = len; + } + + tic80_size_name = max_len + sizeof(":m") - 1 + sizeof (":s") - 1; +} + +/* Trace the result of an ALU operation with 2 integer inputs and an integer output */ +char * +tic80_trace_alu3 (int indx, + unsigned32 result, + unsigned32 input1, + unsigned32 input2) +{ + char buf1[SIZE_DECIMAL+10], buf2[SIZE_DECIMAL+10], bufr[SIZE_DECIMAL+10]; + + if (!tic80_size_name) + tic80_init_trace (); + + sprintf (bufr, "(%ld)", (long) (signed32) result); + sprintf (buf1, "(%ld)", (long) (signed32) input1); + sprintf (buf2, "(%ld)", (long) (signed32) input2); + + sprintf (tic80_trace_buffer, "%-*s 0x%.*lx %-*s 0x%.*lx %-*s => 0x%.*lx %-*s", + tic80_size_name, itable[indx].name, + SIZE_HEX, input1, SIZE_DECIMAL, buf1, + SIZE_HEX, input2, SIZE_DECIMAL, buf2, + SIZE_HEX, result, SIZE_DECIMAL, bufr); + + return tic80_trace_buffer; +} + +/* Trace the result of an ALU operation with 1 integer input and an integer output */ +char * +tic80_trace_alu2 (int indx, + unsigned32 result, + unsigned32 input) +{ + char bufi[SIZE_DECIMAL+10], bufr[SIZE_DECIMAL+10]; + + if (!tic80_size_name) + tic80_init_trace (); + + sprintf (bufr, "(%ld)", (long) (signed32) result); + sprintf (bufi, "(%ld)", (long) (signed32) input); + + sprintf (tic80_trace_buffer, "%-*s 0x%.*lx %-*s %*s => 0x%.*lx %-*s", + tic80_size_name, itable[indx].name, + SIZE_HEX, input, SIZE_DECIMAL, bufi, + SIZE_HEX + SIZE_DECIMAL + 3, "", + SIZE_HEX, result, SIZE_DECIMAL, bufr); + + return tic80_trace_buffer; +} + +/* Trace the result of an FPU operation with 2 integer inputs and an integer output */ +void +tic80_trace_fpu3 (SIM_DESC sd, + sim_cpu *cpu, + sim_cia cia, + int indx, + sim_fpu result, + sim_fpu input1, + sim_fpu input2) +{ + if (!tic80_size_name) + tic80_init_trace (); + + trace_one_insn (sd, cpu, cia.ip, 1, + itable[indx].file, itable[indx].line_nr, "fpu", + "%-*s %*f %*f => %*f", + tic80_size_name, itable[indx].name, + SIZE_HEX + SIZE_DECIMAL + 3, sim_fpu_2d (input1), + SIZE_HEX + SIZE_DECIMAL + 3, sim_fpu_2d (input2), + SIZE_HEX + SIZE_DECIMAL + 3, sim_fpu_2d (result)); +} + +/* Trace the result of an FPU operation with 1 integer input and an integer output */ +void +tic80_trace_fpu2 (SIM_DESC sd, + sim_cpu *cpu, + sim_cia cia, + int indx, + sim_fpu result, + sim_fpu input) +{ + if (!tic80_size_name) + tic80_init_trace (); + + trace_one_insn (sd, cpu, cia.ip, 1, + itable[indx].file, itable[indx].line_nr, "fpu", + "%-*s %*f %-*s => %*f", + tic80_size_name, itable[indx].name, + SIZE_HEX + SIZE_DECIMAL + 3, sim_fpu_2d (input), + SIZE_HEX + SIZE_DECIMAL + 3, "", + SIZE_HEX + SIZE_DECIMAL, sim_fpu_2d (result)); +} + +/* Trace the result of an FPU operation with 1 integer input and an integer output */ +void +tic80_trace_fpu2i (SIM_DESC sd, + sim_cpu *cpu, + sim_cia cia, + int indx, + unsigned32 result, + sim_fpu input1, + sim_fpu input2) +{ + char bufr[SIZE_DECIMAL+10]; + + if (!tic80_size_name) + tic80_init_trace (); + + sprintf (bufr, "(%ld)", (long) (signed32) result); + + trace_one_insn (sd, cpu, cia.ip, 1, + itable[indx].file, itable[indx].line_nr, "fpu", + "%-*s %*f %*f => 0x%.*lx %-*s", + tic80_size_name, itable[indx].name, + SIZE_HEX + SIZE_DECIMAL + 3, sim_fpu_2d (input1), + SIZE_HEX + SIZE_DECIMAL + 3, sim_fpu_2d (input2), + SIZE_HEX, result, SIZE_DECIMAL, bufr); +} + +/* Trace the result of a NOP operation */ +char * +tic80_trace_nop (int indx) +{ + if (!tic80_size_name) + tic80_init_trace (); + + sprintf (tic80_trace_buffer, "%s", itable[indx].name); + return tic80_trace_buffer; +} + +/* Trace the result of a data sink with one input */ +char * +tic80_trace_sink1 (int indx, unsigned32 input) +{ + char buf[SIZE_DECIMAL+10]; + + if (!tic80_size_name) + tic80_init_trace (); + + sprintf (buf, "(%ld)", (long) (signed32) input); + sprintf (tic80_trace_buffer, "%-*s 0x%.*lx %-*s", + tic80_size_name, itable[indx].name, + SIZE_HEX, input, SIZE_DECIMAL, buf); + + return tic80_trace_buffer; +} + +/* Trace the result of a data sink with two inputs */ +char * +tic80_trace_sink2 (int indx, unsigned32 input1, unsigned32 input2) +{ + char buf1[SIZE_DECIMAL+10], buf2[SIZE_DECIMAL+10]; + + if (!tic80_size_name) + tic80_init_trace (); + + sprintf (buf1, "(%ld)", (long) (signed32) input1); + sprintf (buf2, "(%ld)", (long) (signed32) input2); + sprintf (tic80_trace_buffer, "%-*s 0x%.*lx %-*s 0x%.*lx %-*s", + tic80_size_name, itable[indx].name, + SIZE_HEX, input1, SIZE_DECIMAL, buf1, + SIZE_HEX, input2, SIZE_DECIMAL, buf2); + + return tic80_trace_buffer; +} + +/* Trace the result of a data sink with two inputs */ +char * +tic80_trace_sink3 (int indx, unsigned32 input1, unsigned32 input2, unsigned32 input3) +{ + char buf1[SIZE_DECIMAL+10], buf2[SIZE_DECIMAL+10], buf3[SIZE_DECIMAL+10]; + + if (!tic80_size_name) + tic80_init_trace (); + + sprintf (buf1, "(%ld)", (long) (signed32) input1); + sprintf (buf2, "(%ld)", (long) (signed32) input2); + sprintf (buf3, "(%ld)", (long) (signed32) input3); + + sprintf (tic80_trace_buffer, "%-*s 0x%.*lx %-*s 0x%.*lx %-*s 0x%.*lx %-*s", + tic80_size_name, itable[indx].name, + SIZE_HEX, input1, SIZE_DECIMAL, buf1, + SIZE_HEX, input2, SIZE_DECIMAL, buf2, + SIZE_HEX, input3, SIZE_DECIMAL, buf3); + + return tic80_trace_buffer; +} + +/* Trace the result of a conditional branch operation */ +char * +tic80_trace_cond_br (int indx, + int jump_p, + unsigned32 cond, + unsigned32 target) +{ + char buf[SIZE_DECIMAL+10]; + + if (!tic80_size_name) + tic80_init_trace (); + + sprintf (buf, "(%ld)", (long) (signed32) cond); + + if (jump_p) + sprintf (tic80_trace_buffer, + "%-*s 0x%.*lx %*s 0x%.*lx %-*s => 0x%.*lx", + tic80_size_name, itable[indx].name, + SIZE_HEX, target, SIZE_DECIMAL, "", + SIZE_HEX, cond, SIZE_DECIMAL, buf, + SIZE_HEX, target); + else + sprintf (tic80_trace_buffer, + "%-*s 0x%.*lx %*s 0x%.*lx %-*s => [fallthrough]", + tic80_size_name, itable[indx].name, + SIZE_HEX, target, SIZE_DECIMAL, "", + SIZE_HEX, cond, SIZE_DECIMAL, buf); + + return tic80_trace_buffer; +} + +/* Trace the result of a unconditional branch operation */ +char * +tic80_trace_ucond_br (int indx, + unsigned32 target) +{ + if (!tic80_size_name) + tic80_init_trace (); + + sprintf (tic80_trace_buffer, + "%-*s 0x%.*lx %*s => 0x%.*lx", + tic80_size_name, itable[indx].name, + SIZE_HEX, target, (SIZE_DECIMAL*2) + SIZE_HEX + 4, "", + SIZE_HEX, target); + + return tic80_trace_buffer; +} + +/* Trace the result of a load or store operation with 2 integer addresses + and an integer output or input */ +char * +tic80_trace_ldst (int indx, + int st_p, + int m_p, + int s_p, + unsigned32 value, + unsigned32 input1, + unsigned32 input2) +{ + char buf1[SIZE_DECIMAL+10], buf2[SIZE_DECIMAL+10], bufr[SIZE_DECIMAL+10]; + char name[40]; + + if (!tic80_size_name) + tic80_init_trace (); + + strcpy (name, itable[indx].name); + if (m_p) + strcat (name, ":m"); + + if (s_p) + strcat (name, ":s"); + + sprintf (bufr, "(%ld)", (long) (signed32) value); + sprintf (buf1, "(%ld)", (long) (signed32) input1); + sprintf (buf2, "(%ld)", (long) (signed32) input2); + + sprintf (tic80_trace_buffer, "%-*s 0x%.*lx %-*s 0x%.*lx %-*s %s 0x%.*lx %-*s", + tic80_size_name, name, + SIZE_HEX, input1, SIZE_DECIMAL, buf1, + SIZE_HEX, input2, SIZE_DECIMAL, buf2, + (!st_p) ? "=>" : "<=", + SIZE_HEX, value, SIZE_DECIMAL, bufr); + + return tic80_trace_buffer; +} + +#endif /* WITH_TRACE */ diff --git a/sim/tic80/sim-calls.c b/sim/tic80/sim-calls.c index 966b71f..cf8e2e9 100644 --- a/sim/tic80/sim-calls.c +++ b/sim/tic80/sim-calls.c @@ -222,6 +222,7 @@ sim_create_inferior (SIM_DESC sd, STATE_CPU (sd, 0)->cia.ip = STATE_START_ADDR(sd); STATE_CPU (sd, 0)->cia.dp = (STATE_START_ADDR(sd) + sizeof (instruction_word)); + STATE_CPU (sd, 0)->cr[IE_CR] |= IE_CR_IE; STATE_CPU (sd, 0)->reg[1] = TIC80_MEM_START + TIC80_MEM_SIZE - 16; return SIM_RC_OK; } diff --git a/sim/tic80/sim-main.h b/sim/tic80/sim-main.h index fc78cb3..1992f29 100644 --- a/sim/tic80/sim-main.h +++ b/sim/tic80/sim-main.h @@ -38,8 +38,8 @@ static const sim_cia null_cia = {0}; /* Dummy */ #include "sim-base.h" -#include "cpu.h" #include "alu.h" +#include "cpu.h" struct sim_state { |