diff options
| -rw-r--r-- | sim/v850/ChangeLog | 12 | ||||
| -rw-r--r-- | sim/v850/interp.c | 101 | ||||
| -rw-r--r-- | sim/v850/simops.c | 189 |
3 files changed, 181 insertions, 121 deletions
diff --git a/sim/v850/ChangeLog b/sim/v850/ChangeLog index f90bfda..7c33dba 100644 --- a/sim/v850/ChangeLog +++ b/sim/v850/ChangeLog @@ -1,5 +1,17 @@ Thu Aug 29 13:53:29 1996 Jeffrey A Law (law@cygnus.com) + * v850_sim.h: The V850 doesn't have split I&D spaces. Change + accordingly. Remove many unused definitions. + * interp.c: The V850 doesn't have split I&D spaces. Change + accordingly. + (get_longlong, get_longword, get_word): Deleted. + (write_longlong, write_longword, write_word): Deleted. + (get_operands): Deleted. + (get_byte, get_half, get_word): New functions. + (put_byte, put_half, put_word): New functions. + * simops.c: Remove unused functions. Rough cut at + "ld.b", "ld.h", "ld.w", "st.b", "st.h", "st.w" insns. + * v850_sim.h (struct _state): Remove "psw" field. Add "sregs" field. (PSW): Remove bogus definition. diff --git a/sim/v850/interp.c b/sim/v850/interp.c index d824590..fbd808d 100644 --- a/sim/v850/interp.c +++ b/sim/v850/interp.c @@ -6,8 +6,7 @@ #include "v850_sim.h" -#define IMEM_SIZE 18 /* V850 instruction memory size is 18 bits */ -#define DMEM_SIZE 16 /* Data memory */ +#define MEM_SIZE 18 /* V850 memory size is 18 bits XXX */ uint16 OP[4]; @@ -72,82 +71,58 @@ lookup_hash (ins) return (h); } -uint32 -get_longword (x) - uint8 *x; +uint8 +get_byte (x) + uint8 *x; { - uint8 *a = x; - return (a[3]<<24) + (a[2]<<16) + (a[1]<<8) + (a[0]); + return *x; } -int64 -get_longlong (x) - uint8 *x; +uint16 +get_half (x) + uint8 *x; { uint8 *a = x; - return ((int64)a[0]<<56) + ((int64)a[1]<<48) + ((int64)a[2]<<40) + ((int64)a[3]<<32) + - ((int64)a[4]<< 24) + ((int64)a[5]<<16) + ((int64)a[6]<<8) + (int64)a[7]; + return (a[1] << 8) + (a[0]); } -uint16 +uint32 get_word (x) uint8 *x; { uint8 *a = x; - return ((uint16)a[0]<<8) + a[1]; + return (a[3]<<24) + (a[2]<<16) + (a[1]<<8) + (a[0]); } - void -write_word (addr, data) +put_byte (addr, data) uint8 *addr; - uint16 data; + uint8 data; { uint8 *a = addr; - a[0] = data >> 8; - a[1] = data & 0xff; + a[0] = data; } void -write_longword (addr, data) +put_half (addr, data) uint8 *addr; - uint32 data; + uint16 data; { - addr[0] = (data >> 24) & 0xff; - addr[1] = (data >> 16) & 0xff; - addr[2] = (data >> 8) & 0xff; - addr[3] = data & 0xff; + uint8 *a = addr; + a[0] = data & 0xff; + a[1] = (data >> 8) & 0xff; } void -write_longlong (addr, data) +put_word (addr, data) uint8 *addr; - int64 data; + uint32 data; { uint8 *a = addr; - a[0] = data >> 56; - a[1] = (data >> 48) & 0xff; - a[2] = (data >> 40) & 0xff; - a[3] = (data >> 32) & 0xff; - a[4] = (data >> 24) & 0xff; - a[5] = (data >> 16) & 0xff; - a[6] = (data >> 8) & 0xff; - a[7] = data & 0xff; -} - -static void -get_operands (struct simops *s, uint32 ins) -{ - int i, shift, bits, flags; - uint32 mask; - for (i=0; i < s->numops; i++) - { - shift = s->operands[3*i]; - bits = s->operands[3*i+1]; - flags = s->operands[3*i+2]; - mask = 0x7FFFFFFF >> (31 - bits); - OP[i] = (ins >> shift) & mask; - } + a[0] = data & 0xff; + a[1] = (data >> 8) & 0xff; + a[2] = (data >> 16) & 0xff; + a[3] = (data >> 24) & 0xff; } static void @@ -213,7 +188,14 @@ static void do_format_7 (insn) uint32 insn; { + struct hash_entry *h; printf("format 7 0x%x\n", insn); + + h = lookup_hash (insn); + OP[0] = insn & 0x1f; + OP[1] = (insn >> 11) & 0x1f; + OP[2] = (insn >> 16) & 0xffff; + (h->ops->func) (); } static void @@ -241,27 +223,24 @@ sim_size (power) int power; { - if (State.imem) + if (State.mem) { - free (State.imem); - free (State.dmem); + free (State.mem); } - State.imem = (uint8 *)calloc(1,1<<IMEM_SIZE); - State.dmem = (uint8 *)calloc(1,1<<DMEM_SIZE); - if (!State.imem || !State.dmem ) + State.mem = (uint8 *)calloc(1,1<<MEM_SIZE); + if (!State.mem) { fprintf (stderr,"Memory allocation failed.\n"); exit(1); } - printf ("Allocated %d bytes instruction memory and\n",1<<IMEM_SIZE); - printf (" %d bytes data memory.\n",1<<DMEM_SIZE); + printf ("Allocated %d bytes memory and\n",1<<MEM_SIZE); } static void init_system () { - if (!State.imem) + if (!State.mem) sim_size(1); } @@ -277,7 +256,7 @@ sim_write (addr, buffer, size) /* printf ("sim_write %d bytes to 0x%x\n",size,addr); */ for (i = 0; i < size; i++) { - State.imem[i+addr] = buffer[i]; + State.mem[i+addr] = buffer[i]; } return size; } @@ -486,7 +465,7 @@ sim_read (addr, buffer, size) int i; for (i = 0; i < size; i++) { - buffer[i] = State.imem[addr + i]; + buffer[i] = State.mem[addr + i]; } return size; } diff --git a/sim/v850/simops.c b/sim/v850/simops.c index e305602..8a0bc98 100644 --- a/sim/v850/simops.c +++ b/sim/v850/simops.c @@ -2,19 +2,134 @@ #include "v850_sim.h" #include "simops.h" +/* sld.b */ void -OP_10760 () +OP_300 () { } +/* sld.h */ void -OP_C7C0 () +OP_400 () +{ +} + +/* sld.w */ +void +OP_500 () { } +/* sst.b */ +void +OP_380 () +{ +} + +/* sst.h */ +void +OP_480 () +{ +} + +/* sst.w */ +void +OP_501 () +{ +} + +/* ld.b */ +void +OP_700 () +{ + unsigned int op0, op1, op2; + int result, temp; + + op0 = State.regs[OP[0]]; + temp = OP[2]; + temp = (temp << 16) >> 16; + op2 = temp; + result = get_byte (State.mem + op0 + op2); + result = (result << 24) >> 24; + State.regs[OP[1]] = result; +} + +/* ld.h */ +void +OP_720 () +{ + unsigned int op0, op1, op2; + int result, temp; + + op0 = State.regs[OP[0]]; + temp = (temp << 16) >> 16; + temp &= ~0x1; + op2 = temp; + result = get_half (State.mem + op0 + op2); + result = (result << 16) >> 16; + State.regs[OP[1]] = result; +} + +/* ld.w */ +void +OP_10720 () +{ + unsigned int op0, op1, op2; + int result, temp; + + op0 = State.regs[OP[0]]; + temp = (temp << 16) >> 16; + temp &= ~0x1; + op2 = temp; + result = get_word (State.mem + op0 + op2); + State.regs[OP[1]] = result; +} + +/* st.b */ +void +OP_740 () +{ + unsigned int op0, op1, op2; + int result, temp; + + op0 = State.regs[OP[0]]; + op1 = State.regs[OP[1]]; + temp = OP[2]; + temp = (temp << 16) >> 16; + op2 = temp; + put_byte (State.mem + op0 + op2, op1); +} + +/* st.h */ void OP_760 () { + unsigned int op0, op1, op2; + int result, temp; + + op0 = State.regs[OP[0]]; + op1 = State.regs[OP[1]]; + temp = OP[2]; + temp &= ~0x1; + temp = (temp << 16) >> 16; + op2 = temp; + put_half (State.mem + op0 + op2, op1); +} + +/* st.w */ +void +OP_10760 () +{ + unsigned int op0, op1, op2; + int result, temp; + + op0 = State.regs[OP[0]]; + op1 = State.regs[OP[1]]; + temp = OP[2]; + temp &= ~0x1; + temp = (temp << 16) >> 16; + op2 = temp; + put_word (State.mem + op0 + op2, op1); } /* bv disp9 */ @@ -823,26 +938,6 @@ OP_160 () State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)); } -void -OP_10720 () -{ -} - -void -OP_720 () -{ -} - -void -OP_87C0 () -{ -} - -void -OP_300 () -{ -} - /* mov reg, reg */ void OP_0 () @@ -883,21 +978,6 @@ OP_640 () State.regs[OP[2]] = State.regs[OP[1]] + value; } -void -OP_7C0 () -{ -} - -void -OP_1687E0 () -{ -} - -void -OP_740 () -{ -} - /* sar zero_extend(imm5),reg1 */ void OP_2A0 () @@ -1030,16 +1110,6 @@ OP_8007E0 () | (cy ? PSW_CY : 0)); } -void -OP_500 () -{ -} - -void -OP_47C0 () -{ -} - /* or reg, reg */ void OP_100 () @@ -1182,18 +1252,27 @@ OP_20 () State.sregs[5] |= ((z ? PSW_Z : 0) | (s ? PSW_S : 0)); } +/* set1 */ void -OP_480 () +OP_7C0 () { } +/* not1 */ void -OP_380 () +OP_47C0 () { } +/* clr1 */ void -OP_501 () +OP_87C0 () +{ +} + +/* tst1 */ +void +OP_C7C0 () { } @@ -1252,13 +1331,3 @@ OP_4007E0 () State.regs[OP[0]] = op0; } -void -OP_400 () -{ -} - -void -OP_700 () -{ -} - |