diff options
| -rw-r--r-- | sim/frv/cache.c | 2 | ||||
| -rw-r--r-- | sim/frv/profile-fr400.c | 11 | ||||
| -rw-r--r-- | sim/frv/profile-fr500.c | 2 |
3 files changed, 0 insertions, 15 deletions
diff --git a/sim/frv/cache.c b/sim/frv/cache.c index 76f762f..b4f33f1 100644 --- a/sim/frv/cache.c +++ b/sim/frv/cache.c @@ -362,7 +362,6 @@ read_data_from_memory (SIM_CPU *current_cpu, SI address, char *buffer, static void fill_line_from_memory (FRV_CACHE *cache, FRV_CACHE_TAG *tag, SI address) { - PCADDR pc; int line_alignment; SI read_address; SIM_CPU *current_cpu = cache->cpu; @@ -382,7 +381,6 @@ fill_line_from_memory (FRV_CACHE *cache, FRV_CACHE_TAG *tag, SI address) tag->line = cache->data_storage + (line_index * cache->line_size); } - pc = CPU_PC_GET (current_cpu); line_alignment = cache->line_size - 1; read_address = address & ~line_alignment; read_data_from_memory (current_cpu, read_address, tag->line, diff --git a/sim/frv/profile-fr400.c b/sim/frv/profile-fr400.c index 58ad8c8..31e2517 100644 --- a/sim/frv/profile-fr400.c +++ b/sim/frv/profile-fr400.c @@ -632,7 +632,6 @@ frvbf_model_fr400_u_media_1 (SIM_CPU *cpu, const IDESC *idesc, { int cycles; FRV_PROFILE_STATE *ps; - const CGEN_INSN *insn; int busy_adjustment[] = {0, 0}; int *fr; @@ -643,7 +642,6 @@ frvbf_model_fr400_u_media_1 (SIM_CPU *cpu, const IDESC *idesc, cycles = idesc->timing->units[unit_num].done; ps = CPU_PROFILE_STATE (cpu); - insn = idesc->idata; /* The latency of the registers may be less than previously recorded, depending on how they were used previously. @@ -1673,9 +1671,7 @@ frvbf_model_fr400_u_media_4 (SIM_CPU *cpu, const IDESC *idesc, { int cycles; FRV_PROFILE_STATE *ps; - const CGEN_INSN *insn; int busy_adjustment[] = {0}; - int *fr; if (model_insn == FRV_INSN_MODEL_PASS_1) return 0; @@ -1684,7 +1680,6 @@ frvbf_model_fr400_u_media_4 (SIM_CPU *cpu, const IDESC *idesc, cycles = idesc->timing->units[unit_num].done; ps = CPU_PROFILE_STATE (cpu); - insn = idesc->idata; /* The latency of the registers may be less than previously recorded, depending on how they were used previously. @@ -1709,7 +1704,6 @@ frvbf_model_fr400_u_media_4 (SIM_CPU *cpu, const IDESC *idesc, post_wait_for_FR (cpu, out_FRk); /* Restore the busy cycles of the registers we used. */ - fr = ps->fr_busy; /* The latency of the output register will be at least the latency of the other inputs. Once initiated, post-processing will take 1 cycle. */ @@ -1751,7 +1745,6 @@ frvbf_model_fr400_u_media_4_acc_dual (SIM_CPU *cpu, const IDESC *idesc, { int cycles; FRV_PROFILE_STATE *ps; - const CGEN_INSN *insn; INT ACC40Si_1; INT FRk_1; @@ -1765,8 +1758,6 @@ frvbf_model_fr400_u_media_4_acc_dual (SIM_CPU *cpu, const IDESC *idesc, ACC40Si_1 = DUAL_REG (in_ACC40Si); FRk_1 = DUAL_REG (out_FRk); - insn = idesc->idata; - /* The post processing must wait if there is a dependency on a FR which is not ready yet. */ ps->post_wait = cycles; @@ -1802,7 +1793,6 @@ frvbf_model_fr400_u_media_6 (SIM_CPU *cpu, const IDESC *idesc, { int cycles; FRV_PROFILE_STATE *ps; - const CGEN_INSN *insn; int busy_adjustment[] = {0}; int *fr; @@ -1813,7 +1803,6 @@ frvbf_model_fr400_u_media_6 (SIM_CPU *cpu, const IDESC *idesc, cycles = idesc->timing->units[unit_num].done; ps = CPU_PROFILE_STATE (cpu); - insn = idesc->idata; /* The latency of the registers may be less than previously recorded, depending on how they were used previously. diff --git a/sim/frv/profile-fr500.c b/sim/frv/profile-fr500.c index 9d268ce..0593aef 100644 --- a/sim/frv/profile-fr500.c +++ b/sim/frv/profile-fr500.c @@ -2043,7 +2043,6 @@ frvbf_model_fr500_u_media (SIM_CPU *cpu, const IDESC *idesc, { int cycles; FRV_PROFILE_STATE *ps; - const CGEN_INSN *insn; int is_media_s1; int is_media_s2; int busy_adjustment[] = {0, 0, 0}; @@ -2057,7 +2056,6 @@ frvbf_model_fr500_u_media (SIM_CPU *cpu, const IDESC *idesc, cycles = idesc->timing->units[unit_num].done; ps = CPU_PROFILE_STATE (cpu); - insn = idesc->idata; /* If the previous use of the registers was a media op, then their latency will be less than previously recorded. |