diff options
| -rw-r--r-- | bfd/ChangeLog | 5 | ||||
| -rw-r--r-- | bfd/elf32-arm.c | 2 | ||||
| -rw-r--r-- | binutils/ChangeLog | 5 | ||||
| -rw-r--r-- | binutils/readelf.c | 3 | ||||
| -rw-r--r-- | gas/ChangeLog | 24 | ||||
| -rw-r--r-- | gas/config/tc-arm.c | 108 | ||||
| -rw-r--r-- | gas/testsuite/ChangeLog | 7 | ||||
| -rw-r--r-- | gas/testsuite/gas/arm/any-armv8m.d | 2 | ||||
| -rw-r--r-- | gas/testsuite/gas/arm/archv8m-base.d | 47 | ||||
| -rw-r--r-- | gas/testsuite/gas/arm/armv8m.base-idiv.d | 13 | ||||
| -rw-r--r-- | gas/testsuite/gas/arm/attr-march-armv8m.base.d | 13 | ||||
| -rw-r--r-- | include/elf/ChangeLog | 4 | ||||
| -rw-r--r-- | include/elf/arm.h | 1 | ||||
| -rw-r--r-- | include/opcode/ChangeLog | 29 | ||||
| -rw-r--r-- | include/opcode/arm.h | 49 | ||||
| -rw-r--r-- | opcodes/ChangeLog | 6 | ||||
| -rw-r--r-- | opcodes/arm-dis.c | 28 |
17 files changed, 290 insertions, 56 deletions
diff --git a/bfd/ChangeLog b/bfd/ChangeLog index aea882b..65e9bfb 100644 --- a/bfd/ChangeLog +++ b/bfd/ChangeLog @@ -1,5 +1,10 @@ 2015-12-24 Thomas Preud'homme <thomas.preudhomme@arm.com> + (tag_cpu_arch_combine): Adjust comment in v4t_plus_v6_m with regards + to merging with ARMv8-M Baseline. + +2015-12-24 Thomas Preud'homme <thomas.preudhomme@arm.com> + (tag_cpu_arch_combine): Adjust v4t_plus_v6_m and comb array to account for new TAG_CPU_ARCH_V4T_PLUS_V6_M value. Deal with NULL values in comb array. diff --git a/bfd/elf32-arm.c b/bfd/elf32-arm.c index 93f32f3..415090f 100644 --- a/bfd/elf32-arm.c +++ b/bfd/elf32-arm.c @@ -12293,7 +12293,7 @@ tag_cpu_arch_combine (bfd *ibfd, int oldtag, int *secondary_compat_out, T(V7E_M), /* V7E_M. */ T(V8), /* V8. */ -1, /* Unused. */ - -1, /* Unused. */ + -1, /* V8-M BASELINE. */ -1, /* V8-M MAINLINE. */ T(V4T_PLUS_V6_M) /* V4T plus V6_M. */ }; diff --git a/binutils/ChangeLog b/binutils/ChangeLog index 33a2bbf..ea7a779 100644 --- a/binutils/ChangeLog +++ b/binutils/ChangeLog @@ -1,5 +1,10 @@ 2015-12-24 Thomas Preud'homme <thomas.preudhomme@arm.com> + * readelf.c (arm_attr_tag_CPU_arch): Add ARMv8-M Baseline Tag_CPU_arch + value. + +2015-12-24 Thomas Preud'homme <thomas.preudhomme@arm.com> + * readelf.c (arm_attr_tag_CPU_arch): Add ARMv8-M Mainline Tag_CPU_arch value. (arm_attr_tag_THUMB_ISA_use): Add ARMv8-M Mainline Tag_THUMB_ISA_use diff --git a/binutils/readelf.c b/binutils/readelf.c index e1ce551..5986456 100644 --- a/binutils/readelf.c +++ b/binutils/readelf.c @@ -12731,7 +12731,8 @@ typedef struct static const char * arm_attr_tag_CPU_arch[] = {"Pre-v4", "v4", "v4T", "v5T", "v5TE", "v5TEJ", "v6", "v6KZ", "v6T2", - "v6K", "v7", "v6-M", "v6S-M", "v7E-M", "v8", "", "", "v8-M.mainline"}; + "v6K", "v7", "v6-M", "v6S-M", "v7E-M", "v8", "", "v8-M.baseline", + "v8-M.mainline"}; static const char * arm_attr_tag_ARM_ISA_use[] = {"No", "Yes"}; static const char * arm_attr_tag_THUMB_ISA_use[] = {"No", "Thumb-1", "Thumb-2", "Yes"}; diff --git a/gas/ChangeLog b/gas/ChangeLog index a4c0db6..f056312 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,5 +1,29 @@ 2015-12-24 Thomas Preud'homme <thomas.preudhomme@arm.com> + * config/tc-arm.c (arm_ext_v6t2_v8m): New feature for instructions + shared between ARMv6T2 and ARMv8-M. + (move_or_literal_pool): Check mov.w/mvn and movw availability against + arm_ext_v6t2 and arm_ext_v6t2_v8m respectively instead of checking + arm_arch_t2. + (do_t_branch): Error out for wide conditional branch instructions if + targetting ARMv8-M Baseline. + (non_v6t2_wide_only_insn): Add the logic for new wide-only instructions + in ARMv8-M Baseline. + (wide_insn_ok): New function. + (md_assemble): Use wide_insn_ok instead of non_v6t2_wide_only_insn and + adapt error message for unsupported wide instruction to ARMv8-M + Baseline. + (insns): Reorganize instructions shared by ARMv8-M Baseline and + ARMv6t2 architecture. + (arm_cpus): Set feature bit ARM_EXT2_V6T2_V8M for marvell-pj4 and + marvell-whitney cores. + (arm_archs): Define armv8-m.base architecture. + (cpu_arch_ver): Define ARM_ARCH_V8M_BASE architecture version. + (aeabi_set_public_attributes): Add logic to set Tag_CPU_arch to 17 for + ARMv8-M Mainline. Set Tag_DIV_use for ARMv8-M Baseline as well. + +2015-12-24 Thomas Preud'homme <thomas.preudhomme@arm.com> + * config/tc-arm.c (arm_ext_m): Include ARMv8-M. (arm_ext_v8m): New feature for ARMv8-M. (arm_ext_atomics): New feature for ARMv8 atomics. diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c index 7992360..d23181c 100644 --- a/gas/config/tc-arm.c +++ b/gas/config/tc-arm.c @@ -209,6 +209,8 @@ static const arm_feature_set arm_ext_adiv = ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV); static const arm_feature_set arm_ext_virt = ARM_FEATURE_CORE_LOW (ARM_EXT_VIRT); static const arm_feature_set arm_ext_pan = ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN); static const arm_feature_set arm_ext_v8m = ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8M); +static const arm_feature_set arm_ext_v6t2_v8m = + ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M); /* Instructions shared between ARMv8-A and ARMv8-M. */ static const arm_feature_set arm_ext_atomics = ARM_FEATURE_CORE_HIGH (ARM_EXT2_ATOMICS); @@ -7873,7 +7875,8 @@ move_or_literal_pool (int i, enum lit_type t, bfd_boolean mode_3) return TRUE; } - if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2)) + if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2) + || ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2_v8m)) { /* Check if on thumb2 it can be done with a mov.w, mvn or movw instruction. */ @@ -7892,7 +7895,8 @@ move_or_literal_pool (int i, enum lit_type t, bfd_boolean mode_3) /* The number can be loaded with a mov.w or mvn instruction. */ - if (newimm != (unsigned int) FAIL) + if (newimm != (unsigned int) FAIL + && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2)) { inst.instruction = (0xf04f0000 /* MOV.W. */ | (inst.operands[i].reg << 8)); @@ -7904,7 +7908,8 @@ move_or_literal_pool (int i, enum lit_type t, bfd_boolean mode_3) return TRUE; } /* The number can be loaded with a movw instruction. */ - else if ((v & ~0xFFFF) == 0) + else if ((v & ~0xFFFF) == 0 + && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2_v8m)) { int imm = v & 0xFFFF; @@ -10939,6 +10944,10 @@ do_t_branch (void) reloc = BFD_RELOC_THUMB_PCREL_BRANCH25; else { + constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2), + _("selected architecture does not support " + "wide conditional branch instruction")); + gas_assert (cond != 0xF); inst.instruction |= cond << 22; reloc = BFD_RELOC_THUMB_PCREL_BRANCH20; @@ -17809,11 +17818,12 @@ in_it_block (void) return now_it.state != OUTSIDE_IT_BLOCK; } -/* Whether OPCODE only has T32 encoding and makes build attribute - Tag_THUMB_ISA_use be set to 1 if assembled without any cpu or arch info. */ +/* Whether OPCODE only has T32 encoding. Since this function is only used by + t32_insn_ok, OPCODE enabled by v6t2 extension bit do not need to be listed + here, hence the "known" in the function name. */ static bfd_boolean -t1_isa_t32_only_insn (const struct asm_opcode *opcode) +known_t32_only_insn (const struct asm_opcode *opcode) { /* Original Thumb-1 wide instruction. */ if (opcode->tencode == do_t_blx @@ -17822,6 +17832,39 @@ t1_isa_t32_only_insn (const struct asm_opcode *opcode) || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_barrier)) return TRUE; + /* Wide-only instruction added to ARMv8-M. */ + if (ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_v8m) + || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_atomics) + || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_v6t2_v8m) + || ARM_CPU_HAS_FEATURE (*opcode->tvariant, arm_ext_div)) + return TRUE; + + return FALSE; +} + +/* Whether wide instruction variant can be used if available for a valid OPCODE + in ARCH. */ + +static bfd_boolean +t32_insn_ok (arm_feature_set arch, const struct asm_opcode *opcode) +{ + if (known_t32_only_insn (opcode)) + return TRUE; + + /* Instruction with narrow and wide encoding added to ARMv8-M. Availability + of variant T3 of B.W is checked in do_t_branch. */ + if (ARM_CPU_HAS_FEATURE (arch, arm_ext_v8m) + && opcode->tencode == do_t_branch) + return TRUE; + + /* Wide instruction variants of all instructions with narrow *and* wide + variants become available with ARMv6t2. Other opcodes are either + narrow-only or wide-only and are thus available if OPCODE is valid. */ + if (ARM_CPU_HAS_FEATURE (arch, arm_ext_v6t2)) + return TRUE; + + /* OPCODE with narrow only instruction variant or wide variant not + available. */ return FALSE; } @@ -17893,14 +17936,18 @@ md_assemble (char *str) Only instructions with narrow and wide variants need to be handled but selecting all non wide-only instructions is easier. */ if (!ARM_CPU_HAS_FEATURE (variant, arm_ext_v6t2) - && !t1_isa_t32_only_insn (opcode)) + && !t32_insn_ok (variant, opcode)) { if (inst.size_req == 0) inst.size_req = 2; else if (inst.size_req == 4) { - as_bad (_("selected processor does not support `%s' in Thumb-2 " - "mode"), str); + if (ARM_CPU_HAS_FEATURE (variant, arm_ext_v8m)) + as_bad (_("selected processor does not support 32bit wide " + "variant of instruction `%s'"), str); + else + as_bad (_("selected processor does not support `%s' in " + "Thumb-2 mode"), str); return; } } @@ -17939,7 +17986,11 @@ md_assemble (char *str) set those bits when Thumb-2 32-bit instructions are seen. The impact of relaxable instructions will be considered later after we finish all relaxation. */ - if (inst.size == 4 && !t1_isa_t32_only_insn (opcode)) + if (ARM_FEATURE_CORE_EQUAL (cpu_variant, arm_arch_any)) + variant = arm_arch_none; + else + variant = cpu_variant; + if (inst.size == 4 && !t32_insn_ok (variant, opcode)) ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, arm_ext_v6t2); @@ -18906,11 +18957,14 @@ static const struct asm_opcode insns[] = TUF("setend", 1010000, b650, 1, (ENDI), setend, t_setend), #undef THUMB_VARIANT -#define THUMB_VARIANT & arm_ext_v6t2 +#define THUMB_VARIANT & arm_ext_v6t2_v8m TCE("ldrex", 1900f9f, e8500f00, 2, (RRnpc_npcsp, ADDR), ldrex, t_ldrex), TCE("strex", 1800f90, e8400000, 3, (RRnpc_npcsp, RRnpc_npcsp, ADDR), strex, t_strex), +#undef THUMB_VARIANT +#define THUMB_VARIANT & arm_ext_v6t2 + TUF("mcrr2", c400000, fc400000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), TUF("mrrc2", c500000, fc500000, 5, (RCP, I15b, RRnpc, RRnpc, RCN), co_reg2c, co_reg2c), @@ -19056,7 +19110,7 @@ static const struct asm_opcode insns[] = RRnpcb), strexd, t_strexd), #undef THUMB_VARIANT -#define THUMB_VARIANT & arm_ext_v6t2 +#define THUMB_VARIANT & arm_ext_v6t2_v8m TCE("ldrexb", 1d00f9f, e8d00f4f, 2, (RRnpc_npcsp,RRnpcb), rd_rn, rd_rn), TCE("ldrexh", 1f00f9f, e8d00f5f, 2, (RRnpc_npcsp, RRnpcb), @@ -19100,8 +19154,6 @@ static const struct asm_opcode insns[] = TCE("ubfx", 7e00050, f3c00000, 4, (RR, RR, I31, I32), bfx, t_bfx), TCE("mls", 0600090, fb000010, 4, (RRnpc, RRnpc, RRnpc, RRnpc), mlas, t_mla), - TCE("movw", 3000000, f2400000, 2, (RRnpc, HALF), mov16, t_mov16), - TCE("movt", 3400000, f2c00000, 2, (RRnpc, HALF), mov16, t_mov16), TCE("rbit", 6ff0f30, fa90f0a0, 2, (RR, RR), rd_rm, t_rbit), TC3("ldrht", 03000b0, f8300e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt), @@ -19109,6 +19161,11 @@ static const struct asm_opcode insns[] = TC3("ldrsbt", 03000d0, f9100e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt), TC3("strht", 02000b0, f8200e00, 2, (RRnpc_npcsp, ADDR), ldsttv4, t_ldstt), +#undef THUMB_VARIANT +#define THUMB_VARIANT & arm_ext_v6t2_v8m + TCE("movw", 3000000, f2400000, 2, (RRnpc, HALF), mov16, t_mov16), + TCE("movt", 3400000, f2c00000, 2, (RRnpc, HALF), mov16, t_mov16), + /* Thumb-only instructions. */ #undef ARM_VARIANT #define ARM_VARIANT NULL @@ -19120,6 +19177,8 @@ static const struct asm_opcode insns[] = -mimplicit-it=[never | arm] modes. */ #undef ARM_VARIANT #define ARM_VARIANT & arm_ext_v1 +#undef THUMB_VARIANT +#define THUMB_VARIANT & arm_ext_v6t2 TUE("it", bf08, bf08, 1, (COND), it, t_it), TUE("itt", bf0c, bf0c, 1, (COND), it, t_it), @@ -24888,11 +24947,13 @@ static const struct arm_cpu_option_table arm_cpus[] = ARM_CPU_OPT ("ep9312", ARM_FEATURE_LOW (ARM_AEXT_V4T, ARM_CEXT_MAVERICK), FPU_ARCH_MAVERICK, "ARM920T"), /* Marvell processors. */ - ARM_CPU_OPT ("marvell-pj4", ARM_FEATURE_CORE_LOW (ARM_AEXT_V7A | ARM_EXT_MP - | ARM_EXT_SEC), + ARM_CPU_OPT ("marvell-pj4", ARM_FEATURE_CORE (ARM_AEXT_V7A | ARM_EXT_MP + | ARM_EXT_SEC, + ARM_EXT2_V6T2_V8M), FPU_ARCH_VFP_V3D16, NULL), - ARM_CPU_OPT ("marvell-whitney", ARM_FEATURE_CORE_LOW (ARM_AEXT_V7A | ARM_EXT_MP - | ARM_EXT_SEC), + ARM_CPU_OPT ("marvell-whitney", ARM_FEATURE_CORE (ARM_AEXT_V7A | ARM_EXT_MP + | ARM_EXT_SEC, + ARM_EXT2_V6T2_V8M), FPU_ARCH_NEON_VFP_V4, NULL), /* APM X-Gene family. */ ARM_CPU_OPT ("xgene1", ARM_ARCH_V8A, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8, @@ -24962,6 +25023,7 @@ static const struct arm_arch_option_table arm_archs[] = ARM_ARCH_OPT ("armv7-r", ARM_ARCH_V7R, FPU_ARCH_VFP), ARM_ARCH_OPT ("armv7-m", ARM_ARCH_V7M, FPU_ARCH_VFP), ARM_ARCH_OPT ("armv7e-m", ARM_ARCH_V7EM, FPU_ARCH_VFP), + ARM_ARCH_OPT ("armv8-m.base", ARM_ARCH_V8M_BASE, FPU_ARCH_VFP), ARM_ARCH_OPT ("armv8-m.main", ARM_ARCH_V8M_MAIN, FPU_ARCH_VFP), ARM_ARCH_OPT ("armv8-a", ARM_ARCH_V8A, FPU_ARCH_VFP), ARM_ARCH_OPT ("armv8.1-a", ARM_ARCH_V8_1A, FPU_ARCH_VFP), @@ -25582,6 +25644,7 @@ static const cpu_arch_ver_table cpu_arch_ver[] = {10, ARM_ARCH_V7R}, {10, ARM_ARCH_V7M}, {14, ARM_ARCH_V8A}, + {16, ARM_ARCH_V8M_BASE}, {17, ARM_ARCH_V8M_MAIN}, {0, ARM_ARCH_NONE} }; @@ -25615,6 +25678,7 @@ aeabi_set_public_attributes (void) int fp16_optional = 0; arm_feature_set flags; arm_feature_set tmp; + arm_feature_set arm_arch_v8m_base = ARM_ARCH_V8M_BASE; const cpu_arch_ver_table *p; /* Choose the architecture based on the capabilities of the requested cpu @@ -25669,6 +25733,10 @@ aeabi_set_public_attributes (void) && ARM_CPU_HAS_FEATURE (flags, arm_ext_v6_dsp)) arch = TAG_CPU_ARCH_V7E_M; + ARM_CLEAR_FEATURE (tmp, flags, arm_arch_v8m_base); + if (arch == TAG_CPU_ARCH_V8M_BASE && ARM_CPU_HAS_FEATURE (tmp, arm_arch_any)) + arch = TAG_CPU_ARCH_V8M_MAIN; + /* In cpu_arch_ver ARMv8-A is before ARMv8-M for atomics to be detected as coming from ARMv8-A. However, since ARMv8-A has more instructions than ARMv8-M, -march=all must be detected as ARMv8-A. */ @@ -25799,7 +25867,9 @@ aeabi_set_public_attributes (void) by the base architecture. For new architectures we will have to check these tests. */ - gas_assert (arch <= TAG_CPU_ARCH_V8 || arch == TAG_CPU_ARCH_V8M_MAIN); + gas_assert (arch <= TAG_CPU_ARCH_V8 + || (arch >= TAG_CPU_ARCH_V8M_BASE + && arch <= TAG_CPU_ARCH_V8M_MAIN)); if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v8) || ARM_CPU_HAS_FEATURE (flags, arm_ext_v8m)) aeabi_set_attribute_int (Tag_DIV_use, 0); diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog index baad934..15da433 100644 --- a/gas/testsuite/ChangeLog +++ b/gas/testsuite/ChangeLog @@ -1,5 +1,12 @@ 2015-12-24 Thomas Preud'homme <thomas.preudhomme@arm.com> + * gas/arm/archv8m-base.d: New file. + * gas/arm/attr-march-armv8m.base.d: Likewise. + * gas/arm/armv8m.base-idiv.d: Likewise. + * gas/arm/any-armv8m.d: Adapt to deal with ARMv8-M Baseline. + +2015-12-24 Thomas Preud'homme <thomas.preudhomme@arm.com> + * gas/arm/archv8m.s: New file. * gas/arm/archv8m-main.d: Likewise. * gas/arm/attr-march-armv8m.main.d: Likewise. diff --git a/gas/testsuite/gas/arm/any-armv8m.d b/gas/testsuite/gas/arm/any-armv8m.d index fc0b22d..9dc5533 100644 --- a/gas/testsuite/gas/arm/any-armv8m.d +++ b/gas/testsuite/gas/arm/any-armv8m.d @@ -7,6 +7,6 @@ Attribute Section: aeabi File Attributes - Tag_CPU_arch: v8-M.mainline + Tag_CPU_arch: v8-M.baseline Tag_CPU_arch_profile: Microcontroller Tag_THUMB_ISA_use: Yes diff --git a/gas/testsuite/gas/arm/archv8m-base.d b/gas/testsuite/gas/arm/archv8m-base.d new file mode 100644 index 0000000..00331c3 --- /dev/null +++ b/gas/testsuite/gas/arm/archv8m-base.d @@ -0,0 +1,47 @@ +#name: ARM V8-M baseline instructions +#source: archv8m.s +#as: -march=armv8-m.base +#objdump: -dr --prefix-addresses --show-raw-insn + +.*: +file format .*arm.* + +Disassembly of section .text: +0+.* <[^>]*> 47a0 blx r4 +0+.* <[^>]*> 47c8 blx r9 +0+.* <[^>]*> 4720 bx r4 +0+.* <[^>]*> 4748 bx r9 +0+.* <[^>]*> e841 f000 tt r0, r1 +0+.* <[^>]*> e849 f800 tt r8, r9 +0+.* <[^>]*> e841 f040 ttt r0, r1 +0+.* <[^>]*> e849 f840 ttt r8, r9 +0+.* <[^>]*> f24f 1023 movw r0, #61731 ; 0xf123 +0+.* <[^>]*> f24f 1823 movw r8, #61731 ; 0xf123 +0+.* <[^>]*> f2cf 1023 movt r0, #61731 ; 0xf123 +0+.* <[^>]*> f2cf 1823 movt r8, #61731 ; 0xf123 +0+.* <[^>]*> b154 cbz r4, 0+.* <[^>]*> +0+.* <[^>]*> b94c cbnz r4, 0+.* <[^>]*> +0+.* <[^>]*> f000 b808 b.w 0+.* <[^>]*> +0+.* <[^>]*> fb91 f0f2 sdiv r0, r1, r2 +0+.* <[^>]*> fb99 f8fa sdiv r8, r9, sl +0+.* <[^>]*> fbb1 f0f2 udiv r0, r1, r2 +0+.* <[^>]*> fbb9 f8fa udiv r8, r9, sl +0+.* <[^>]*> 4408 add r0, r1 +0+.* <[^>]*> f3bf 8f2f clrex +0+.* <[^>]*> e851 0f01 ldrex r0, \[r1, #4\] +0+.* <[^>]*> e8d1 0f4f ldrexb r0, \[r1\] +0+.* <[^>]*> e8d1 0f5f ldrexh r0, \[r1\] +0+.* <[^>]*> e842 1001 strex r0, r1, \[r2, #4\] +0+.* <[^>]*> e8c2 1f40 strexb r0, r1, \[r2\] +0+.* <[^>]*> e8c2 1f50 strexh r0, r1, \[r2\] +0+.* <[^>]*> e8d1 0faf lda r0, \[r1\] +0+.* <[^>]*> e8d1 0f8f ldab r0, \[r1\] +0+.* <[^>]*> e8d1 0f9f ldah r0, \[r1\] +0+.* <[^>]*> e8c1 0faf stl r0, \[r1\] +0+.* <[^>]*> e8c1 0f8f stlb r0, \[r1\] +0+.* <[^>]*> e8c1 0f9f stlh r0, \[r1\] +0+.* <[^>]*> e8d1 0fef ldaex r0, \[r1\] +0+.* <[^>]*> e8d1 0fcf ldaexb r0, \[r1\] +0+.* <[^>]*> e8d1 0fdf ldaexh r0, \[r1\] +0+.* <[^>]*> e8c2 1fe0 stlex r0, r1, \[r2\] +0+.* <[^>]*> e8c2 1fc0 stlexb r0, r1, \[r2\] +0+.* <[^>]*> e8c2 1fd0 stlexh r0, r1, \[r2\] diff --git a/gas/testsuite/gas/arm/armv8m.base-idiv.d b/gas/testsuite/gas/arm/armv8m.base-idiv.d new file mode 100644 index 0000000..241a0af --- /dev/null +++ b/gas/testsuite/gas/arm/armv8m.base-idiv.d @@ -0,0 +1,13 @@ +# name: attributes for 'armv8-m.base' CPU with Thumb integer divide +# source: any-idiv.s +# as: -march=armv8-m.base +# readelf: -A +# This test is only valid on EABI based ports. +# target: *-*-*eabi* *-*-nacl* + +Attribute Section: aeabi +File Attributes + Tag_CPU_name: "8-M.BASE" + Tag_CPU_arch: v8-M.baseline + Tag_CPU_arch_profile: Microcontroller + Tag_THUMB_ISA_use: Yes diff --git a/gas/testsuite/gas/arm/attr-march-armv8m.base.d b/gas/testsuite/gas/arm/attr-march-armv8m.base.d new file mode 100644 index 0000000..d661cab --- /dev/null +++ b/gas/testsuite/gas/arm/attr-march-armv8m.base.d @@ -0,0 +1,13 @@ +# name: attributes for -march=armv8-m.base +# source: blank.s +# as: -march=armv8-m.base +# readelf: -A +# This test is only valid on EABI based ports. +# target: *-*-*eabi* *-*-nacl* + +Attribute Section: aeabi +File Attributes + Tag_CPU_name: "8-M.BASE" + Tag_CPU_arch: v8-M.baseline + Tag_CPU_arch_profile: Microcontroller + Tag_THUMB_ISA_use: Yes diff --git a/include/elf/ChangeLog b/include/elf/ChangeLog index b083168..045d843 100644 --- a/include/elf/ChangeLog +++ b/include/elf/ChangeLog @@ -1,5 +1,9 @@ 2015-12-24 Thomas Preud'homme <thomas.preudhomme@arm.com> + * arm.h (TAG_CPU_ARCH_V8M_BASE): Declare. + +2015-12-24 Thomas Preud'homme <thomas.preudhomme@arm.com> + * arm.h (TAG_CPU_ARCH_V8M_MAIN): Declare. (MAX_TAG_CPU_ARCH): Define to TAG_CPU_ARCH_V8M_MAIN. (TAG_CPU_ARCH_V4T_PLUS_V6_M): Define to unused value 15. diff --git a/include/elf/arm.h b/include/elf/arm.h index 631cd98e..b5b8eca 100644 --- a/include/elf/arm.h +++ b/include/elf/arm.h @@ -106,6 +106,7 @@ #define TAG_CPU_ARCH_V6S_M 12 #define TAG_CPU_ARCH_V7E_M 13 #define TAG_CPU_ARCH_V8 14 +#define TAG_CPU_ARCH_V8M_BASE 16 #define TAG_CPU_ARCH_V8M_MAIN 17 #define MAX_TAG_CPU_ARCH TAG_CPU_ARCH_V8M_MAIN /* Pseudo-architecture to allow objects to be compatible with the subset of diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog index a3b6a182..b9d524d 100644 --- a/include/opcode/ChangeLog +++ b/include/opcode/ChangeLog @@ -1,5 +1,34 @@ 2015-12-24 Thomas Preud'homme <thomas.preudhomme@arm.com> + * arm.h (ARM_EXT2_V6T2_V8M): New extension bit. + (ARM_AEXT2_V8A): New architecture extension bitfield. + (ARM_AEXT2_V8_1A): Use ARM_AEXT2_V8A instead of ARM_EXT2_ATOMICS. + (ARM_AEXT_V8M_BASE): New architecture extension bitfield. + (ARM_AEXT2_V8M): Add extension bit ARM_EXT2_V6T2_V8M. + (ARM_ARCH_V6T2): Use ARM_EXT2_V6T2_V8M for the second extension + bitfield. + (ARM_ARCH_V6KT2): Likewise. + (ARM_ARCH_V6ZT2): Likewise. + (ARM_ARCH_V6KZT2): Likewise. + (ARM_ARCH_V7): Likewise. + (ARM_ARCH_V7A): Likewise. + (ARM_ARCH_V7VE): Likewise. + (ARM_ARCH_V7R): Likewise. + (ARM_ARCH_V7M): Likewise. + (ARM_ARCH_V7EM): Likewise. + (ARM_ARCH_V8A): Likewise. + (ARM_ARCH_V8M_BASE): New architecture bitfield. + (ARM_ARCH_THUMB2): Include instructions shared by ARMv6t2 and ARMv8-M. + (ARM_ARCH_V7A_SEC): Use ARM_EXT2_V6T2_V8M for the second extension + bitfield and reindent. + (ARM_ARCH_V7A_MP_SEC): Likewise. + (ARM_ARCH_V7R_IDIV): Likewise. + (ARM_ARCH_V8A_FP): Use ARM_AEXT2_V8A instead of ARM_EXT2_ATOMICS. + (ARM_ARCH_V8A_SIMD): Likewise. + (ARM_ARCH_V8A_CRYPTOV1): Likewise. + +2015-12-24 Thomas Preud'homme <thomas.preudhomme@arm.com> + * arm.h (ARM_EXT2_ATOMICS): New extension bit. (ARM_EXT2_V8M): Likewise. (ARM_EXT_V8): Adjust comment with regards to atomics and remove diff --git a/include/opcode/arm.h b/include/opcode/arm.h index 2edcfe3..81ec2c5 100644 --- a/include/opcode/arm.h +++ b/include/opcode/arm.h @@ -60,6 +60,7 @@ #define ARM_EXT2_V8_2A 0x00000002 /* ARM V8.2A. */ #define ARM_EXT2_V8M 0x00000004 /* ARM V8M. */ #define ARM_EXT2_ATOMICS 0x00000008 /* ARMv8 atomics. */ +#define ARM_EXT2_V6T2_V8M 0x00000010 /* V8M Baseline from V6T2. */ /* Co-processor space extensions. */ #define ARM_CEXT_XSCALE 0x00000001 /* Allow MIA etc. */ @@ -142,10 +143,12 @@ #define ARM_AEXT_V8A \ (ARM_AEXT_V7A | ARM_EXT_MP | ARM_EXT_SEC | ARM_EXT_DIV | ARM_EXT_ADIV \ | ARM_EXT_VIRT | ARM_EXT_V8) -#define ARM_AEXT2_V8_1A (ARM_EXT2_ATOMICS | ARM_EXT2_PAN) +#define ARM_AEXT2_V8A (ARM_EXT2_V6T2_V8M | ARM_EXT2_ATOMICS) +#define ARM_AEXT2_V8_1A (ARM_AEXT2_V8A | ARM_EXT2_PAN) #define ARM_AEXT2_V8_2A (ARM_AEXT2_V8_1A | ARM_EXT2_V8_2A) +#define ARM_AEXT_V8M_BASE (ARM_AEXT_V6SM | ARM_EXT_DIV) #define ARM_AEXT_V8M_MAIN ARM_AEXT_V7M -#define ARM_AEXT2_V8M (ARM_EXT2_V8M | ARM_EXT2_ATOMICS) +#define ARM_AEXT2_V8M (ARM_EXT2_V8M | ARM_EXT2_ATOMICS | ARM_EXT2_V6T2_V8M) /* Processors with specific extensions in the co-processor space. */ #define ARM_ARCH_XSCALE ARM_FEATURE_LOW (ARM_AEXT_V5TE, ARM_CEXT_XSCALE) @@ -243,23 +246,24 @@ #define ARM_ARCH_V6K ARM_FEATURE_CORE_LOW (ARM_AEXT_V6K) #define ARM_ARCH_V6Z ARM_FEATURE_CORE_LOW (ARM_AEXT_V6Z) #define ARM_ARCH_V6KZ ARM_FEATURE_CORE_LOW (ARM_AEXT_V6KZ) -#define ARM_ARCH_V6T2 ARM_FEATURE_CORE_LOW (ARM_AEXT_V6T2) -#define ARM_ARCH_V6KT2 ARM_FEATURE_CORE_LOW (ARM_AEXT_V6KT2) -#define ARM_ARCH_V6ZT2 ARM_FEATURE_CORE_LOW (ARM_AEXT_V6ZT2) -#define ARM_ARCH_V6KZT2 ARM_FEATURE_CORE_LOW (ARM_AEXT_V6KZT2) +#define ARM_ARCH_V6T2 ARM_FEATURE_CORE (ARM_AEXT_V6T2, ARM_EXT2_V6T2_V8M) +#define ARM_ARCH_V6KT2 ARM_FEATURE_CORE (ARM_AEXT_V6KT2, ARM_EXT2_V6T2_V8M) +#define ARM_ARCH_V6ZT2 ARM_FEATURE_CORE (ARM_AEXT_V6ZT2, ARM_EXT2_V6T2_V8M) +#define ARM_ARCH_V6KZT2 ARM_FEATURE_CORE (ARM_AEXT_V6KZT2, ARM_EXT2_V6T2_V8M) #define ARM_ARCH_V6M ARM_FEATURE_CORE_LOW (ARM_AEXT_V6M) #define ARM_ARCH_V6SM ARM_FEATURE_CORE_LOW (ARM_AEXT_V6SM) -#define ARM_ARCH_V7 ARM_FEATURE_CORE_LOW (ARM_AEXT_V7) -#define ARM_ARCH_V7A ARM_FEATURE_CORE_LOW (ARM_AEXT_V7A) -#define ARM_ARCH_V7VE ARM_FEATURE_CORE_LOW (ARM_AEXT_V7VE) -#define ARM_ARCH_V7R ARM_FEATURE_CORE_LOW (ARM_AEXT_V7R) -#define ARM_ARCH_V7M ARM_FEATURE_CORE_LOW (ARM_AEXT_V7M) -#define ARM_ARCH_V7EM ARM_FEATURE_CORE_LOW (ARM_AEXT_V7EM) -#define ARM_ARCH_V8A ARM_FEATURE_CORE (ARM_AEXT_V8A, ARM_EXT2_ATOMICS) +#define ARM_ARCH_V7 ARM_FEATURE_CORE (ARM_AEXT_V7, ARM_EXT2_V6T2_V8M) +#define ARM_ARCH_V7A ARM_FEATURE_CORE (ARM_AEXT_V7A, ARM_EXT2_V6T2_V8M) +#define ARM_ARCH_V7VE ARM_FEATURE_CORE (ARM_AEXT_V7VE, ARM_EXT2_V6T2_V8M) +#define ARM_ARCH_V7R ARM_FEATURE_CORE (ARM_AEXT_V7R, ARM_EXT2_V6T2_V8M) +#define ARM_ARCH_V7M ARM_FEATURE_CORE (ARM_AEXT_V7M, ARM_EXT2_V6T2_V8M) +#define ARM_ARCH_V7EM ARM_FEATURE_CORE (ARM_AEXT_V7EM, ARM_EXT2_V6T2_V8M) +#define ARM_ARCH_V8A ARM_FEATURE_CORE (ARM_AEXT_V8A, ARM_AEXT2_V8A) #define ARM_ARCH_V8_1A ARM_FEATURE (ARM_AEXT_V8A, ARM_AEXT2_V8_1A, \ CRC_EXT_ARMV8) #define ARM_ARCH_V8_2A ARM_FEATURE (ARM_AEXT_V8A, ARM_AEXT2_V8_2A, \ CRC_EXT_ARMV8) +#define ARM_ARCH_V8M_BASE ARM_FEATURE_CORE (ARM_AEXT_V8M_BASE, ARM_AEXT2_V8M) #define ARM_ARCH_V8M_MAIN ARM_FEATURE_CORE (ARM_AEXT_V8M_MAIN, ARM_AEXT2_V8M) /* Some useful combinations: */ @@ -270,26 +274,29 @@ #define FPU_ANY_HARD ARM_FEATURE_COPROC (FPU_FPA | FPU_VFP_HARD | FPU_MAVERICK) /* Extensions containing some Thumb-2 instructions. If any is present, Thumb ISA is Thumb-2. */ -#define ARM_ARCH_THUMB2 ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2 | ARM_EXT_V7 \ - | ARM_EXT_DIV | ARM_EXT_V8) +#define ARM_ARCH_THUMB2 ARM_FEATURE_CORE (ARM_EXT_V6T2 | ARM_EXT_V7 \ + | ARM_EXT_DIV | ARM_EXT_V8, \ + ARM_EXT2_ATOMICS | ARM_EXT2_V6T2_V8M) /* v7-a+sec. */ -#define ARM_ARCH_V7A_SEC ARM_FEATURE_CORE_LOW (ARM_AEXT_V7A | ARM_EXT_SEC) +#define ARM_ARCH_V7A_SEC \ + ARM_FEATURE_CORE (ARM_AEXT_V7A | ARM_EXT_SEC, ARM_EXT2_V6T2_V8M) /* v7-a+mp+sec. */ #define ARM_ARCH_V7A_MP_SEC \ - ARM_FEATURE_CORE_LOW (ARM_AEXT_V7A | ARM_EXT_MP | ARM_EXT_SEC) + ARM_FEATURE_CORE (ARM_AEXT_V7A | ARM_EXT_MP | ARM_EXT_SEC, ARM_EXT2_V6T2_V8M) /* v7-r+idiv. */ -#define ARM_ARCH_V7R_IDIV ARM_FEATURE_CORE_LOW (ARM_AEXT_V7R | ARM_EXT_ADIV) +#define ARM_ARCH_V7R_IDIV \ + ARM_FEATURE_CORE (ARM_AEXT_V7R | ARM_EXT_ADIV, ARM_EXT2_V6T2_V8M) /* Features that are present in v6M and v6S-M but not other v6 cores. */ #define ARM_ARCH_V6M_ONLY ARM_FEATURE_CORE_LOW (ARM_AEXT_V6M_ONLY) /* v8-a+fp. */ #define ARM_ARCH_V8A_FP \ - ARM_FEATURE (ARM_AEXT_V8A, ARM_EXT2_ATOMICS, FPU_ARCH_VFP_ARMV8) + ARM_FEATURE (ARM_AEXT_V8A, ARM_AEXT2_V8A, FPU_ARCH_VFP_ARMV8) /* v8-a+simd (implies fp). */ #define ARM_ARCH_V8A_SIMD \ - ARM_FEATURE (ARM_AEXT_V8A, ARM_EXT2_ATOMICS, FPU_ARCH_NEON_VFP_ARMV8) + ARM_FEATURE (ARM_AEXT_V8A, ARM_AEXT2_V8A, FPU_ARCH_NEON_VFP_ARMV8) /* v8-a+crypto (implies simd+fp). */ #define ARM_ARCH_V8A_CRYPTOV1 \ - ARM_FEATURE (ARM_AEXT_V8A, ARM_EXT2_ATOMICS, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8) + ARM_FEATURE (ARM_AEXT_V8A, ARM_AEXT2_V8A, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8) /* v8.1-a+fp. */ #define ARM_ARCH_V8_1A_FP \ diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index a1f2ee4..23f148c 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,5 +1,11 @@ 2015-12-24 Thomas Preud'homme <thomas.preudhomme@arm.com> + * arm-dis.c (arm_opcodes): Guard movw, movt cbz, cbnz, clrex, ldrex, + ldrexb, ldrexh, strex, strexb, strexh shared by ARMv6T2 and ARMv8-M by + ARM_EXT2_V6T2_V8M instead of ARM_EXT_V6T2. + +2015-12-24 Thomas Preud'homme <thomas.preudhomme@arm.com> + * arm-dis.c (arm_opcodes): Guard lda, ldab, ldaex, ldaexb, ldaexh, stl, stlb, stlh, stlex, stlexb and stlexh by ARM_EXT2_ATOMICS instead of ARM_EXT_V8. diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c index 34f0e62..9df70c5 100644 --- a/opcodes/arm-dis.c +++ b/opcodes/arm-dis.c @@ -1666,9 +1666,9 @@ static const struct opcode32 arm_opcodes[] = {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15R, %S"}, - {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 0x03000000, 0x0ff00000, "movw%c\t%12-15R, %V"}, - {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 0x03400000, 0x0ff00000, "movt%c\t%12-15R, %V"}, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15R, %0-3R"}, @@ -2335,8 +2335,10 @@ static const struct opcode16 thumb_opcodes[] = {ARM_FEATURE_CORE_LOW (ARM_EXT_V6K), 0xbf00, 0xff0f, "nop%c\t{%4-7d}"}, /* ARM V6T2 instructions. */ - {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"}, - {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xb100, 0xfd00, "cbz\t%0-2r, %b%X"}, + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), + 0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"}, + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), + 0xb100, 0xfd00, "cbz\t%0-2r, %b%X"}, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xbf00, 0xff00, "it%I%X"}, /* ARM V6. */ @@ -2611,7 +2613,7 @@ static const struct opcode32 thumb32_opcodes[] = 0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"}, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf7f0a000, 0xfff0f000, "udf%c.w\t%H"}, - {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 0xf3bf8f2f, 0xffffffff, "clrex%c"}, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"}, @@ -2639,9 +2641,9 @@ static const struct opcode32 thumb32_opcodes[] = 0xf3de8f00, 0xffffff00, "subs%c\tpc, lr, #%0-7d"}, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"}, - {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"}, - {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"}, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, #%0-4d"}, @@ -2659,7 +2661,7 @@ static const struct opcode32 thumb32_opcodes[] = 0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"}, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"}, - {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"}, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"}, @@ -2767,7 +2769,7 @@ static const struct opcode32 thumb32_opcodes[] = 0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11R, %16-19R, %0-3R"}, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"}, - {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"}, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4D, %16-19r"}, @@ -2835,7 +2837,7 @@ static const struct opcode32 thumb32_opcodes[] = 0xfbe00000, 0xfff000f0, "umlal%c\t%12-15R, %8-11R, %16-19R, %0-3R"}, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xfbe00060, 0xfff000f0, "umaal%c\t%12-15R, %8-11R, %16-19R, %0-3R"}, - {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, #%0-7W]"}, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"}, @@ -2883,11 +2885,11 @@ static const struct opcode32 thumb32_opcodes[] = 0xf3800000, 0xffd08020, "usat%c\t%8-11r, #%0-4d, %16-19r%s"}, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"}, - {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"}, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"}, - {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"}, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"}, @@ -2909,7 +2911,7 @@ static const struct opcode32 thumb32_opcodes[] = 0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"}, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"}, - {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V6T2_V8M), 0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, #%0-7W]"}, {ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2), 0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"}, |