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-rw-r--r--bfd/ChangeLog12
-rw-r--r--bfd/archures.c1
-rw-r--r--bfd/bfd-in2.h1
-rw-r--r--bfd/cpu-v850.c4
-rw-r--r--bfd/elf32-v850.c25
-rw-r--r--bfd/libbfd.h2
-rw-r--r--binutils/ChangeLog4
-rw-r--r--binutils/readelf.c3
-rw-r--r--gas/ChangeLog10
-rw-r--r--gas/NEWS2
-rw-r--r--gas/config/tc-v850.c19
-rw-r--r--gas/doc/c-v850.texi14
-rw-r--r--gas/testsuite/ChangeLog6
-rw-r--r--gas/testsuite/gas/v850/basic.exp3
-rw-r--r--gas/testsuite/gas/v850/v850e1.d44
-rw-r--r--gas/testsuite/gas/v850/v850e1.s38
-rw-r--r--include/elf/ChangeLog4
-rw-r--r--include/elf/v850.h5
-rw-r--r--include/opcode/ChangeLog4
-rw-r--r--include/opcode/v850.h1
-rw-r--r--opcodes/ChangeLog5
-rw-r--r--opcodes/v850-dis.c28
-rw-r--r--opcodes/v850-opc.c134
23 files changed, 286 insertions, 83 deletions
diff --git a/bfd/ChangeLog b/bfd/ChangeLog
index 003e7ac..7353bdd 100644
--- a/bfd/ChangeLog
+++ b/bfd/ChangeLog
@@ -1,3 +1,15 @@
+2003-09-04 Nick Clifton <nickc@redhat.com>
+
+ * archures.c (bfd_mach_v850e1): Define.
+ * bfd-in2.h: Regenerate.
+ * cpu-v850.h (scan): Accept bfd_mach_v850e1.
+ (arch_info_struct): Include an entry for bfd_mach_v850e1.
+ * elf32-v850.c (v850_elf_object_p): Accept E_V850E1_ARCH flag.
+ (v850_elf_final_write_processing): Accept bfd_mach_v850e1.
+ (v850_elf_print_private_bfd_data): Interpret E_V850E1_ARCH flag.
+ (v850_elf_merge_private_bfd_data): Allow v850e1 binaries to be
+ linked with v850e binaries. Mark the output as v850e.
+
2003-09-03 Nick Clifton <nickc@redhat.com>
* cofflink.c (_bfd_coff_link_input_bfd): Do not skip section
diff --git a/bfd/archures.c b/bfd/archures.c
index 407cd26..3e0cafd 100644
--- a/bfd/archures.c
+++ b/bfd/archures.c
@@ -253,6 +253,7 @@ DESCRIPTION
. bfd_arch_v850, {* NEC V850 *}
.#define bfd_mach_v850 1
.#define bfd_mach_v850e 'E'
+.#define bfd_mach_v850e1 '1'
. bfd_arch_arc, {* ARC Cores *}
.#define bfd_mach_arc_5 5
.#define bfd_mach_arc_6 6
diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
index 38cb316..d81e56f 100644
--- a/bfd/bfd-in2.h
+++ b/bfd/bfd-in2.h
@@ -1682,6 +1682,7 @@ enum bfd_architecture
bfd_arch_v850, /* NEC V850 */
#define bfd_mach_v850 1
#define bfd_mach_v850e 'E'
+#define bfd_mach_v850e1 '1'
bfd_arch_arc, /* ARC Cores */
#define bfd_mach_arc_5 5
#define bfd_mach_arc_6 6
diff --git a/bfd/cpu-v850.c b/bfd/cpu-v850.c
index fe96656..1ff1cb3 100644
--- a/bfd/cpu-v850.c
+++ b/bfd/cpu-v850.c
@@ -1,5 +1,6 @@
/* BFD support for the NEC V850 processor
- Copyright 1996, 1997, 1998, 2000, 2001, 2002 Free Software Foundation, Inc.
+ Copyright 1996, 1997, 1998, 2000, 2001, 2002, 2003
+ Free Software Foundation, Inc.
This file is part of BFD, the Binary File Descriptor library.
@@ -30,6 +31,7 @@
static const bfd_arch_info_type arch_info_struct[] =
{
+ N (bfd_mach_v850e1, "v850e1", FALSE, & arch_info_struct[1]),
N (bfd_mach_v850e, "v850e", FALSE, NULL)
};
diff --git a/bfd/elf32-v850.c b/bfd/elf32-v850.c
index 8437c3d..0dc6542 100644
--- a/bfd/elf32-v850.c
+++ b/bfd/elf32-v850.c
@@ -1877,6 +1877,9 @@ v850_elf_object_p (abfd)
case E_V850E_ARCH:
bfd_default_set_arch_mach (abfd, bfd_arch_v850, bfd_mach_v850e);
break;
+ case E_V850E1_ARCH:
+ bfd_default_set_arch_mach (abfd, bfd_arch_v850, bfd_mach_v850e1);
+ break;
}
return TRUE;
}
@@ -1895,6 +1898,7 @@ v850_elf_final_write_processing (abfd, linker)
default:
case bfd_mach_v850: val = E_V850_ARCH; break;
case bfd_mach_v850e: val = E_V850E_ARCH; break;
+ case bfd_mach_v850e1: val = E_V850E1_ARCH; break;
}
elf_elfheader (abfd)->e_flags &=~ EF_V850_ARCH;
@@ -1960,8 +1964,24 @@ v850_elf_merge_private_bfd_data (ibfd, obfd)
if ((in_flags & EF_V850_ARCH) != (out_flags & EF_V850_ARCH)
&& (in_flags & EF_V850_ARCH) != E_V850_ARCH)
- _bfd_error_handler (_("%s: Architecture mismatch with previous modules"),
- bfd_archive_filename (ibfd));
+ {
+ /* Allow v850e1 binaries to be linked with v850e binaries.
+ Set the output binary to v850e. */
+ if ((in_flags & EF_V850_ARCH) == E_V850E1_ARCH
+ && (out_flags & EF_V850_ARCH) == E_V850E_ARCH)
+ return TRUE;
+
+ if ((in_flags & EF_V850_ARCH) == E_V850E_ARCH
+ && (out_flags & EF_V850_ARCH) == E_V850E1_ARCH)
+ {
+ elf_elfheader (obfd)->e_flags =
+ ((out_flags & ~ EF_V850_ARCH) | E_V850E_ARCH);
+ return TRUE;
+ }
+
+ _bfd_error_handler (_("%s: Architecture mismatch with previous modules"),
+ bfd_archive_filename (ibfd));
+ }
return TRUE;
}
@@ -1987,6 +2007,7 @@ v850_elf_print_private_bfd_data (abfd, ptr)
default:
case E_V850_ARCH: fprintf (file, _("v850 architecture")); break;
case E_V850E_ARCH: fprintf (file, _("v850e architecture")); break;
+ case E_V850E1_ARCH: fprintf (file, _("v850e1 architecture")); break;
}
fputc ('\n', file);
diff --git a/bfd/libbfd.h b/bfd/libbfd.h
index 61c8e65..a428c66 100644
--- a/bfd/libbfd.h
+++ b/bfd/libbfd.h
@@ -854,6 +854,7 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@",
"BFD_RELOC_MIPS_REL16",
"BFD_RELOC_MIPS_RELGOT",
"BFD_RELOC_MIPS_JALR",
+
"BFD_RELOC_FRV_LABEL16",
"BFD_RELOC_FRV_LABEL24",
"BFD_RELOC_FRV_LO16",
@@ -863,6 +864,7 @@ static const char *const bfd_reloc_code_real_names[] = { "@@uninitialized@@",
"BFD_RELOC_FRV_GPREL32",
"BFD_RELOC_FRV_GPRELHI",
"BFD_RELOC_FRV_GPRELLO",
+
"BFD_RELOC_MN10300_GOTOFF24",
"BFD_RELOC_MN10300_GOT32",
"BFD_RELOC_MN10300_GOT24",
diff --git a/binutils/ChangeLog b/binutils/ChangeLog
index f863d98..d238572 100644
--- a/binutils/ChangeLog
+++ b/binutils/ChangeLog
@@ -1,3 +1,7 @@
+2003-09-04 Nick Clifton <nickc@redhat.com>
+
+ * readelf.c (get_machine_flags): Recognise V850E1 machine type.
+
2003-09-03 Andrew Cagney <cagney@redhat.com>
* objdump.c: Refer to init_disassemble_info in comments.
diff --git a/binutils/readelf.c b/binutils/readelf.c
index ac1955e..4887a54 100644
--- a/binutils/readelf.c
+++ b/binutils/readelf.c
@@ -1817,6 +1817,9 @@ get_machine_flags (unsigned e_flags, unsigned e_machine)
case EM_CYGNUS_V850:
switch (e_flags & EF_V850_ARCH)
{
+ case E_V850E1_ARCH:
+ strcat (buf, ", v850e1");
+ break;
case E_V850E_ARCH:
strcat (buf, ", v850e");
break;
diff --git a/gas/ChangeLog b/gas/ChangeLog
index aee80e5..c1c79db 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,13 @@
+2003-09-04 Nick Clifton <nickc@redhat.com>
+
+ * config/tc-v850.c (set_machine): Accept v850e1 machine number.
+ (md_pseudo_table): Add .v850e1 pseudo op.
+ (md_show_usage): Document -mv850e1 switch.
+ (md_parse_option): Accept -mv850e1 switch.
+ (md_begin): Allow TARGET_CPU to be v850e1.
+ * doc/c-v850.texi: Document -mv850e1 switch and .v850e1 pseudo op.
+ * NEWS: Mention support for v850e1.
+
2003-09-04 Alan Modra <amodra@bigpond.net.au>
* config/tc-ppc.c (md_parse_option): Add PPC_OPCODE_ANY to existing
diff --git a/gas/NEWS b/gas/NEWS
index 3393d9c..b1c5b31 100644
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -1,5 +1,7 @@
-*- text -*-
+* Added support for v850e1.
+
* Added -n switch for x86 assembler. By default, x86 GAS replaces
multiple nop instructions used for alignment within code sections
with multi-byte nop instructions such as leal 0(%esi,1),%esi. This
diff --git a/gas/config/tc-v850.c b/gas/config/tc-v850.c
index 1e618aa..25fea3a 100644
--- a/gas/config/tc-v850.c
+++ b/gas/config/tc-v850.c
@@ -479,6 +479,7 @@ set_machine (number)
{
case 0: processor_mask = PROCESSOR_V850; break;
case bfd_mach_v850e: processor_mask = PROCESSOR_V850E; break;
+ case bfd_mach_v850e1: processor_mask = PROCESSOR_V850E; break;
}
}
@@ -539,6 +540,7 @@ const pseudo_typeS md_pseudo_table[] =
{ "call_table_data", v850_seg, CALL_TABLE_DATA_SECTION },
{ "call_table_text", v850_seg, CALL_TABLE_TEXT_SECTION },
{ "v850e", set_machine, bfd_mach_v850e },
+ { "v850e1", set_machine, bfd_mach_v850e1 },
{ "longcall", v850_longcode, 1 },
{ "longjump", v850_longcode, 2 },
{ NULL, NULL, 0 }
@@ -1156,6 +1158,7 @@ md_show_usage (stream)
fprintf (stream, _(" -mwarn-unsigned-overflow Warn if unsigned immediate values overflow\n"));
fprintf (stream, _(" -mv850 The code is targeted at the v850\n"));
fprintf (stream, _(" -mv850e The code is targeted at the v850e\n"));
+ fprintf (stream, _(" -mv850e1 The code is targeted at the v850e1\n"));
fprintf (stream, _(" -mv850any The code is generic, despite any processor specific instructions\n"));
fprintf (stream, _(" -mrelax Enable relaxation\n"));
}
@@ -1191,6 +1194,11 @@ md_parse_option (c, arg)
machine = bfd_mach_v850e;
processor_mask = PROCESSOR_V850E;
}
+ else if (strcmp (arg, "v850e1") == 0)
+ {
+ machine = bfd_mach_v850e1;
+ processor_mask = PROCESSOR_V850E1;
+ }
else if (strcmp (arg, "v850any") == 0)
{
/* Tell the world that this is for any v850 chip. */
@@ -1198,6 +1206,7 @@ md_parse_option (c, arg)
/* But support instructions for the extended versions. */
processor_mask = PROCESSOR_V850E;
+ processor_mask |= PROCESSOR_V850E1;
}
else if (strcmp (arg, "relax") == 0)
v850_relax = 1;
@@ -1327,7 +1336,15 @@ md_begin ()
char *prev_name = "";
const struct v850_opcode *op;
- if (strncmp (TARGET_CPU, "v850e", 5) == 0)
+ if (strncmp (TARGET_CPU, "v850e1", 6) == 0)
+ {
+ if (machine == -1)
+ machine = bfd_mach_v850e1;
+
+ if (processor_mask == -1)
+ processor_mask = PROCESSOR_V850E1;
+ }
+ else if (strncmp (TARGET_CPU, "v850e", 5) == 0)
{
if (machine == -1)
machine = bfd_mach_v850e;
diff --git a/gas/doc/c-v850.texi b/gas/doc/c-v850.texi
index 432f3ba..5fd4bac 100644
--- a/gas/doc/c-v850.texi
+++ b/gas/doc/c-v850.texi
@@ -1,4 +1,4 @@
-@c Copyright 1997 Free Software Foundation, Inc.
+@c Copyright 1997, 2003 Free Software Foundation, Inc.
@c This is part of the GAS manual.
@c For copying conditions, see the file as.texinfo.
@@ -51,6 +51,12 @@ Specifies that the assembled code should be marked as being targeted at
the V850E processor. This allows the linker to detect attempts to link
such code with code assembled for other processors.
+@cindex @code{-mv850e1} command line option, V850
+@item -mv850e1
+Specifies that the assembled code should be marked as being targeted at
+the V850E1 processor. This allows the linker to detect attempts to link
+such code with code assembled for other processors.
+
@cindex @code{-mv850any} command line option, V850
@item -mv850any
Specifies that the assembled code should be marked as being targeted at
@@ -233,6 +239,12 @@ Specifies that the assembled code should be marked as being targeted at
the V850E processor. This allows the linker to detect attempts to link
such code with code assembled for other processors.
+@cindex @code{.v850e1} directive, V850
+@item .v850e1
+Specifies that the assembled code should be marked as being targeted at
+the V850E1 processor. This allows the linker to detect attempts to link
+such code with code assembled for other processors.
+
@end table
@node V850 Opcodes
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 454488d..54324dd 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,9 @@
+2003-09-04 Nick Clifton <nickc@redhat.com>
+
+ * gas/v850/v850e1.s: New test source file.
+ * gas/v850/v850e1.d: New test disassembly file.
+ * gas/v850/basic.exp: Run v850e1 test.
+
2003-09-03 Robert Millan <robertmh@gnu.org>
* gas/alpha/alpha.exp: Match GNU/KFreeBSD with new kfreebsd*-gnu
diff --git a/gas/testsuite/gas/v850/basic.exp b/gas/testsuite/gas/v850/basic.exp
index 9943813..e3b0713 100644
--- a/gas/testsuite/gas/v850/basic.exp
+++ b/gas/testsuite/gas/v850/basic.exp
@@ -1,4 +1,4 @@
-# Copyright (C) 1996 Free Software Foundation, Inc.
+# Copyright (C) 1996, 2003 Free Software Foundation, Inc.
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
@@ -435,4 +435,5 @@ if [istarget v850*-*-*] then {
gas_test "fepsw.s" "" "" "eqsw regression test"
gas_test_error "range.s" "-mwarn-signed-overflow" "Check for range error on byte load/store"
+ run_dump_test "v850e1"
}
diff --git a/gas/testsuite/gas/v850/v850e1.d b/gas/testsuite/gas/v850/v850e1.d
new file mode 100644
index 0000000..9fb689b
--- /dev/null
+++ b/gas/testsuite/gas/v850/v850e1.d
@@ -0,0 +1,44 @@
+#objdump: -dr --prefix-addresses --show-raw-insn
+#name: V850E1 instruction tests
+#as: -mv850e1
+
+# Test the new instructions in the V850E1 processor
+
+.*: +file format .*v850.*
+
+Disassembly of section .text:
+0x0+00 e0 0f 42 13 [ ]*bsh r1, r2
+0x0+04 e0 1f 40 23 [ ]*bsw sp, gp
+0x0+08 05 02 [ ]*callt 5
+0x0+0a e8 3f e4 00 [ ]*clr1 r7, r8
+0x0+0e f6 17 14 1b [ ]*cmov nz, -10, r2, sp
+0x0+12 e1 17 34 1b [ ]*cmov nz, r1, r2, sp
+0x0+16 e0 07 44 01 [ ]*ctret
+0x0+1a e0 07 46 01 [ ]*dbret
+0x0+1e 40 f8 [ ]*dbtrap
+0x0+20 4e 06 00 80 [ ]*dispose 7, {r24}, r0
+0x0+24 4e 06 05 70 [ ]*dispose 7, {r25 - r27}, r5
+0x0+28 e1 17 c0 1a [ ]*div r1, r2, sp
+0x0+2c e4 2f 80 32 [ ]*divh gp, r5, r6
+0x0+30 e7 47 82 4a [ ]*divhu r7, r8, r9
+0x0+34 ea 5f c2 62 [ ]*divu r10, r11, r12
+0x0+38 e0 6f 44 73 [ ]*hsw r13, r14
+0x0+3c a1 17 0d 00 [ ]*ld.bu 13\[r1\],r2
+0x0+40 e3 27 11 00 [ ]*ld.hu 16\[sp\],gp
+0x0+44 21 06 78 56 34 12 [ ]*mov 0x12345678, r1
+0x0+4a e5 17 40 1a [ ]*mul 5, r2, sp
+0x0+4e e1 17 20 1a [ ]*mul r1, r2, sp
+0x0+52 e4 2f 22 32 [ ]*mulu gp, r5, r6
+0x0+56 e3 2f 46 32 [ ]*mulu 35, r5, r6
+0x0+5a ea 4f e2 00 [ ]*not1 r9, r10
+0x0+5e a8 07 01 80 [ ]*prepare {r24}, 20
+0x0+62 a8 07 03 70 [ ]*prepare {r25 - r27}, 20, sp
+0x0+66 e1 4f e0 00 [ ]*set1 r9, r1
+0x0+6a ea 47 00 02 [ ]*sasf nz, r8
+0x0+6e 60 20 [ ]*sld.bu 0\[ep\],gp
+0x0+70 77 28 [ ]*sld.hu 14\[ep\],r5
+0x0+72 a1 00 [ ]*sxb r1
+0x0+74 e2 00 [ ]*sxh r2
+0x0+76 ff 07 e6 00 [ ]*tst1 r0, lp
+0x0+7a 83 00 [ ]*zxb sp
+0x0+7c c4 00 [ ]*zxh gp
diff --git a/gas/testsuite/gas/v850/v850e1.s b/gas/testsuite/gas/v850/v850e1.s
new file mode 100644
index 0000000..5013261
--- /dev/null
+++ b/gas/testsuite/gas/v850/v850e1.s
@@ -0,0 +1,38 @@
+.text
+.align 0
+
+ bsh r1, r2
+ bsw r3, r4
+ callt 5
+ clr1 r7, [r8]
+ cmov nz, 22, r2, r3
+ cmov nz, r1, r2, r3
+ ctret
+ dbret
+ dbtrap
+ dispose 7, {r24}
+ dispose 7, {r25 - r27}, r5
+ div r1, r2, r3
+ divh r4, r5, r6
+ divhu r7, r8, r9
+ divu r10, r11, r12
+ hsw r13, r14
+ ld.bu 13 [r1], r2
+ ld.hu 16 [r3], r4
+ mov 0x12345678, r1
+ mul 5, r2, r3
+ mul r1, r2, r3
+ mulu r4, r5, r6
+ mulu 35, r5, r6
+ not1 r9, [r10]
+ prepare {r24}, 20
+ prepare {r25 - r27}, 20, sp
+ set1 r9, [r1]
+ sasf nz, r8
+ sld.bu 0 [ep], r4
+ sld.hu 14 [ep], r5
+ sxb r1
+ sxh r2
+ tst1 r0, [r31]
+ zxb r3
+ zxh r4
diff --git a/include/elf/ChangeLog b/include/elf/ChangeLog
index f538951..eec49b1 100644
--- a/include/elf/ChangeLog
+++ b/include/elf/ChangeLog
@@ -1,3 +1,7 @@
+2003-09-04 Nick Clifton <nickc@redhat.com>
+
+ * v850.h (E_V850E1_ARCH): Define.
+
2003-08-21 James Cownie <jcownie@etnus.com>
* dwarf2.h: Add PGI dwarf extensions.
diff --git a/include/elf/v850.h b/include/elf/v850.h
index db5b2d9..7d5110b 100644
--- a/include/elf/v850.h
+++ b/include/elf/v850.h
@@ -1,5 +1,5 @@
/* V850 ELF support for BFD.
- Copyright 1997, 1998, 2000, 2002 Free Software Foundation, Inc.
+ Copyright 1997, 1998, 2000, 2002, 2003 Free Software Foundation, Inc.
Created by Michael Meissner, Cygnus Support <meissner@cygnus.com>
This file is part of BFD, the Binary File Descriptor library.
@@ -35,6 +35,9 @@
/* v850e code. */
#define E_V850E_ARCH 0x10000000
+/* v850e1 code. */
+#define E_V850E1_ARCH 0x20000000
+
/* Flags for the st_other field. */
#define V850_OTHER_SDA 0x01 /* Symbol had SDA relocations. */
diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog
index 8aa8453..aaea214 100644
--- a/include/opcode/ChangeLog
+++ b/include/opcode/ChangeLog
@@ -1,3 +1,7 @@
+2003-09-04 Nick Clifton <nickc@redhat.com>
+
+ * v850.h (PROCESSOR_V850E1): Define.
+
2003-08-19 Alan Modra <amodra@bigpond.net.au>
* ppc.h (PPC_OPCODE_440): Define. Formatting. Use hex for other
diff --git a/include/opcode/v850.h b/include/opcode/v850.h
index f6a1eb4..75689bf 100644
--- a/include/opcode/v850.h
+++ b/include/opcode/v850.h
@@ -59,6 +59,7 @@ struct v850_opcode
#define PROCESSOR_V850E (1 << 1) /* Just the V850E. */
#define PROCESSOR_NOT_V850 (~ PROCESSOR_V850) /* Any processor except the V850. */
#define PROCESSOR_V850EA (1 << 2) /* Just the V850EA. */
+#define PROCESSOR_V850E1 (1 << 3) /* Just the V850E1. */
/* The table itself is sorted by major opcode number, and is otherwise
in the order in which the disassembler should consider
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 2fb406d..4af9936 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,8 @@
+2003-09-04 Nick Clifton <nickc@redhat.com>
+
+ * v850-dis.c (disassemble): Accept bfd_mach_v850e1.
+ * v850-opc.c (v850_opcodes): Add DBTRAP and DBRET instructions.
+
2003-09-04 Alan Modra <amodra@bigpond.net.au>
* ppc-dis.c (struct dis_private): New.
diff --git a/opcodes/v850-dis.c b/opcodes/v850-dis.c
index 7c449f6..b5022cd 100644
--- a/opcodes/v850-dis.c
+++ b/opcodes/v850-dis.c
@@ -1,20 +1,20 @@
/* Disassemble V850 instructions.
- Copyright 1996, 1997, 1998, 2000, 2001, 2002
+ Copyright 1996, 1997, 1998, 2000, 2001, 2002, 2003
Free Software Foundation, Inc.
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2 of the License, or
-(at your option) any later version.
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
-You should have received a copy of the GNU General Public License
-along with this program; if not, write to the Free Software
-Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
#include <stdio.h>
@@ -78,6 +78,10 @@ disassemble (memaddr, info, insn)
case bfd_mach_v850e:
target_processor = PROCESSOR_V850E;
break;
+
+ case bfd_mach_v850e1:
+ target_processor = PROCESSOR_V850E1;
+ break;
}
/* Find the opcode. */
diff --git a/opcodes/v850-opc.c b/opcodes/v850-opc.c
index 94969ac..2249d16 100644
--- a/opcodes/v850-opc.c
+++ b/opcodes/v850-opc.c
@@ -1,37 +1,37 @@
/* Assemble V850 instructions.
- Copyright 1996, 1997, 1998, 2000, 2001 Free Software Foundation, Inc.
+ Copyright 1996, 1997, 1998, 2000, 2001, 2003 Free Software Foundation, Inc.
-This program is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2 of the License, or
-(at your option) any later version.
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
-This program is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
-You should have received a copy of the GNU General Public License
-along with this program; if not, write to the Free Software
-Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
#include "sysdep.h"
#include "opcode/v850.h"
#include <stdio.h>
#include "opintl.h"
-/* regular opcode */
+/* Regular opcodes. */
#define OP(x) ((x & 0x3f) << 5)
#define OP_MASK OP (0x3f)
-/* conditional branch opcode */
+/* Conditional branch opcodes. */
#define BOP(x) ((0x0b << 7) | (x & 0x0f))
#define BOP_MASK ((0x0f << 7) | 0x0f)
-/* one-word opcodes */
+/* One-word opcodes. */
#define one(x) ((unsigned int) (x))
-/* two-word opcodes */
+/* Two-word opcodes. */
#define two(x,y) ((unsigned int) (x) | ((unsigned int) (y) << 16))
static long unsigned insert_d9 PARAMS ((long unsigned, long, const char **));
@@ -402,15 +402,15 @@ const struct v850_operand v850_operands[] =
#define UNUSED 0
{ 0, 0, NULL, NULL, 0 },
-/* The R1 field in a format 1, 6, 7, or 9 insn. */
+/* The R1 field in a format 1, 6, 7, or 9 insn. */
#define R1 (UNUSED + 1)
{ 5, 0, NULL, NULL, V850_OPERAND_REG },
/* As above, but register 0 is not allowed. */
#define R1_NOTR0 (R1 + 1)
- { 5, 0, NULL, NULL, V850_OPERAND_REG | V850_NOT_R0 },
+ { 5, 0, NULL, NULL, V850_OPERAND_REG | V850_NOT_R0 },
-/* The R2 field in a format 1, 2, 4, 5, 6, 7, 9 insn. */
+/* The R2 field in a format 1, 2, 4, 5, 6, 7, 9 insn. */
#define R2 (R1_NOTR0 + 1)
{ 5, 11, NULL, NULL, V850_OPERAND_REG },
@@ -418,23 +418,23 @@ const struct v850_operand v850_operands[] =
#define R2_NOTR0 (R2 + 1)
{ 5, 11, NULL, NULL, V850_OPERAND_REG | V850_NOT_R0 },
-/* The imm5 field in a format 2 insn. */
+/* The imm5 field in a format 2 insn. */
#define I5 (R2_NOTR0 + 1)
{ 5, 0, NULL, NULL, V850_OPERAND_SIGNED },
-/* The unsigned imm5 field in a format 2 insn. */
+/* The unsigned imm5 field in a format 2 insn. */
#define I5U (I5 + 1)
{ 5, 0, NULL, NULL, 0 },
-/* The imm16 field in a format 6 insn. */
+/* The imm16 field in a format 6 insn. */
#define I16 (I5U + 1)
{ 16, 16, NULL, NULL, V850_OPERAND_SIGNED },
-/* The signed disp7 field in a format 4 insn. */
+/* The signed disp7 field in a format 4 insn. */
#define D7 (I16 + 1)
{ 7, 0, NULL, NULL, 0},
-/* The disp16 field in a format 6 insn. */
+/* The disp16 field in a format 6 insn. */
#define D16_15 (D7 + 1)
{ 15, 17, insert_d16_15, extract_d16_15, V850_OPERAND_SIGNED },
@@ -446,11 +446,11 @@ const struct v850_operand v850_operands[] =
#define CCCC (B3 + 1)
{ 4, 0, NULL, NULL, V850_OPERAND_CC },
-/* The unsigned DISP8 field in a format 4 insn. */
+/* The unsigned DISP8 field in a format 4 insn. */
#define D8_7 (CCCC + 1)
{ 7, 0, insert_d8_7, extract_d8_7, 0 },
-/* The unsigned DISP8 field in a format 4 insn. */
+/* The unsigned DISP8 field in a format 4 insn. */
#define D8_6 (D8_7 + 1)
{ 6, 1, insert_d8_6, extract_d8_6, 0 },
@@ -462,7 +462,7 @@ const struct v850_operand v850_operands[] =
#define EP (SR1 + 1)
{ 0, 0, NULL, NULL, V850_OPERAND_EP },
-/* The imm16 field (unsigned) in a format 6 insn. */
+/* The imm16 field (unsigned) in a format 6 insn. */
#define I16U (EP + 1)
{ 16, 16, NULL, NULL, 0},
@@ -470,11 +470,11 @@ const struct v850_operand v850_operands[] =
#define SR2 (I16U + 1)
{ 5, 11, NULL, NULL, V850_OPERAND_SRG },
-/* The disp16 field in a format 8 insn. */
+/* The disp16 field in a format 8 insn. */
#define D16 (SR2 + 1)
{ 16, 16, NULL, NULL, V850_OPERAND_SIGNED },
-/* The DISP9 field in a format 3 insn, relaxable. */
+/* The DISP9 field in a format 3 insn, relaxable. */
#define D9_RELAX (D16 + 1)
{ 9, 0, insert_d9, extract_d9, V850_OPERAND_RELAX | V850_OPERAND_SIGNED | V850_OPERAND_DISP },
@@ -484,19 +484,19 @@ const struct v850_operand v850_operands[] =
#define D22 (D9_RELAX + 1)
{ 22, 0, insert_d22, extract_d22, V850_OPERAND_SIGNED | V850_OPERAND_DISP },
-/* The signed disp4 field in a format 4 insn. */
+/* The signed disp4 field in a format 4 insn. */
#define D4 (D22 + 1)
{ 4, 0, NULL, NULL, 0},
-/* The unsigned disp5 field in a format 4 insn. */
+/* The unsigned disp5 field in a format 4 insn. */
#define D5_4 (D4 + 1)
{ 4, 0, insert_d5_4, extract_d5_4, 0 },
-/* The disp16 field in an format 7 unsigned byte load insn. */
+/* The disp16 field in an format 7 unsigned byte load insn. */
#define D16_16 (D5_4 + 1)
{ -1, 0xfffe0020, insert_d16_16, extract_d16_16, 0 },
-/* Third register in conditional moves. */
+/* Third register in conditional moves. */
#define R3 (D16_16 + 1)
{ 5, 27, NULL, NULL, V850_OPERAND_REG },
@@ -504,11 +504,11 @@ const struct v850_operand v850_operands[] =
#define MOVCC (R3 + 1)
{ 4, 17, NULL, NULL, V850_OPERAND_CC },
-/* The imm9 field in a multiply word. */
+/* The imm9 field in a multiply word. */
#define I9 (MOVCC + 1)
{ 9, 0, insert_i9, extract_i9, V850_OPERAND_SIGNED },
-/* The unsigned imm9 field in a multiply word. */
+/* The unsigned imm9 field in a multiply word. */
#define U9 (I9 + 1)
{ 9, 0, insert_u9, extract_u9, 0 },
@@ -516,7 +516,7 @@ const struct v850_operand v850_operands[] =
#define LIST12 (U9 + 1)
{ -1, 0xffe00001, NULL, NULL, V850E_PUSH_POP },
-/* The IMM6 field in a call instruction. */
+/* The IMM6 field in a call instruction. */
#define I6 (LIST12 + 1)
{ 6, 0, NULL, NULL, 0 },
@@ -528,19 +528,19 @@ const struct v850_operand v850_operands[] =
#define IMM32 (IMM16 + 1)
{ 0, 0, NULL, NULL, V850E_IMMEDIATE32 },
-/* The imm5 field in a push/pop instruction. */
+/* The imm5 field in a push/pop instruction. */
#define IMM5 (IMM32 + 1)
{ 5, 1, NULL, NULL, 0 },
-/* Reg2 in dispose instruction. */
+/* Reg2 in dispose instruction. */
#define R2DISPOSE (IMM5 + 1)
{ 5, 16, NULL, NULL, V850_OPERAND_REG | V850_NOT_R0 },
-/* Stack pointer in prepare instruction. */
+/* Stack pointer in prepare instruction. */
#define SP (R2DISPOSE + 1)
{ 2, 19, insert_spe, extract_spe, V850_OPERAND_REG },
-/* The IMM5 field in a divide N step instruction. */
+/* The IMM5 field in a divide N step instruction. */
#define I5DIV (SP + 1)
{ 9, 0, insert_i5div, extract_i5div, V850_OPERAND_SIGNED },
@@ -550,23 +550,24 @@ const struct v850_operand v850_operands[] =
/* The list of registers in a PUSHML/POPML instruction. */
#define LIST18_L (LIST18_H + 1)
- { -1, 0xfff8001f, NULL, NULL, V850E_PUSH_POP }, /* The setting of the 4th bit is a flag to disassmble() in v850-dis.c */
+ /* The setting of the 4th bit is a flag to disassmble() in v850-dis.c. */
+ { -1, 0xfff8001f, NULL, NULL, V850E_PUSH_POP },
} ;
-/* reg-reg instruction format (Format I) */
+/* Reg - Reg instruction format (Format I). */
#define IF1 {R1, R2}
-/* imm-reg instruction format (Format II) */
+/* Imm - Reg instruction format (Format II). */
#define IF2 {I5, R2}
-/* conditional branch instruction format (Format III) */
+/* Conditional branch instruction format (Format III). */
#define IF3 {D9_RELAX}
-/* 3 operand instruction (Format VI) */
+/* 3 operand instruction (Format VI). */
#define IF6 {I16, R1, R2}
-/* 3 operand instruction (Format VI) */
+/* 3 operand instruction (Format VI). */
#define IF6U {I16U, R1, R2}
@@ -604,17 +605,22 @@ const struct v850_operand v850_operands[] =
const struct v850_opcode v850_opcodes[] =
{
{ "breakpoint", 0xffff, 0xffff, {UNUSED}, 0, PROCESSOR_ALL },
+{ "dbtrap", one (0xf840), one (0xffff), {UNUSED}, 0, PROCESSOR_V850E1 },
{ "jmp", one (0x0060), one (0xffe0), {R1}, 1, PROCESSOR_ALL },
-/* load/store instructions */
+/* Load/store instructions. */
+{ "sld.bu", one (0x0060), one (0x07f0), {D4, EP, R2_NOTR0}, 1, PROCESSOR_V850E1 },
{ "sld.bu", one (0x0060), one (0x07f0), {D4, EP, R2_NOTR0}, 1, PROCESSOR_V850E },
+{ "sld.hu", one (0x0070), one (0x07f0), {D5_4, EP, R2_NOTR0}, 1, PROCESSOR_V850E1 },
{ "sld.hu", one (0x0070), one (0x07f0), {D5_4, EP, R2_NOTR0}, 1, PROCESSOR_V850E },
+{ "sld.b", one (0x0300), one (0x0780), {D7, EP, R2}, 1, PROCESSOR_V850E1 },
{ "sld.b", one (0x0300), one (0x0780), {D7, EP, R2}, 1, PROCESSOR_V850E },
{ "sld.b", one (0x0300), one (0x0780), {D7, EP, R2}, 1, PROCESSOR_V850 },
+{ "sld.h", one (0x0400), one (0x0780), {D8_7, EP, R2}, 1, PROCESSOR_V850E1 },
{ "sld.h", one (0x0400), one (0x0780), {D8_7, EP, R2}, 1, PROCESSOR_V850E },
{ "sld.h", one (0x0400), one (0x0780), {D8_7, EP, R2}, 1, PROCESSOR_V850 },
{ "sld.w", one (0x0500), one (0x0781), {D8_6, EP, R2}, 1, PROCESSOR_ALL },
@@ -639,7 +645,7 @@ const struct v850_opcode v850_opcodes[] =
{ "st.h", two (0x0760, 0x0000), two (0x07e0, 0x0001), {R2, D16_15, R1}, 2, PROCESSOR_ALL },
{ "st.w", two (0x0760, 0x0001), two (0x07e0, 0x0001), {R2, D16_15, R1}, 2, PROCESSOR_ALL },
-/* byte swap/extend instructions */
+/* Byte swap/extend instructions. */
{ "zxb", one (0x0080), one (0xffe0), {R1_NOTR0}, 0, PROCESSOR_NOT_V850 },
{ "zxh", one (0x00c0), one (0xffe0), {R1_NOTR0}, 0, PROCESSOR_NOT_V850 },
{ "sxb", one (0x00a0), one (0xffe0), {R1_NOTR0}, 0, PROCESSOR_NOT_V850 },
@@ -648,12 +654,12 @@ const struct v850_opcode v850_opcodes[] =
{ "bsw", two (0x07e0, 0x0340), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_NOT_V850 },
{ "hsw", two (0x07e0, 0x0344), two (0x07ff, 0x07ff), {R2, R3}, 0, PROCESSOR_NOT_V850 },
-/* jump table instructions */
+/* Jump table instructions. */
{ "switch", one (0x0040), one (0xffe0), {R1}, 1, PROCESSOR_NOT_V850 },
{ "callt", one (0x0200), one (0xffc0), {I6}, 0, PROCESSOR_NOT_V850 },
{ "ctret", two (0x07e0, 0x0144), two (0xffff, 0xffff), {0}, 0, PROCESSOR_NOT_V850 },
-/* arithmetic operation instructions */
+/* Arithmetic operation instructions. */
{ "setf", two (0x07e0, 0x0000), two (0x07f0, 0xffff), {CCCC, R2}, 0, PROCESSOR_ALL },
{ "cmov", two (0x07e0, 0x0320), two (0x07e0, 0x07e1), {MOVCC, R1, R2, R3}, 0, PROCESSOR_NOT_V850 },
{ "cmov", two (0x07e0, 0x0300), two (0x07e0, 0x07e1), {MOVCC, I5, R2, R3}, 0, PROCESSOR_NOT_V850 },
@@ -686,14 +692,14 @@ const struct v850_opcode v850_opcodes[] =
{ "cmp", OP (0x0f), OP_MASK, IF1, 0, PROCESSOR_ALL },
{ "cmp", OP (0x13), OP_MASK, IF2, 0, PROCESSOR_ALL },
-/* saturated operation instructions */
+/* Saturated operation instructions. */
{ "satadd", OP (0x11), OP_MASK, {I5, R2_NOTR0}, 0, PROCESSOR_ALL },
{ "satadd", OP (0x06), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL },
{ "satsub", OP (0x05), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL },
{ "satsubi", OP (0x33), OP_MASK, {I16, R1, R2_NOTR0}, 0, PROCESSOR_ALL },
{ "satsubr", OP (0x04), OP_MASK, {R1, R2_NOTR0}, 0, PROCESSOR_ALL },
-/* logical operation instructions */
+/* Logical operation instructions. */
{ "tst", OP (0x0b), OP_MASK, IF1, 0, PROCESSOR_ALL },
{ "or", OP (0x08), OP_MASK, IF1, 0, PROCESSOR_ALL },
{ "ori", OP (0x34), OP_MASK, IF6U, 0, PROCESSOR_ALL },
@@ -710,21 +716,21 @@ const struct v850_opcode v850_opcodes[] =
{ "shr", two (0x07e0, 0x0080), two (0x07e0, 0xffff), {R1, R2}, 0, PROCESSOR_ALL },
{ "sasf", two (0x07e0, 0x0200), two (0x07f0, 0xffff), {CCCC, R2}, 0, PROCESSOR_NOT_V850 },
-/* branch instructions */
- /* signed integer */
+/* Branch instructions. */
+ /* Signed integer. */
{ "bgt", BOP (0xf), BOP_MASK, IF3, 0, PROCESSOR_ALL },
{ "bge", BOP (0xe), BOP_MASK, IF3, 0, PROCESSOR_ALL },
{ "blt", BOP (0x6), BOP_MASK, IF3, 0, PROCESSOR_ALL },
{ "ble", BOP (0x7), BOP_MASK, IF3, 0, PROCESSOR_ALL },
- /* unsigned integer */
+ /* Unsigned integer. */
{ "bh", BOP (0xb), BOP_MASK, IF3, 0, PROCESSOR_ALL },
{ "bnh", BOP (0x3), BOP_MASK, IF3, 0, PROCESSOR_ALL },
{ "bl", BOP (0x1), BOP_MASK, IF3, 0, PROCESSOR_ALL },
{ "bnl", BOP (0x9), BOP_MASK, IF3, 0, PROCESSOR_ALL },
- /* common */
+ /* Common. */
{ "be", BOP (0x2), BOP_MASK, IF3, 0, PROCESSOR_ALL },
{ "bne", BOP (0xa), BOP_MASK, IF3, 0, PROCESSOR_ALL },
- /* others */
+ /* Others. */
{ "bv", BOP (0x0), BOP_MASK, IF3, 0, PROCESSOR_ALL },
{ "bnv", BOP (0x8), BOP_MASK, IF3, 0, PROCESSOR_ALL },
{ "bn", BOP (0x4), BOP_MASK, IF3, 0, PROCESSOR_ALL },
@@ -741,20 +747,20 @@ const struct v850_opcode v850_opcodes[] =
We use the short form in the opcode/mask fields. The assembler
will twiddle bits as necessary if the long form is needed. */
- /* signed integer */
+ /* Signed integer. */
{ "jgt", BOP (0xf), BOP_MASK, IF3, 0, PROCESSOR_ALL },
{ "jge", BOP (0xe), BOP_MASK, IF3, 0, PROCESSOR_ALL },
{ "jlt", BOP (0x6), BOP_MASK, IF3, 0, PROCESSOR_ALL },
{ "jle", BOP (0x7), BOP_MASK, IF3, 0, PROCESSOR_ALL },
- /* unsigned integer */
+ /* Unsigned integer. */
{ "jh", BOP (0xb), BOP_MASK, IF3, 0, PROCESSOR_ALL },
{ "jnh", BOP (0x3), BOP_MASK, IF3, 0, PROCESSOR_ALL },
{ "jl", BOP (0x1), BOP_MASK, IF3, 0, PROCESSOR_ALL },
{ "jnl", BOP (0x9), BOP_MASK, IF3, 0, PROCESSOR_ALL },
- /* common */
+ /* Common. */
{ "je", BOP (0x2), BOP_MASK, IF3, 0, PROCESSOR_ALL },
{ "jne", BOP (0xa), BOP_MASK, IF3, 0, PROCESSOR_ALL },
- /* others */
+ /* Others. */
{ "jv", BOP (0x0), BOP_MASK, IF3, 0, PROCESSOR_ALL },
{ "jnv", BOP (0x8), BOP_MASK, IF3, 0, PROCESSOR_ALL },
{ "jn", BOP (0x4), BOP_MASK, IF3, 0, PROCESSOR_ALL },
@@ -769,7 +775,7 @@ const struct v850_opcode v850_opcodes[] =
{ "jr", one (0x0780), two (0xffc0, 0x0001), {D22}, 0, PROCESSOR_ALL },
{ "jarl", one (0x0780), two (0x07c0, 0x0001), {D22, R2}, 0, PROCESSOR_ALL},
-/* bit manipulation instructions */
+/* Bit manipulation instructions. */
{ "set1", two (0x07c0, 0x0000), two (0xc7e0, 0x0000), {B3, D16, R1}, 2, PROCESSOR_ALL },
{ "set1", two (0x07e0, 0x00e0), two (0x07e0, 0xffff), {R2, R1}, 2, PROCESSOR_NOT_V850 },
{ "not1", two (0x47c0, 0x0000), two (0xc7e0, 0x0000), {B3, D16, R1}, 2, PROCESSOR_ALL },
@@ -779,7 +785,7 @@ const struct v850_opcode v850_opcodes[] =
{ "tst1", two (0xc7c0, 0x0000), two (0xc7e0, 0x0000), {B3, D16, R1}, 2, PROCESSOR_ALL },
{ "tst1", two (0x07e0, 0x00e6), two (0x07e0, 0xffff), {R2, R1}, 2, PROCESSOR_NOT_V850 },
-/* special instructions */
+/* Special instructions. */
{ "di", two (0x07e0, 0x0160), two (0xffff, 0xffff), {0}, 0, PROCESSOR_ALL },
{ "ei", two (0x87e0, 0x0160), two (0xffff, 0xffff), {0}, 0, PROCESSOR_ALL },
{ "halt", two (0x07e0, 0x0120), two (0xffff, 0xffff), {0}, 0, PROCESSOR_ALL },
@@ -787,10 +793,10 @@ const struct v850_opcode v850_opcodes[] =
{ "trap", two (0x07e0, 0x0100), two (0xffe0, 0xffff), {I5U}, 0, PROCESSOR_ALL },
{ "ldsr", two (0x07e0, 0x0020), two (0x07e0, 0xffff), {R1, SR2}, 0, PROCESSOR_ALL },
{ "stsr", two (0x07e0, 0x0040), two (0x07e0, 0xffff), {SR1, R2}, 0, PROCESSOR_ALL },
+{ "dbret", two (0x07e0, 0x0146), two (0xffff, 0xffff), {UNUSED}, 0, PROCESSOR_V850E1 },
{ 0, 0, 0, {0}, 0, 0 },
} ;
const int v850_num_opcodes =
sizeof (v850_opcodes) / sizeof (v850_opcodes[0]);
-
generated by cgit v1.1 at 2024-07-14 19:58:51 +0000