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-rw-r--r--gas/testsuite/ChangeLog4
-rw-r--r--gas/testsuite/gas/ppc/e500mc.d9
-rw-r--r--opcodes/ChangeLog6
-rw-r--r--opcodes/ppc-opc.c9
4 files changed, 20 insertions, 8 deletions
diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 62708ea..e97c4c6 100644
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,7 @@
+2009-04-07 Peter Bergner <bergner@vnet.ibm.com>
+
+ * gas/ppc/e500mc.d: Update to match extended mnemonics.
+
2009-04-01 Nathan Sidwell <nathan@codesourcery.com>
* gas/arm/align.s, gas/arm/align.d: New.
diff --git a/gas/testsuite/gas/ppc/e500mc.d b/gas/testsuite/gas/ppc/e500mc.d
index 7d10f12..9a3d600 100644
--- a/gas/testsuite/gas/ppc/e500mc.d
+++ b/gas/testsuite/gas/ppc/e500mc.d
@@ -50,7 +50,8 @@ Disassembly of section \.text:
a0: 7c 64 29 fe dcbtstep r3,r4,r5
a4: 7c c7 42 7e dcbtep r6,r7,r8
a8: 7c 0b 67 fe dcbzep r11,r12
- ac: 7c 00 06 26 tlbilx 0,0,r0
- b0: 7c 20 06 26 tlbilx 1,0,r0
- b4: 7c 62 1e 26 tlbilx 3,r2,r3
- b8: 7c 64 2e 26 tlbilx 3,r4,r5
+ ac: 7c 00 00 24 tlbilxlpid
+ b0: 7c 20 00 24 tlbilxpid
+ b4: 7c 62 18 24 tlbilxva r2,r3
+ b8: 7c 64 28 24 tlbilxva r4,r5
+
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 4cdc261..37c14fc 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,9 @@
+2009-04-07 Peter Bergner <bergner@vnet.ibm.com>
+
+ * ppc-opc.c (powerpc_opcodes) <"tlbilxlpid", "tlbilxpid", "tlbilxva",
+ "tlbilx">: Use secondary opcode "18" as per the ISA 2.06 documentation.
+ Reorder entries so the extended mnemonics are listed before tlbilx.
+
2009-04-02 Peter Bergner <bergner@vnet.ibm.com>
* ppc-dis.c (powerpc_init_dialect): Do not choose a default dialect
diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index 7bf96c4..bc64e49 100644
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -3464,6 +3464,11 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"isellt", X(31,15), X_MASK, PPCISEL, PPCNONE, {RT, RA, RB}},
+{"tlbilxlpid", XTO(31,18,0), XTO_MASK, E500MC, PPCNONE, {0}},
+{"tlbilxpid", XTO(31,18,1), XTO_MASK, E500MC, PPCNONE, {0}},
+{"tlbilxva", XTO(31,18,3), XTO_MASK, E500MC, PPCNONE, {RA0, RB}},
+{"tlbilx", X(31,18), X_MASK, E500MC, PPCNONE, {T, RA0, RB}},
+
{"mfcr", XFXM(31,19,0,0), XFXFXM_MASK, POWER4, PPCNONE, {RT, FXM4}},
{"mfcr", XFXM(31,19,0,0), XRARB_MASK, COM, POWER4, {RT}},
{"mfocrf", XFXM(31,19,0,1), XFXFXM_MASK, COM, PPCNONE, {RT, FXM}},
@@ -4551,10 +4556,6 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"lxvw4x", X(31,780), XX1_MASK, PPCVSX, PPCNONE, {XT6, RA, RB}},
{"tlbivax", X(31,786), XRT_MASK, BOOKE, PPCNONE, {RA, RB}},
-{"tlbilx", X(31,787), X_MASK, E500MC, PPCNONE, {T, RA0, RB}},
-{"tlbilxlpid", XTO(31,787,0), XTO_MASK, E500MC, PPCNONE, {0}},
-{"tlbilxpid", XTO(31,787,1), XTO_MASK, E500MC, PPCNONE, {0}},
-{"tlbilxva", XTO(31,787,3), XTO_MASK, E500MC, PPCNONE, {RA0, RB}},
{"lwzcix", X(31,789), X_MASK, POWER6, PPCNONE, {RT, RA0, RB}},