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| author | Nick Clifton <nickc@redhat.com> | 2002-07-05 14:12:01 +0000 |
|---|---|---|
| committer | Nick Clifton <nickc@redhat.com> | 2002-07-05 14:12:01 +0000 |
| commit | 630ace253aa871d9b8ef3d0d6f0f97183136e08d (patch) | |
| tree | b58b90d3e3dfb767b91837edfe65a1313ed86646 /sim | |
| parent | 34786259b83b1c3a8866b3dc52ea2895a1e85fe6 (diff) | |
| download | fsf-binutils-gdb-630ace253aa871d9b8ef3d0d6f0f97183136e08d.zip fsf-binutils-gdb-630ace253aa871d9b8ef3d0d6f0f97183136e08d.tar.gz fsf-binutils-gdb-630ace253aa871d9b8ef3d0d6f0f97183136e08d.tar.bz2 | |
Add checks to catch invaliud XScale MIA, MIAPH and MIAxy instructions.
Diffstat (limited to 'sim')
| -rw-r--r-- | sim/arm/ChangeLog | 5 | ||||
| -rw-r--r-- | sim/arm/armemu.c | 142 |
2 files changed, 79 insertions, 68 deletions
diff --git a/sim/arm/ChangeLog b/sim/arm/ChangeLog index 64452db..acd66ad 100644 --- a/sim/arm/ChangeLog +++ b/sim/arm/ChangeLog @@ -1,3 +1,8 @@ +2002-07-05 Nick Clifton <nickc@cambridge.redhat.com> + + * armemu.c (ARMul_Emulate32): Add more tests for valid MIA, MIAPH + and MIAxy instructions. + 2002-06-21 Nick Clifton <nickc@cambridge.redhat.com> * armos.h (ADP_Stopped_RunTimeError): Set correct value. diff --git a/sim/arm/armemu.c b/sim/arm/armemu.c index 8e71926..44943c4 100644 --- a/sim/arm/armemu.c +++ b/sim/arm/armemu.c @@ -3366,78 +3366,84 @@ check_PMUintr: switch (BITS (18, 19)) { case 0x0: - { - /* XScale MIA instruction. Signed multiplication of two 32 bit - values and addition to 40 bit accumulator. */ - long long Rm = state->Reg[MULLHSReg]; - long long Rs = state->Reg[MULACCReg]; - - if (Rm & (1 << 31)) - Rm -= 1ULL << 32; - if (Rs & (1 << 31)) - Rs -= 1ULL << 32; - state->Accumulator += Rm * Rs; - } - goto donext; + if (BITS (4, 11) == 1 && BITS (16, 17) == 0) + { + /* XScale MIA instruction. Signed multiplication of + two 32 bit values and addition to 40 bit accumulator. */ + long long Rm = state->Reg[MULLHSReg]; + long long Rs = state->Reg[MULACCReg]; + + if (Rm & (1 << 31)) + Rm -= 1ULL << 32; + if (Rs & (1 << 31)) + Rs -= 1ULL << 32; + state->Accumulator += Rm * Rs; + goto donext; + } + break; case 0x2: - { - /* XScale MIAPH instruction. */ - ARMword t1 = state->Reg[MULLHSReg] >> 16; - ARMword t2 = state->Reg[MULACCReg] >> 16; - ARMword t3 = state->Reg[MULLHSReg] & 0xffff; - ARMword t4 = state->Reg[MULACCReg] & 0xffff; - long long t5; - - if (t1 & (1 << 15)) - t1 -= 1 << 16; - if (t2 & (1 << 15)) - t2 -= 1 << 16; - if (t3 & (1 << 15)) - t3 -= 1 << 16; - if (t4 & (1 << 15)) - t4 -= 1 << 16; - t1 *= t2; - t5 = t1; - if (t5 & (1 << 31)) - t5 -= 1ULL << 32; - state->Accumulator += t5; - t3 *= t4; - t5 = t3; - if (t5 & (1 << 31)) - t5 -= 1ULL << 32; - state->Accumulator += t5; - } - goto donext; + if (BITS (4, 11) == 1 && BITS (16, 17) == 0) + { + /* XScale MIAPH instruction. */ + ARMword t1 = state->Reg[MULLHSReg] >> 16; + ARMword t2 = state->Reg[MULACCReg] >> 16; + ARMword t3 = state->Reg[MULLHSReg] & 0xffff; + ARMword t4 = state->Reg[MULACCReg] & 0xffff; + long long t5; + + if (t1 & (1 << 15)) + t1 -= 1 << 16; + if (t2 & (1 << 15)) + t2 -= 1 << 16; + if (t3 & (1 << 15)) + t3 -= 1 << 16; + if (t4 & (1 << 15)) + t4 -= 1 << 16; + t1 *= t2; + t5 = t1; + if (t5 & (1 << 31)) + t5 -= 1ULL << 32; + state->Accumulator += t5; + t3 *= t4; + t5 = t3; + if (t5 & (1 << 31)) + t5 -= 1ULL << 32; + state->Accumulator += t5; + goto donext; + } + break; case 0x3: - { - /* XScale MIAxy instruction. */ - ARMword t1; - ARMword t2; - long long t5; - - if (BIT (17)) - t1 = state->Reg[MULLHSReg] >> 16; - else - t1 = state->Reg[MULLHSReg] & 0xffff; - - if (BIT (16)) - t2 = state->Reg[MULACCReg] >> 16; - else - t2 = state->Reg[MULACCReg] & 0xffff; - - if (t1 & (1 << 15)) - t1 -= 1 << 16; - if (t2 & (1 << 15)) - t2 -= 1 << 16; - t1 *= t2; - t5 = t1; - if (t5 & (1 << 31)) - t5 -= 1ULL << 32; - state->Accumulator += t5; - } - goto donext; + if (BITS (4, 11) == 1) + { + /* XScale MIAxy instruction. */ + ARMword t1; + ARMword t2; + long long t5; + + if (BIT (17)) + t1 = state->Reg[MULLHSReg] >> 16; + else + t1 = state->Reg[MULLHSReg] & 0xffff; + + if (BIT (16)) + t2 = state->Reg[MULACCReg] >> 16; + else + t2 = state->Reg[MULACCReg] & 0xffff; + + if (t1 & (1 << 15)) + t1 -= 1 << 16; + if (t2 & (1 << 15)) + t2 -= 1 << 16; + t1 *= t2; + t5 = t1; + if (t5 & (1 << 31)) + t5 -= 1ULL << 32; + state->Accumulator += t5; + goto donext; + } + break; default: break; |