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| author | Oleg Endo <olegendo@gcc.gnu.org> | 2016-04-09 10:24:00 +0900 |
|---|---|---|
| committer | Oleg Endo <olegendo@gcc.gnu.org> | 2016-04-09 10:24:00 +0900 |
| commit | 417a667c4afc1e04ba2caadc3f4051e0590585bb (patch) | |
| tree | 23969bc172c2172f1a3aafde7ada4bb44ad2cdc7 /sim | |
| parent | 9f5a6a60d9858f54d95443a2adf7d8077ee1528b (diff) | |
| download | fsf-binutils-gdb-417a667c4afc1e04ba2caadc3f4051e0590585bb.zip fsf-binutils-gdb-417a667c4afc1e04ba2caadc3f4051e0590585bb.tar.gz fsf-binutils-gdb-417a667c4afc1e04ba2caadc3f4051e0590585bb.tar.bz2 | |
Adjust default memory size and stack base address for SH simulator.
ld/ChangeLog:
* sh/interp.c (sim_memory_size): Default init to 30.
(parse_and_set_memory_size): Adjust upper bound to 31.
sim/ChangeLog:
* sh/interp.c (sim_memory_size): Default init to 30.
(parse_and_set_memory_size): Adjust upper bound to 31.
Diffstat (limited to 'sim')
| -rw-r--r-- | sim/ChangeLog | 5 | ||||
| -rw-r--r-- | sim/sh/interp.c | 6 |
2 files changed, 8 insertions, 3 deletions
diff --git a/sim/ChangeLog b/sim/ChangeLog index 76c384d..c316d17 100644 --- a/sim/ChangeLog +++ b/sim/ChangeLog @@ -1,3 +1,8 @@ +2016-04-09 Oleg Endo <olegendo@gcc.gnu.org> + + * sh/interp.c (sim_memory_size): Default init to 30. + (parse_and_set_memory_size): Adjust upper bound to 31. + 2016-02-03 Maciej W. Rozycki <macro@linux-mips.org> * MAINTAINERS (Past sim maintainers): Add Thiemo Seufer. diff --git a/sim/sh/interp.c b/sim/sh/interp.c index df29f96..46701e2 100644 --- a/sim/sh/interp.c +++ b/sim/sh/interp.c @@ -722,7 +722,7 @@ do { \ #if defined(__GO32__) int sim_memory_size = 19; #else -int sim_memory_size = 24; +int sim_memory_size = 30; #endif static int sim_profile_size = 17; @@ -2477,10 +2477,10 @@ parse_and_set_memory_size (SIM_DESC sd, const char *str) int n; n = strtol (str, NULL, 10); - if (n > 0 && n <= 24) + if (n > 0 && n <= 31) sim_memory_size = n; else - sim_io_printf (sd, "Bad memory size %d; must be 1 to 24, inclusive\n", n); + sim_io_printf (sd, "Bad memory size %d; must be 1 to 31, inclusive\n", n); } SIM_RC |