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authorAndrew Cagney <cagney@redhat.com>1997-07-29 00:57:39 +0000
committerAndrew Cagney <cagney@redhat.com>1997-07-29 00:57:39 +0000
commitf1bea83b2b6ec2d432299f6fea7567320375cf08 (patch)
treef75ea40d9affd1ff34853249e8f4ca6dd298da46 /sim
parente42b2520842a3cbafa2afd9fc3809f9cfc5debfb (diff)
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Add test for "mtsa"
Diffstat (limited to 'sim')
-rw-r--r--sim/testsuite/mips64vr5900el-elf/ChangeLog4
-rw-r--r--sim/testsuite/mips64vr5900el-elf/Makefile.in1
-rw-r--r--sim/testsuite/mips64vr5900el-elf/t-mtsa.s11
3 files changed, 16 insertions, 0 deletions
diff --git a/sim/testsuite/mips64vr5900el-elf/ChangeLog b/sim/testsuite/mips64vr5900el-elf/ChangeLog
index a6ad061..444ff9a 100644
--- a/sim/testsuite/mips64vr5900el-elf/ChangeLog
+++ b/sim/testsuite/mips64vr5900el-elf/ChangeLog
@@ -1,3 +1,7 @@
+Tue Jul 29 10:56:53 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * t-mtsa.s: Check move/from SA instructions.
+
Mon Jul 28 20:51:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
* t-pdivuw.s: Also check normal cases.
diff --git a/sim/testsuite/mips64vr5900el-elf/Makefile.in b/sim/testsuite/mips64vr5900el-elf/Makefile.in
index 2efdd7a..849efb3 100644
--- a/sim/testsuite/mips64vr5900el-elf/Makefile.in
+++ b/sim/testsuite/mips64vr5900el-elf/Makefile.in
@@ -82,6 +82,7 @@ TESTS = \
hello.ok \
exit47.ko \
\
+ t-mtsa.ok \
t-paddb.ok \
t-paddsb.ok \
t-paddsh.ok \
diff --git a/sim/testsuite/mips64vr5900el-elf/t-mtsa.s b/sim/testsuite/mips64vr5900el-elf/t-mtsa.s
new file mode 100644
index 0000000..04ad529
--- /dev/null
+++ b/sim/testsuite/mips64vr5900el-elf/t-mtsa.s
@@ -0,0 +1,11 @@
+.include "t-macros.i"
+
+ start
+
+test_mtsa:
+ load $9 0x0000000000000000 0x0000000000000020 # 32
+ mtsa $9
+ mfsa $10 #Expectation rd:0x20
+ check10 0x0000000000000000 0x0000000000000020
+
+ exit0