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author | Andrew Cagney <cagney@redhat.com> | 1997-07-14 16:53:04 +0000 |
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committer | Andrew Cagney <cagney@redhat.com> | 1997-07-14 16:53:04 +0000 |
commit | d9c61e839197ff0595fb9b3fc658b51e300b5772 (patch) | |
tree | 51f2fb05c97a83543fc488725113e7bfba6cc20c /sim | |
parent | 54a3aefcb634ace0bf931cf6073157f2000ba3a7 (diff) | |
download | fsf-binutils-gdb-d9c61e839197ff0595fb9b3fc658b51e300b5772.zip fsf-binutils-gdb-d9c61e839197ff0595fb9b3fc658b51e300b5772.tar.gz fsf-binutils-gdb-d9c61e839197ff0595fb9b3fc658b51e300b5772.tar.bz2 |
Standard simulator tests.
Diffstat (limited to 'sim')
-rw-r--r-- | sim/testsuite/d30v-elf/exit47.s | 4 | ||||
-rw-r--r-- | sim/testsuite/d30v-elf/hello.s | 9 | ||||
-rw-r--r-- | sim/testsuite/d30v-elf/loop.s | 1 | ||||
-rw-r--r-- | sim/testsuite/d30v-elf/tick.s | 51 |
4 files changed, 65 insertions, 0 deletions
diff --git a/sim/testsuite/d30v-elf/exit47.s b/sim/testsuite/d30v-elf/exit47.s new file mode 100644 index 0000000..9830ffb --- /dev/null +++ b/sim/testsuite/d30v-elf/exit47.s @@ -0,0 +1,4 @@ +# Verify r2 = 47; exit(r47) works + add r2, r0, 47 + .long 0x0e000004 + nop diff --git a/sim/testsuite/d30v-elf/hello.s b/sim/testsuite/d30v-elf/hello.s new file mode 100644 index 0000000..261629e --- /dev/null +++ b/sim/testsuite/d30v-elf/hello.s @@ -0,0 +1,9 @@ + + add r2, r0, hello + # putstr + .long 0x0e000001, 0x00f00000 + # finished + add r2, r0, r0 || nop + .long 0x0e000004, 0x00f00000 + +hello: .ascii "Hello World\r\n" diff --git a/sim/testsuite/d30v-elf/loop.s b/sim/testsuite/d30v-elf/loop.s new file mode 100644 index 0000000..69f2692 --- /dev/null +++ b/sim/testsuite/d30v-elf/loop.s @@ -0,0 +1 @@ +loop: bra loop diff --git a/sim/testsuite/d30v-elf/tick.s b/sim/testsuite/d30v-elf/tick.s new file mode 100644 index 0000000..d834ca7 --- /dev/null +++ b/sim/testsuite/d30v-elf/tick.s @@ -0,0 +1,51 @@ + .globl _start + # + # NOTE: Registers r10-r11 are reserved for the interrupt handler + # while the others can be used by the main loop/start code. + +_start: + # patch the external interrupt handlers entry + add r1, r0, handler + ldw r2, @(r1, 0) + ldw r3, @(r1, 4) + add r1, r0, 0xfffff138 + stw r2, @(r1, 0) + stw r3, @(r1, 4) + + # enable external interrupts - cr0 == PSW + mvfsys r2, cr0 + or r2, r0, 0x04000000 + mvtsys cr0, r2 + + + # wait for flag to be set +loop: + add r2, r0, flag + ldw r3, @(r2, 0) + bratzr r3, loop + + # clear the flag + stw r0, @(r2, 0) + + add r2, r0, tick + # putstr + .long 0x0e000001, 0x00f00000 + + bra loop + + # finished + add r2, r0, r0 || nop + .long 0x0e000004, 0x00f00000 + + +handler: + jmp real_handler +real_handler: + add r10, r0, 1 + add r11, r0, flag + stb r10, @(r11,0) + reit + + +flag: .long 0 +tick: .ascii "Tick\r\n" |