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author | Joyce Janczyn <janczyn@cygnus> | 1998-08-26 13:37:56 +0000 |
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committer | Joyce Janczyn <janczyn@cygnus> | 1998-08-26 13:37:56 +0000 |
commit | cf83964e6f6a002262b85911708bea5822ea8bb5 (patch) | |
tree | 731751d80fe2c20111c197ae907526b701f19fda /sim | |
parent | ef4d20e91566e7f6ee7133ccee235f6922bd6df5 (diff) | |
download | fsf-binutils-gdb-cf83964e6f6a002262b85911708bea5822ea8bb5.zip fsf-binutils-gdb-cf83964e6f6a002262b85911708bea5822ea8bb5.tar.gz fsf-binutils-gdb-cf83964e6f6a002262b85911708bea5822ea8bb5.tar.bz2 |
Regress yesterday's change to jmp instn implementation in mn10300.igen.
Diffstat (limited to 'sim')
-rw-r--r-- | sim/mn10300/ChangeLog | 5 |
1 files changed, 0 insertions, 5 deletions
diff --git a/sim/mn10300/ChangeLog b/sim/mn10300/ChangeLog index 1278b76..c5a460b 100644 --- a/sim/mn10300/ChangeLog +++ b/sim/mn10300/ChangeLog @@ -3,11 +3,6 @@ Wed Aug 26 09:29:38 1998 Joyce Janczyn <janczyn@cygnus.com> * mn10300.igen (div,divu): Fix divide instructions so divide by 0 behaves like the hardware. -Tue Aug 25 16:46:59 1998 Joyce Janczyn <janczyn@cygnus.com> - - * mn10300.igen (OP_F0F4): Need to load contents of register AN0 - for jmp. - Mon Aug 24 11:50:09 1998 Joyce Janczyn <janczyn@cygnus.com> * sim-main.h (SIM_HANDLES_LMA): Define SIM_HANDLES_LMA. |