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author | Nelson Chu <nelson.chu@sifive.com> | 2021-01-26 18:02:38 +0800 |
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committer | Nelson Chu <nelson.chu@sifive.com> | 2021-02-19 11:44:49 +0800 |
commit | 5a9f5403c75c8ae1f4935a9a0904949f52d9e3aa (patch) | |
tree | 7fd17df7fe3b4eb80cb7dc6d03087b7a5c04857a /sim | |
parent | 2f973f134d7752cbc662ec65da8ad8bbe4c6fb8f (diff) | |
download | fsf-binutils-gdb-5a9f5403c75c8ae1f4935a9a0904949f52d9e3aa.zip fsf-binutils-gdb-5a9f5403c75c8ae1f4935a9a0904949f52d9e3aa.tar.gz fsf-binutils-gdb-5a9f5403c75c8ae1f4935a9a0904949f52d9e3aa.tar.bz2 |
RISC-V: PR27158, fixed UJ/SB types and added CSS/CL/CS types for .insn.
* Renamed obsolete UJ/SB types and RVC types, also added CSS/CL(CS) types,
[VALID/EXTRACT/ENCODE macros]
BTYPE_IMM: Renamed from SBTYPE_IMM.
JTYPE_IMM: Renamed from UJTYPE_IMM.
CITYPE_IMM: Renamed from RVC_IMM.
CITYPE_LUI_IMM: Renamed from RVC_LUI_IMM.
CITYPE_ADDI16SP_IMM: Renamed from RVC_ADDI16SP_IMM.
CITYPE_LWSP_IMM: Renamed from RVC_LWSP_IMM.
CITYPE_LDSP_IMM: Renamed from RVC_LDSP_IMM.
CIWTYPE_IMM: Renamed from RVC_UIMM8.
CIWTYPE_ADDI4SPN_IMM: Renamed from RVC_ADDI4SPN_IMM.
CSSTYPE_IMM: Added for .insn without special encoding.
CSSTYPE_SWSP_IMM: Renamed from RVC_SWSP_IMM.
CSSTYPE_SDSP_IMM: Renamed from RVC_SDSP_IMM.
CLTYPE_IMM: Added for .insn without special encoding.
CLTYPE_LW_IMM: Renamed from RVC_LW_IMM.
CLTYPE_LD_IMM: Renamed from RVC_LD_IMM.
RVC_SIMM3: Unused and removed.
CBTYPE_IMM: Renamed from RVC_B_IMM.
CJTYPE_IMM: Renamed from RVC_J_IMM.
* Added new operands and removed the unused ones,
C5: Unsigned CL(CS) immediate, added for .insn directive.
C6: Unsigned CSS immediate, added for .insn directive.
Ci: Unused and removed.
C<: Unused and removed.
bfd/
PR 27158
* elfnn-riscv.c (perform_relocation): Updated encoding macros.
(_bfd_riscv_relax_call): Likewise.
(_bfd_riscv_relax_lui): Likewise.
* elfxx-riscv.c (howto_table): Likewise.
gas/
PR 27158
* config/tc-riscv.c (riscv_ip): Updated encoding macros.
(md_apply_fix): Likewise.
(md_convert_frag_branch): Likewise.
(validate_riscv_insn): Likewise. Also arranged operands, including
added C5 and C6 operands, and removed unused Ci and C< operands.
* doc/c-riscv.texi: Updated and added CSS/CL/CS types.
* testsuite/gas/riscv/insn.d: Added CSS/CL/CS instructions.
* testsuite/gas/riscv/insn.s: Likewise.
gdb/
PR 27158
* riscv-tdep.c (decode_ci_type_insn): Updated encoding macros.
(decode_j_type_insn): Likewise.
(decode_cj_type_insn): Likewise.
(decode_b_type_insn): Likewise.
(decode): Likewise.
include/
PR 27158
* opcode/riscv.h: Updated encoding macros.
opcodes/
PR 27158
* riscv-dis.c (print_insn_args): Updated encoding macros.
* riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM.
(match_c_addi16sp): Updated encoding macros.
(match_c_lui): Likewise.
(match_c_lui_with_hint): Likewise.
(match_c_addi4spn): Likewise.
(match_c_slli): Likewise.
(match_slli_as_c_slli): Likewise.
(match_c_slli64): Likewise.
(match_srxi_as_c_srxi): Likewise.
(riscv_insn_types): Added .insn css/cl/cs.
sim/
PR 27158
* riscv/sim-main.c (execute_i): Updated encoding macros.
Diffstat (limited to 'sim')
-rw-r--r-- | sim/ChangeLog | 5 | ||||
-rw-r--r-- | sim/riscv/sim-main.c | 6 |
2 files changed, 8 insertions, 3 deletions
diff --git a/sim/ChangeLog b/sim/ChangeLog index df11c5e..6bea868 100644 --- a/sim/ChangeLog +++ b/sim/ChangeLog @@ -1,3 +1,8 @@ +2021-02-19 Nelson Chu <nelson.chu@sifive.com> + + PR 27158 + * riscv/sim-main.c (execute_i): Updated encoding macros. + 2021-02-13 Mike Frysinger <vapier@gentoo.org> * configure.tgt: Delete call to AC_SUBST(sim_arch). diff --git a/sim/riscv/sim-main.c b/sim/riscv/sim-main.c index 8185bfc..ff328a0 100644 --- a/sim/riscv/sim-main.c +++ b/sim/riscv/sim-main.c @@ -157,7 +157,7 @@ execute_i (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op) unsigned_word i_imm = EXTRACT_ITYPE_IMM (iw); unsigned_word u_imm = EXTRACT_UTYPE_IMM ((unsigned64) iw); unsigned_word s_imm = EXTRACT_STYPE_IMM (iw); - unsigned_word sb_imm = EXTRACT_SBTYPE_IMM (iw); + unsigned_word sb_imm = EXTRACT_BTYPE_IMM (iw); unsigned_word shamt_imm = ((iw >> OP_SH_SHAMT) & OP_MASK_SHAMT); unsigned_word tmp; sim_cia pc = cpu->pc + 4; @@ -416,9 +416,9 @@ execute_i (SIM_CPU *cpu, unsigned_word iw, const struct riscv_opcode *op) break; case MATCH_JAL: TRACE_INSN (cpu, "jal %s, %" PRIiTW ";", rd_name, - EXTRACT_UJTYPE_IMM (iw)); + EXTRACT_JTYPE_IMM (iw)); store_rd (cpu, rd, cpu->pc + 4); - pc = cpu->pc + EXTRACT_UJTYPE_IMM (iw); + pc = cpu->pc + EXTRACT_JTYPE_IMM (iw); TRACE_BRANCH (cpu, "to %#" PRIxTW, pc); break; case MATCH_JALR: |