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| author | Mike Frysinger <vapier@gentoo.org> | 2023-12-07 21:38:11 -0700 |
|---|---|---|
| committer | Mike Frysinger <vapier@gentoo.org> | 2023-12-07 21:41:27 -0700 |
| commit | 190fcd0d6ce07abc4f6ad08d43a3dedd48b27b3e (patch) | |
| tree | 38f0119c2f40eb3476efe61d20ec3f074f1f9e9b /sim | |
| parent | ff46c180998fedb8277feaf502862bee7d847553 (diff) | |
| download | fsf-binutils-gdb-190fcd0d6ce07abc4f6ad08d43a3dedd48b27b3e.zip fsf-binutils-gdb-190fcd0d6ce07abc4f6ad08d43a3dedd48b27b3e.tar.gz fsf-binutils-gdb-190fcd0d6ce07abc4f6ad08d43a3dedd48b27b3e.tar.bz2 | |
sim: m32r: add more cgen prototypes for traps
The traps file uses a bunch of functions directly without prototypes,
and we can't safely include the relevant cpu*.h files for them.
Diffstat (limited to 'sim')
| -rw-r--r-- | sim/m32r/m32r-sim.h | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/sim/m32r/m32r-sim.h b/sim/m32r/m32r-sim.h index c72be52..875fc23 100644 --- a/sim/m32r/m32r-sim.h +++ b/sim/m32r/m32r-sim.h @@ -47,6 +47,18 @@ extern void m32rbf_model_insn_before (SIM_CPU *, int); extern void m32rbf_model_insn_after (SIM_CPU *, int, int); extern CPUREG_FETCH_FN m32rbf_fetch_register; extern CPUREG_STORE_FN m32rbf_store_register; +extern UQI m32rbf_h_psw_get (SIM_CPU *); +extern void m32rbf_h_psw_set (SIM_CPU *, UQI); +extern UQI m32r2f_h_psw_get (SIM_CPU *); +extern void m32r2f_h_psw_set (SIM_CPU *, UQI); +extern UQI m32rxf_h_psw_get (SIM_CPU *); +extern void m32rxf_h_psw_set (SIM_CPU *, UQI); +extern void m32rbf_h_bpsw_set (SIM_CPU *, UQI); +extern void m32r2f_h_bpsw_set (SIM_CPU *, UQI); +extern void m32rxf_h_bpsw_set (SIM_CPU *, UQI); +extern SI m32rbf_h_gr_get (SIM_CPU *, UINT); +extern void m32rbf_h_gr_set (SIM_CPU *, UINT, SI); +extern USI m32rbf_h_cr_get (SIM_CPU *, UINT); extern void m32rbf_h_cr_set (SIM_CPU *, UINT, USI); /* Cover macros for hardware accesses. |