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| author | Jim Wilson <jimw@sifive.com> | 2021-04-07 18:51:52 -0700 |
|---|---|---|
| committer | Jim Wilson <jimw@sifive.com> | 2021-04-07 18:51:52 -0700 |
| commit | 0592e80bcf1bbab2fbbb110ea395f9608e4f594c (patch) | |
| tree | b175364127540032ba3a64ca889ab5d67efa82ea /sim | |
| parent | bf5271659d0d78174041aa0e198406c9ecacc7a4 (diff) | |
| download | fsf-binutils-gdb-0592e80bcf1bbab2fbbb110ea395f9608e4f594c.zip fsf-binutils-gdb-0592e80bcf1bbab2fbbb110ea395f9608e4f594c.tar.gz fsf-binutils-gdb-0592e80bcf1bbab2fbbb110ea395f9608e4f594c.tar.bz2 | |
Aarch64 sim fix for gcc-10 miscompilation.
This fixes a problem that occurs when compiled by gcc-10, as the code
is relying on undefined overflow behavior. This is fixed by replacing
compares between 32-bit and 64-bit results with compares that just use
the 64-bit results with a cast.
PR sim/27483
* simulator.c (set_flags_for_add32): Compare uresult against
itself. Compare sresult against itself.
Diffstat (limited to 'sim')
| -rw-r--r-- | sim/aarch64/ChangeLog | 6 | ||||
| -rw-r--r-- | sim/aarch64/simulator.c | 4 |
2 files changed, 8 insertions, 2 deletions
diff --git a/sim/aarch64/ChangeLog b/sim/aarch64/ChangeLog index e667c47..d328fcd 100644 --- a/sim/aarch64/ChangeLog +++ b/sim/aarch64/ChangeLog @@ -1,3 +1,9 @@ +2021-04-07 Jim Wilson <jimw@sifive.com> + + PR sim/27483 + * simulator.c (set_flags_for_add32): Compare uresult against + itself. Compare sresult against itself. + 2021-04-02 Mike Frysinger <vapier@gentoo.org> * aclocal.m4, configure: Regenerate. diff --git a/sim/aarch64/simulator.c b/sim/aarch64/simulator.c index 6ba29a0..e0b428d 100644 --- a/sim/aarch64/simulator.c +++ b/sim/aarch64/simulator.c @@ -1650,10 +1650,10 @@ set_flags_for_add32 (sim_cpu *cpu, int32_t value1, int32_t value2) if (result & (1 << 31)) flags |= N; - if (uresult != (uint32_t)result) + if (uresult != (uint32_t)uresult) flags |= C; - if (sresult != result) + if (sresult != (int32_t)sresult) flags |= V; aarch64_set_CPSR (cpu, flags); |