Restrict ldsr (load system register) to modifying just non-reserved PSW bits.

For v850eq, include PSW[US] in bits that can be modified.

5 files changed, 55 insertions, 59 deletions

diff --git a/sim/v850/ChangeLog b/sim/v850/ChangeLog
index cdf2076..5e979d8 100644
--- a/sim/v850/ChangeLog
+++ b/sim/v850/ChangeLog
@@ -1,3 +1,15 @@
+Tue Sep 16 09:02:00 1997  Andrew Cagney  <cagney@b1.cygnus.com>
+
+	* sim-main.h (struct _sim_cpu): Add psw_mask so that reserved bits
+ 	can be masked out.
+
+	* simops.c (OP_2007E0, OP_4007E0): Move "ldsr", "stsr"
+ 	instructions from here.
+	* v850.igen (ldsr, stsr): To here.  Mask out reserved bits when
+ 	setting PSW.
+	
+	* interp.c (sim_open): Set psw_mask if machine known.
+
 Tue Sep 16 10:20:00 1997  Andrew Cagney  <cagney@b1.cygnus.com>
 
 start-sanitize-v850e
diff --git a/sim/v850/interp.c b/sim/v850/interp.c
index 1981cfb..3d7d866 100644
--- a/sim/v850/interp.c
+++ b/sim/v850/interp.c
@@ -220,10 +220,7 @@ sim_open (kind, cb, abfd, argv)
      char **argv;
 {
   SIM_DESC sd = sim_state_alloc (kind, cb);
-#if 0
-  struct simops *s;
-  struct hash_entry *h;
-#endif
+  int mach;
 
   /* for compatibility */
   simulator = sd;
@@ -285,26 +282,33 @@ sim_open (kind, cb, abfd, argv)
       return 0;
     }
 
-#if 0
-  /* put all the opcodes in the hash table */
-  for (s = Simops; s->func; s++)
-    {
-      h = &hash_table[hash(s->opcode)];
-      
-      /* go to the last entry in the chain */
-      while (h->next)
-	  h = h->next;
 
-      if (h->ops)
-	{
-	  h->next = (struct hash_entry *) calloc(1,sizeof(struct hash_entry));
-	  h = h->next;
-	}
-      h->ops = s;
-      h->mask = s->mask;
-      h->opcode = s->opcode;
+  /* determine the machine type */
+  if (STATE_ARCHITECTURE (sd) != NULL
+      && STATE_ARCHITECTURE (sd)->arch == bfd_arch_v850)
+    mach = STATE_ARCHITECTURE (sd)->mach;
+  else
+    mach = bfd_mach_v850; /* default */
+
+  /* set machine specific configuration */
+  switch (mach)
+    {
+    case bfd_mach_v850:
+      /* start-sanitize-v850e */
+    case bfd_mach_v850e:
+      /* end-sanitize-v850e */
+      STATE_CPU (sd, 0)->psw_mask = (PSW_NP | PSW_EP | PSW_ID | PSW_SAT
+				     | PSW_CY | PSW_OV | PSW_S | PSW_Z);
+      break;
+      /* start-sanitize-v850eq */
+    case bfd_mach_v850eq:
+      PSW |= PSW_US;
+      STATE_CPU (sd, 0)->psw_mask = (PSW_US
+				     | PSW_NP | PSW_EP | PSW_ID | PSW_SAT
+				     | PSW_CY | PSW_OV | PSW_S | PSW_Z);
+      break;
+      /* end-sanitize-v850eq */
     }
-#endif
 
   return sd;
 }
diff --git a/sim/v850/sim-main.h b/sim/v850/sim-main.h
index d222282..f7222a1 100644
--- a/sim/v850/sim-main.h
+++ b/sim/v850/sim-main.h
@@ -48,6 +48,7 @@ struct _sim_cpu
 {
   /* ... simulator specific members ... */
   v850_regs reg;
+  reg_t psw_mask;               /* only allow non-reserved bits to be set */
   /* ... base type ... */
   sim_cpu_base base;
 };
diff --git a/sim/v850/simops.c b/sim/v850/simops.c
index 2cc54e4..93b0407 100644
--- a/sim/v850/simops.c
+++ b/sim/v850/simops.c
@@ -1935,15 +1935,6 @@ OP_C7C0 ()
   return 4;
 }
 
-/* breakpoint */
-int
-OP_FFFF ()
-{
-  sim_engine_halt (simulator, STATE_CPU (simulator, 0), NULL, PC,
-		   sim_stopped, SIGTRAP);
-  return 0;
-}
-
 /* di */
 int
 OP_16007E0 ()
@@ -2299,32 +2290,6 @@ OP_10007E0 ()
     }
 }
 
-/* ldsr, reg,reg */
-int
-OP_2007E0 ()
-{
-  trace_input ("ldsr", OP_LDSR, 0);
-  
-  State.sregs[ OP[1] ] = State.regs[ OP[0] ];
-  
-  trace_output (OP_LDSR);
-
-  return 4;
-}
-
-/* stsr */
-int
-OP_4007E0 ()
-{
-  trace_input ("stsr", OP_STSR, 0);
-  
-  State.regs[ OP[1] ] = State.sregs[ OP[0] ];
-  
-  trace_output (OP_STSR);
-
-  return 4;
-}
-
 /* start-sanitize-v850e */
 /* tst1 reg2, [reg1] */
 int
diff --git a/sim/v850/v850.igen b/sim/v850/v850.igen
index 93bf0b7..e1f8556 100644
--- a/sim/v850/v850.igen
+++ b/sim/v850/v850.igen
@@ -545,7 +545,15 @@ rrrrr!0,111111,RRRRR + ddddddddddddddd,1:VII:::ld.hu
 rrrrr,111111,RRRRR + 0000000000100000:IX:::ldsr
 "ldsr r<reg1>, r<regID>"
 {
-  COMPAT_2 (OP_2007E0 ());
+  SAVE_2;
+  trace_input ("ldsr", OP_LDSR, 0);
+  
+  if (&PSW == &State.sregs[ regID ])
+    PSW = (State.regs[ reg1 ] & (CPU)->psw_mask);
+  else
+    State.sregs[ regID ] = State.regs[ reg1 ];
+  
+  trace_output (OP_LDSR);
 }
 
 
@@ -1047,7 +1055,13 @@ rrrrr,111011,RRRRR + ddddddddddddddd,1:VII:::st.w
 rrrrr,111111,RRRRR + 0000000001000000:IX:::stsr
 "stsr r<regID>, r<reg1>"
 {
-  COMPAT_2 (OP_4007E0 ());
+  SAVE_2;
+
+  trace_input ("stsr", OP_STSR, 0);
+  
+  State.regs[ reg1 ] = State.sregs[ regID ];
+  
+  trace_output (OP_STSR);
 }