diff options
| author | Andrew Cagney <cagney@redhat.com> | 1997-09-16 04:49:24 +0000 |
|---|---|---|
| committer | Andrew Cagney <cagney@redhat.com> | 1997-09-16 04:49:24 +0000 |
| commit | c7db488f71fb6faf5d327edb3517a879de35ceea (patch) | |
| tree | 733ea5ee31bd4e41d74a82d63a163bd79562abf7 /sim/v850/v850.igen | |
| parent | 896e248fe06ea228be115540fffec18644db6270 (diff) | |
| download | fsf-binutils-gdb-c7db488f71fb6faf5d327edb3517a879de35ceea.zip fsf-binutils-gdb-c7db488f71fb6faf5d327edb3517a879de35ceea.tar.gz fsf-binutils-gdb-c7db488f71fb6faf5d327edb3517a879de35ceea.tar.bz2 | |
Restrict ldsr (load system register) to modifying just non-reserved PSW bits.
For v850eq, include PSW[US] in bits that can be modified.
Diffstat (limited to 'sim/v850/v850.igen')
| -rw-r--r-- | sim/v850/v850.igen | 18 |
1 files changed, 16 insertions, 2 deletions
diff --git a/sim/v850/v850.igen b/sim/v850/v850.igen index 93bf0b7..e1f8556 100644 --- a/sim/v850/v850.igen +++ b/sim/v850/v850.igen @@ -545,7 +545,15 @@ rrrrr!0,111111,RRRRR + ddddddddddddddd,1:VII:::ld.hu rrrrr,111111,RRRRR + 0000000000100000:IX:::ldsr "ldsr r<reg1>, r<regID>" { - COMPAT_2 (OP_2007E0 ()); + SAVE_2; + trace_input ("ldsr", OP_LDSR, 0); + + if (&PSW == &State.sregs[ regID ]) + PSW = (State.regs[ reg1 ] & (CPU)->psw_mask); + else + State.sregs[ regID ] = State.regs[ reg1 ]; + + trace_output (OP_LDSR); } @@ -1047,7 +1055,13 @@ rrrrr,111011,RRRRR + ddddddddddddddd,1:VII:::st.w rrrrr,111111,RRRRR + 0000000001000000:IX:::stsr "stsr r<regID>, r<reg1>" { - COMPAT_2 (OP_4007E0 ()); + SAVE_2; + + trace_input ("stsr", OP_STSR, 0); + + State.regs[ reg1 ] = State.sregs[ regID ]; + + trace_output (OP_STSR); } |