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| author | DJ Delorie <dj@redhat.com> | 2008-02-06 04:41:26 +0000 |
|---|---|---|
| committer | DJ Delorie <dj@redhat.com> | 2008-02-06 04:41:26 +0000 |
| commit | 98e460c30d2f5e3848d7ae429bebcce3b8c90b81 (patch) | |
| tree | 40dbef44e0edc002f1f39fd3fd7f5efd0d32a8a3 /sim/v850/simops.c | |
| parent | 1a4ca44aeb9dbeed9848d1703a3c4ddae5cb6ffe (diff) | |
| download | fsf-binutils-gdb-98e460c30d2f5e3848d7ae429bebcce3b8c90b81.zip fsf-binutils-gdb-98e460c30d2f5e3848d7ae429bebcce3b8c90b81.tar.gz fsf-binutils-gdb-98e460c30d2f5e3848d7ae429bebcce3b8c90b81.tar.bz2 | |
* simops.c (OP_1C007E0): Compensate for 64 bit hosts.
(OP_18007E0): Likewise.
(OP_2C007E0): Likewise.
(OP_28007E0): Likewise.
* v850.igen (divh): Likewise.
Diffstat (limited to 'sim/v850/simops.c')
| -rw-r--r-- | sim/v850/simops.c | 16 |
1 files changed, 9 insertions, 7 deletions
diff --git a/sim/v850/simops.c b/sim/v850/simops.c index 5513341..49f1200 100644 --- a/sim/v850/simops.c +++ b/sim/v850/simops.c @@ -2209,8 +2209,8 @@ OP_1C007E0 (void) imm5 = 32 - ((OP[3] & 0x3c0000) >> 17); - divide_by = State.regs[ OP[0] ]; - divide_this = State.regs[ OP[1] ] << imm5; + divide_by = (signed32) State.regs[ OP[0] ]; + divide_this = (signed32) (State.regs[ OP[1] ] << imm5); divn (imm5, divide_by, divide_this, & quotient, & remainder, & overflow); @@ -2280,7 +2280,7 @@ OP_18007E0 (void) imm5 = 32 - ((OP[3] & 0x3c0000) >> 17); divide_by = EXTEND16 (State.regs[ OP[0] ]); - divide_this = State.regs[ OP[1] ] << imm5; + divide_this = (signed32) (State.regs[ OP[1] ] << imm5); divn (imm5, divide_by, divide_this, & quotient, & remainder, & overflow); @@ -2351,14 +2351,14 @@ OP_2C007E0 (void) /* Compute the result. */ - divide_by = State.regs[ OP[0] ]; + divide_by = (signed32) State.regs[ OP[0] ]; divide_this = State.regs[ OP[1] ]; if (divide_by == 0) { PSW |= PSW_OV; } - else if (divide_by == -1 && divide_this == (1 << 31)) + else if (divide_by == -1 && divide_this == (1L << 31)) { PSW &= ~PSW_Z; PSW |= PSW_OV | PSW_S; @@ -2367,9 +2367,10 @@ OP_2C007E0 (void) } else { + divide_this = (signed32) divide_this; State.regs[ OP[1] ] = quotient = divide_this / divide_by; State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by; - + /* Set condition codes. */ PSW &= ~(PSW_Z | PSW_S | PSW_OV); @@ -2442,7 +2443,7 @@ OP_28007E0 (void) { PSW |= PSW_OV; } - else if (divide_by == -1 && divide_this == (1 << 31)) + else if (divide_by == -1 && divide_this == (1L << 31)) { PSW &= ~PSW_Z; PSW |= PSW_OV | PSW_S; @@ -2451,6 +2452,7 @@ OP_28007E0 (void) } else { + divide_this = (signed32) divide_this; State.regs[ OP[1] ] = quotient = divide_this / divide_by; State.regs[ OP[2] >> 11 ] = remainder = divide_this % divide_by; |