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| author | Andrew Cagney <cagney@redhat.com> | 1997-09-08 17:23:16 +0000 |
|---|---|---|
| committer | Andrew Cagney <cagney@redhat.com> | 1997-09-08 17:23:16 +0000 |
| commit | 70c8abdb4cf6fc5f3e9d7374491997bce1048100 (patch) | |
| tree | b62dea0b06aa8dfb3e3f51e5d0b7915c2d422bd7 /sim/tic80/cpu.h | |
| parent | 75faf9aecb2023ca625dd5cbdd667e134071cf9f (diff) | |
| download | fsf-binutils-gdb-70c8abdb4cf6fc5f3e9d7374491997bce1048100.zip fsf-binutils-gdb-70c8abdb4cf6fc5f3e9d7374491997bce1048100.tar.gz fsf-binutils-gdb-70c8abdb4cf6fc5f3e9d7374491997bce1048100.tar.bz2 | |
Use updated MSMASK, MSMASKED macros.
Fix sat problem in d30v.
Diffstat (limited to 'sim/tic80/cpu.h')
| -rw-r--r-- | sim/tic80/cpu.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/sim/tic80/cpu.h b/sim/tic80/cpu.h index ca2d327..e710364 100644 --- a/sim/tic80/cpu.h +++ b/sim/tic80/cpu.h @@ -151,6 +151,8 @@ struct _sim_cpu { sim_cpu_base base; }; +#define CPU_CIA(CPU) ((CPU)->cia) + #define GPR(N) ((CPU)->reg[N]) #define GPR_SET(N, VAL) ((CPU)->reg[N] = (VAL)) #define ACC(N) ((CPU)->acc[N]) |