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author | Jim Wilson <jim.wilson@linaro.org> | 2017-01-17 16:01:40 -0800 |
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committer | Jim Wilson <jim.wilson@linaro.org> | 2017-01-17 16:11:09 -0800 |
commit | 05b3d79d265aa9de2a81ac2d0f5e6f5821161f34 (patch) | |
tree | e6e003e2f85da81fdc73ee6a4b209170a2ada370 /sim/testsuite | |
parent | 11741d50eff1424bb1f628ede3dfe42a74343b52 (diff) | |
download | fsf-binutils-gdb-05b3d79d265aa9de2a81ac2d0f5e6f5821161f34.zip fsf-binutils-gdb-05b3d79d265aa9de2a81ac2d0f5e6f5821161f34.tar.gz fsf-binutils-gdb-05b3d79d265aa9de2a81ac2d0f5e6f5821161f34.tar.bz2 |
Fixes for addv and xtn2 instructions.
sim/aarch64/
* simulator.c (do_vec_ADDV): Call aarch64_set_vec_u64 instead of
aarch64_set_reg_u64. In case 2, call HALT_UNALLOC if not full. In
case 3, call HALT_UNALLOC unconditionally.
(do_vec_XTN): Delete shifts. In case 2, change index from i + 4 to
i + 2. Delete if on bias, change index to i + bias * X.
sim/testsuite/sim/aarch64/
* addv.s: New.
* xtn.s: New.
Diffstat (limited to 'sim/testsuite')
-rw-r--r-- | sim/testsuite/sim/aarch64/ChangeLog | 5 | ||||
-rw-r--r-- | sim/testsuite/sim/aarch64/addv.s | 50 | ||||
-rw-r--r-- | sim/testsuite/sim/aarch64/xtn.s | 79 |
3 files changed, 134 insertions, 0 deletions
diff --git a/sim/testsuite/sim/aarch64/ChangeLog b/sim/testsuite/sim/aarch64/ChangeLog index b756603..7e48dd1 100644 --- a/sim/testsuite/sim/aarch64/ChangeLog +++ b/sim/testsuite/sim/aarch64/ChangeLog @@ -1,3 +1,8 @@ +2017-01-17 Jim Wilson <jim.wilson@linaro.org> + + * addv.s: New. + * xtn.s: New. + 2017-01-09 Jim Wilson <jim.wilson@linaro.org> * uzp.s: New. diff --git a/sim/testsuite/sim/aarch64/addv.s b/sim/testsuite/sim/aarch64/addv.s new file mode 100644 index 0000000..4da8935 --- /dev/null +++ b/sim/testsuite/sim/aarch64/addv.s @@ -0,0 +1,50 @@ +# mach: aarch64 + +# Check the add across vector instruction: addv. + +.include "testutils.inc" + + .data + .align 4 +input: + .word 0x04030201 + .word 0x08070605 + .word 0x0c0b0a09 + .word 0x100f0e0d + + start + adrp x0, input + ldr q0, [x0, #:lo12:input] + + addv b1, v0.8b + mov x1, v1.d[0] + cmp x1, #36 + bne .Lfailure + + addv b1, v0.16b + mov x1, v1.d[0] + cmp x1, #136 + bne .Lfailure + + addv h1, v0.4h + mov x1, v1.d[0] + mov x2, #5136 + cmp x1, x2 + bne .Lfailure + + addv h1, v0.8h + mov x1, v1.d[0] + mov x2, #18496 + cmp x1, x2 + bne .Lfailure + + addv s1, v0.4s + mov x1, v1.d[0] + mov x2, 8220 + movk x2, 0x2824, lsl 16 + cmp x1, x2 + bne .Lfailure + + pass +.Lfailure: + fail diff --git a/sim/testsuite/sim/aarch64/xtn.s b/sim/testsuite/sim/aarch64/xtn.s new file mode 100644 index 0000000..de369f7 --- /dev/null +++ b/sim/testsuite/sim/aarch64/xtn.s @@ -0,0 +1,79 @@ +# mach: aarch64 + +# Check the extract narrow instructions: xtn, xtn2. + +.include "testutils.inc" + + .data + .align 4 +input: + .word 0x04030201 + .word 0x08070605 + .word 0x0c0b0a09 + .word 0x100f0e0d +input2: + .word 0x14131211 + .word 0x18171615 + .word 0x1c1b1a19 + .word 0x201f1e1d +x16b: + .word 0x07050301 + .word 0x0f0d0b09 + .word 0x17151311 + .word 0x1f1d1b19 +x8h: + .word 0x06050201 + .word 0x0e0d0a09 + .word 0x16151211 + .word 0x1e1d1a19 +x4s: + .word 0x04030201 + .word 0x0c0b0a09 + .word 0x14131211 + .word 0x1c1b1a19 + + start + adrp x0, input + ldr q0, [x0, #:lo12:input] + adrp x0, input2 + ldr q1, [x0, #:lo12:input2] + + xtn v2.8b, v0.8h + xtn2 v2.16b, v1.8h + mov x1, v2.d[0] + mov x2, v2.d[1] + adrp x3, x16b + ldr x4, [x3, #:lo12:x16b] + cmp x1, x4 + bne .Lfailure + ldr x5, [x3, #:lo12:x16b+8] + cmp x2, x5 + bne .Lfailure + + xtn v2.4h, v0.4s + xtn2 v2.8h, v1.4s + mov x1, v2.d[0] + mov x2, v2.d[1] + adrp x3, x8h + ldr x4, [x3, #:lo12:x8h] + cmp x1, x4 + bne .Lfailure + ldr x5, [x3, #:lo12:x8h+8] + cmp x2, x5 + bne .Lfailure + + xtn v2.2s, v0.2d + xtn2 v2.4s, v1.2d + mov x1, v2.d[0] + mov x2, v2.d[1] + adrp x3, x4s + ldr x4, [x3, #:lo12:x4s] + cmp x1, x4 + bne .Lfailure + ldr x5, [x3, #:lo12:x4s+8] + cmp x2, x5 + bne .Lfailure + + pass +.Lfailure: + fail |